Literatura académica sobre el tema "10T SRAM CELL"
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Artículos de revistas sobre el tema "10T SRAM CELL"
Elangovan, M. y K. Gunavathi. "High Stable and Low Power 10T CNTFET SRAM Cell". Journal of Circuits, Systems and Computers 29, n.º 10 (19 de diciembre de 2019): 2050158. http://dx.doi.org/10.1142/s0218126620501583.
Texto completoReddy Gujjula, Nagarjuna y Rameshbabu Kellampalli. "Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor". International Journal of Scientific Methods in Engineering and Management 01, n.º 01 (2023): 47–57. http://dx.doi.org/10.58599/ijsmem.2023.1105.
Texto completoGanesh, Chokkakula y Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell". Active and Passive Electronic Components 2023 (30 de junio de 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.
Texto completoRao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak y Baseem Khan. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications". Journal of Electrical and Computer Engineering 2023 (7 de junio de 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.
Texto completoIslam, A. y M. Hasan. "Leakage Characterization of 10T SRAM Cell". IEEE Transactions on Electron Devices 59, n.º 3 (marzo de 2012): 631–38. http://dx.doi.org/10.1109/ted.2011.2181387.
Texto completoChaurasia, Ranu, Brijesh Kumar, Sudhanshu Verma y Akhilesh Kumar. "Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques". IOP Conference Series: Materials Science and Engineering 1272, n.º 1 (1 de diciembre de 2022): 012007. http://dx.doi.org/10.1088/1757-899x/1272/1/012007.
Texto completoLiu, Changjun, Hongxia Liu y Jianye Yang. "A Novel Low-Power and Soft Error Recovery 10T SRAM Cell". Micromachines 14, n.º 4 (13 de abril de 2023): 845. http://dx.doi.org/10.3390/mi14040845.
Texto completoZhou, Hong Gang, Qiang Song, Chun Yu Peng y Shou Biao Tan. "A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture". Applied Mechanics and Materials 263-266 (diciembre de 2012): 9–14. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.9.
Texto completoSingh, Arjun y Sangeeta Nakhte. "Optimized High Performance 10T SRAM Cell Characterization". International Journal of Computer Applications 134, n.º 5 (15 de enero de 2016): 29–33. http://dx.doi.org/10.5120/ijca2016907964.
Texto completoGupta, Neha, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl y Patrick Girard. "Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications". Electronics 10, n.º 14 (17 de julio de 2021): 1718. http://dx.doi.org/10.3390/electronics10141718.
Texto completoTesis sobre el tema "10T SRAM CELL"
Lo, Cheng-Hung y 羅正鴻. "A PPN Based 10T Sub-threshold SRAM Cell with Low Leakage and Differential Sensing". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/39470329821328407138.
Texto completo國立清華大學
電機工程學系
98
In this thesis, we propose a P-P-N inverter based differential 10T SRAM cell capable of providing low power operation. Since cell stability is especially vulnerable to noise at sub-threshold voltage, the proposed cell avoids read disturb, improving cell stability significantly. Without cell stability concern, we strengthen the access transistors to ensure cell writability by employing reverse short channel effect. As transistor leakage becomes more prominent in nanometer technology, we introduce VGND biasing scheme to reduce the impact of data-dependent leakage current. Without complicate wordline control, the proposed cell allows multi-word on a wordline to increase cell density and to enable efficient error correction code (ECC). To verify the proposed cell, a 16Kb array of the proposed cell is fabricated in 90nm CMOS technology. For comparison, we also fabricate 2Kb array of previous work in our chip. Supply voltage for array and peripheral is separated to enable periphery voltage boosting and to measure the cell array leakage. Applying higher peripheral voltage not only enhances the chip operating speed but also resolve the operating limitation at low voltage while the cell array still operates at lower voltage, reducing leakage power significantly. Measurement results show the 16Kb array of the proposed cell can work successfully down to 285mV. By boosting periphery voltage to 0.4V, the proposed cell can work at a lower (265mV) voltage and operate at a higher frequency. The entire 16Kb array consumes 2.6uW leakage power at 300mV. After normalization, our cell consumes only 0.2X leakage current compared to previous work.
YADAV, PUNEET. "DESIGN AND ANALYSIS OF A LOW POWER AND HIGH PERFORMANCE 10T SRAM CELL AT 32 NM TECHNOLOGY NODE". Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19835.
Texto completoCapítulos de libros sobre el tema "10T SRAM CELL"
Gupta, Vinay, Pratiksha Shukla y Manisha Pattanaik. "Low Leakage Noise Tolerant 10T SRAM Cell". En Communications in Computer and Information Science, 538–50. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5950-7_45.
Texto completoSharma, Deepika, Shilpi Birla y Neha Mathur. "Comparative Analysis of 10T SRAM Cell using Nanodevices". En Intelligent Computing Techniques for Smart Energy Systems, 133–41. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0252-9_13.
Texto completoManoj Kumar, R. y P. V. Sridevi. "Design of Low Standby Power 10T SRAM Cell with Improved Write Margin". En Lecture Notes in Electrical Engineering, 507–14. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-3828-5_53.
Texto completoSingh, Anushka, Yash Sharma, Arvind Sharma y Archana Pandey. "A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance". En Communications in Computer and Information Science, 523–31. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8_43.
Texto completoAakansha, G. S. Namith, A. Dinesh, A. Sai Ram, Shashank Kumar Dubey y Aminul Islam. "A Highly Reliable and Radiation-Hardened Majority PFET-Based 10T SRAM Cell". En Lecture Notes in Electrical Engineering, 113–22. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1570-2_11.
Texto completoJoshi, Vinod Kumar y Haniel Craig Lobo. "Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology". En Advanced Computing and Communication Technologies, 25–40. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1023-1_3.
Texto completoSingh, Kamini, R. S. Gamad y P. P. Bansod. "Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell". En Communications in Computer and Information Science, 541–49. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8_45.
Texto completoYadav, Vaishali y V. K. Tomar. "A Low Leakage with Enhanced Write Margin 10T SRAM Cell for IoT Applications". En Lecture Notes in Electrical Engineering, 201–11. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3767-4_19.
Texto completoSwaati y Bishnu Prasad Das. "A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications". En Communications in Computer and Information Science, 487–95. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_48.
Texto completoAhlawat, Siddhant, Siddharth, Bhawna Rawat y Poornima Mittal. "A Comparative Performance Analysis of Varied 10T SRAM Cell Topologies at 32 nm Technology Node". En Modeling, Simulation and Optimization, 63–75. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0836-1_5.
Texto completoActas de conferencias sobre el tema "10T SRAM CELL"
Kaur, Navneet, Neha Gupta, Hitesh Pahuja, Balwinder Singh y Sudhakar Panday. "Low Power FinFET based 10T SRAM cell". En 2016 Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH). IEEE, 2016. http://dx.doi.org/10.1109/cipech.2016.7918772.
Texto completoPrasad, Govind. "Novel low power 10T SRAM cell on 90nm CMOS". En 2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB). IEEE, 2016. http://dx.doi.org/10.1109/aeeicb.2016.7538408.
Texto completoBansal, Manav, Ankur Kumar, Priyanka Singh y R. K. Nagaria. "A Novel 10T SRAM cell for Low Power Applications". En 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON). IEEE, 2018. http://dx.doi.org/10.1109/upcon.2018.8596829.
Texto completoUpadhyay, Prashant, Rajib Kar, Durbadal Mandal y Sakti P. Ghoshal. "A novel 10T SRAM cell for low power circuits". En 2014 International Conference on Communications and Signal Processing (ICCSP). IEEE, 2014. http://dx.doi.org/10.1109/iccsp.2014.6949770.
Texto completoMansore, S. R. y Amit Naik. "A Highly Stable 10T SRAM Cell for Low Power Applications". En 2022 OPJU International Technology Conference on Emerging Technologies for Sustainable Development (OTCON). IEEE, 2023. http://dx.doi.org/10.1109/otcon56053.2023.10113962.
Texto completoSharma, Deepika y Shilpi Birla. "Design and Analysis of 10T SRAM Cell with Stability Characterizations". En 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT). IEEE, 2021. http://dx.doi.org/10.1109/icaect49130.2021.9392517.
Texto completoAhmad, Sayeed, Naushad Alam y Mohd Hasan. "Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications". En 2021 25th International Symposium on VLSI Design and Test (VDAT). IEEE, 2021. http://dx.doi.org/10.1109/vdat53777.2021.9601130.
Texto completoGrace, P. Shiny y N. M. Sivamangai. "Design of 10T SRAM cell for high SNM and low power". En 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2016. http://dx.doi.org/10.1109/icdcsyst.2016.7570609.
Texto completoKumar, Mukku Pavan, Rohit Lorenzo, Junjurampalli Khaja y Avtar Singh. "A Highly Stable PNN-PPN-10T SRAM Cell With Improved Reliability". En 2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP). IEEE, 2023. http://dx.doi.org/10.1109/aisp57993.2023.10135013.
Texto completoZhang, Jiubai, Xiaoqing Wu, Xilin Yi, Jiaxun Lv y Yajuan He. "A Subthreshold 10T SRAM Cell with Enhanced Read and Write Operations". En 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702371.
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