Relevant bibliographies by topics / Μm TSMC

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  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Μm TSMC'

Author: Grafiati
Published: 28 June 2021
Last updated: 9 February 2022

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Journal articles on the topic "Μm TSMC"

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CHENG, KUO-HSING, SHUN-WEN CHENG, and WEN-SHIUAN LEE. "64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS." Journal of Circuits, Systems and Computers 15, no. 01 (February 2006): 13–27. http://dx.doi.org/10.1142/s0218126606002915.

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This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.
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Shokrani, Mohammad Reza, Mojtaba Khoddam, Mohd Nizar B. Hamidon, Noor Ain Kamsani, Fakhrul Zaman Rokhani, and Suhaidi Bin Shafie. "An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/963709.

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This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.
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Pandey, Neeta, and Rajeshwari Pandey. "Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA." Active and Passive Electronic Components 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/967057.

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This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.
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Li, Zhi Yuan, and Xiang Ning Fan. "Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process." Applied Mechanics and Materials 364 (August 2013): 429–33. http://dx.doi.org/10.4028/www.scientific.net/amm.364.429.

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The design of a 0.7~3.8GHz CMOS power amplifier (PA) for multi-band applications in TSMC 0.18-μm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency (PAE) at gain compression point is 17.8% at 2GHz.
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Wang, Bin, and Qing Sheng Hu. "A High-Speed 64b/66b Decoder Used in SerDes." Applied Mechanics and Materials 556-562 (May 2014): 1549–52. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1549.

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A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-μm CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of technology such as pipeline strategy, optimization of complicated logics and parallel descrambler.
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Yu, Zhou, Xiang Ning Fan, Zai Jun Hua, and Chen Xu. "Design of a 0.7~2.6GHz Wideband Power Amplifier in 0.18-μm CMOS Process." Applied Mechanics and Materials 618 (August 2014): 543–47. http://dx.doi.org/10.4028/www.scientific.net/amm.618.543.

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A power amplifier (PA) for multi-mode multi-standard transceiver which is implemented in a TSMC 0.18μm process is presented. The proposed PA uses matching compensation, lossy matching network and negative feedback technique to improve bandwidth. To achieve the linearity performance, the two-stage PA operates in Class-A regime. Simulation results show that the power amplifier achieves maximum output power of more than 24dBm in 0.7~2.6GHz. The output P1dBof the PA is larger than 22dBm. The simulated power gain is more than 27dB. The S11 is less than-10dB and the S22 is under-5dB.
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Lee, Chae-Eun, Younginha Jung, and Yoon-Kyu Song. "8-Channel Biphasic Current Stimulator Optimized for Retinal Prostheses." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4298–302. http://dx.doi.org/10.1166/jnn.2021.19405.

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Retinal prostheses substitute the functionality of damaged photoreceptors by electrically stimulating retinal ganglion cells (RGCs). RGCs, densely packed in a small region, needs a high spatial resolution of the microelectrode, which in turn raises its impedance. Therefore, the high output impedance circuit and the high compliance output voltage are the key characteristics of the current-source-based stimulator. Also, as the system is intended to implant in the retina, the stimulation parameter should be optimized for efficiency and safety. Here we designed 8-channel neural stimulator customized to the retinal ganglion cell. Designed IC is fabricated in the TSMC 0.18 μm 1P6M RF CMOS process with 3.3 V supply voltage, occupying the 1060 μm×950 μm area.
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Mohan, Jitendra, and Sudhanshu Maheshwari. "Cascadable Current-Mode First-Order All-Pass Filter Based on Minimal Components." Scientific World Journal 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/859784.

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A novel current-mode first-order all-pass filter with low input and high output impedance feature is presented. The circuit realization employs a single dual-X-second-generation current conveyor, one grounded capacitor, and one grounded resistor, which is a minimum component realization. The theoretical results are verified using PSPICE simulation program with TSMC 0.35 μm CMOS process parameters.
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Bouzerara, Lyes, and Mohand Belaroussi. "Current mode approach: High performance 0.35 μm CMOS class AB push-pull current amplifier." Facta universitatis - series: Electronics and Energetics 16, no. 2 (2003): 195–204. http://dx.doi.org/10.2298/fuee0302195b.

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A very high bandwidth class AB (Push-Pull) current amplifier using the compensation resistor technique is presented and analyzed. Such technique stands as a powerful method of bandwidth enhancement for general circuits using CMOS current mirrors. The proposed bandwidth is enhanced from 675 MHz for the uncompensated current amplifier to 745MHz for the compensated one without affecting the current gain and other design parameters such as power consumption and output swing. The circuit exhibits a current gain of 20 dB and consumes 1.48 mW for ?2.5V power supply voltage. All simulation results were performed using Hspice tool with 0.35^m CMOS TSMC parameters.
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FAN, CHIH-PENG, and CHIA-HAO FANG. "LOW-POWER INSTRUCTION ADDRESS BUS CODING WITH XOR–BITS ARCHITECTURE." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 45–57. http://dx.doi.org/10.1142/s0218126609004910.

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In this paper, we present an address bus coding method to reduce dynamic power dissipations and delay faults at on-chip applications. The purpose of the proposed new coding technique is to diminish the switching and coupling activities on instruction address busses effectively. The proposed bus coding method is called the exclusive-OR and bus inverter transition signaling (XOR–BITS) code. The XOR–BITS code has four advantages. Firstly, it can save a large number of switching activities. Secondly, it can also save a large number of coupling activities. Thirdly, its architecture belongs to a low-complexity architecture. Finally, its delay is short after optimizations. Experimental results show that the XOR–BITS coding indicates an average reduction in 78.5% switching activities and 21.9% coupling activities on instruction address busses. It surpasses the other address coding methods in total power dissipations when the load capacitance is more than 1 pF/bit with the TSMC 0.13 μm CMOS technology. For a 50 pF/bit load capacitance, it achieves a 74.9% average reduction in total power dissipations, compared with the un-coded schemes by using seven benchmarks. Similarly, our method also surpasses the other address bus coding methods with the TSMC 0.18 μm CMOS technology.
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Dissertations / Theses on the topic "Μm TSMC"

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Chou, Tsung-Yi, and 周宗毅. "4-Gbps On-chip Interconnect Circuit in TSMC 0.18 μm Technology." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/76684066811559151718.

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碩士
國立臺灣大學
電子工程學研究所
95
This work is based on a novel structure of transmission line — slotted semi-coaxial line and adopts the proposed peripheral circuits to solve the problem of global interconnect. This work adopted TSMC 0.18μm technology and it is proved by the measurement results that the proposed structure can transmit up to 4 Gbps data at 1.8V peak-to-peak. The system which adopted the proposed transmission line is also faster than the conventional RC repeater.
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Lin, Guan-Wei, and 林冠瑋. "Design of Millimeter-wave Front-end Circuit With TSMC & UMC 0.18 μm CMOS-MEMS Process." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/8362xy.

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碩士
國立中正大學
電機工程研究所
103
This thesis presents the design of three millimeter-wave front-end circuits using TSMC 0.18 μm and UMC 0.18 μm CMOS-MEMS technologies, including a broadside coupler-based reflection-type phase shifter with continuous-phase-tuning mechanism, a DC-70 GHz CMOS-MEMS SPST switch with low operating voltage, and an active-circulator-based reflection-type phase shifter. The broadside coupler-based reflection-type phase shifter with continuous-phase-tuning mechanism is implemented in TSMC 0.18 μm CMOS-MEMS process. In this design, the number of switching states is increased, leading to larger achievable phase tuning range. With 47-volt actuation voltage, the simulation result shows that the ~134°phase tuning range can be achieved while the insertion loss is 4.3 0.5dB at 70-GHz. The second circuit is a DC-70 GHz CMOS-MEMS SPST switch, which is implemented in both UMC and TSMC 0.18 μm CMOS-MEMS process. The electrical-driven actuator was carefully designed to reduce the operating voltage down to 12 V. The measurement result shows that the insertion loss is less than 0.4 dB in ON-state, but the isolation is not good in OFF-state due to the unexpected silicon oxide accumulation. The last one is an active-circulator-based reflection-type phase shifter. The active quasi-circulator is constructed by CMOS transistors, while the MEMS-driven capacitance is adopted as reflective load. It is implemented in TSMC 0.18 μm CMOS-MEMS process. The Simulation result shows that the phase tuning range is 102° under a 35-volt supply voltage at 24-GHz.
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Conference papers on the topic "Μm TSMC"

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Prajapati, Jignesh R., and Zuber M. Patel. "High linearity low noise figure mixer for Wi-max in 0.18 μm tsmc technology." In 2016 International Conference on Signal and Information Processing (IConSIP). IEEE, 2016. http://dx.doi.org/10.1109/iconsip.2016.7857456.

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Chen, Wen-Yu, Yi-Feng Zhang, Paul C. P. Chao, and Eka Fitrah Pribadi. "Design and Implementation of a High Accuracy Interpolation Encoder IC for Magnetic Sensor." In ASME 2019 28th Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/isps2019-7476.

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Abstract The magnetic encoder (ME) always employs sensor passing through periodic and equal distance grating and then generates periodic quadrature scaling signals for displacement measurement. The phase is relative to the movement. To improve encoder accuracy or resolution, electronic interpolation technique had been developed to subdivide the phase of quadrature scaling signals. According to the trends, this paper proposed a specific method with excellent noise immunity characteristic and a complete calibration process to improve the accuracy of the system. The designed circuit is taped-out using TSMC 0.18-μm CMOS process, where the active area is 1643 μm × 1676 μm. The chip has the specification of 3.3 V supply voltage, 20 MHz clock frequency, and 0.0859 mW power consumption. The accuracy of the measurement system is 1.065um.
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Pribadi, Eka Fitrah, Rajeev Kumar Pandey, and Paul C. P. Chao. "A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal." In ASME 2021 30th Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2021. http://dx.doi.org/10.1115/isps2021-65248.

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Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.
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Chao, Paul C. P., Chin-I. Su, Trong-Hieu Tran, and Hsiao-Wen Zan. "A 3.2 mW Mixed-Signal Readout Circuit for an Organic Vertical Nano-Junctions Sensor." In ASME 2016 Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/isps2016-9599.

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A new sensitivity organic vertical nano-junctions (VNJ) sensor for ammonia detection and its readout system are presented in this study. The designed ammonia sensor, VNJP3HT diode, is a simple structure with real-time response, high reproducibility and low-cost sensor. Along with the designed sensor, a precision and robust readout circuit is designed and successfully implemented as the proposed chip in this study. To utilize for a novel organic bio-chip, a particular readout system is presented that can acquire signal, compute and display concentration values of ammonia without using microcontroller. The chip is fabricated by the TSMC 0.18-μm 1P6M 3.3V mixed-signal CMOS process technique for verification. Experiment results show that the average resolution is 70.48mV/log (ppm) in a short transient time response, 50 seconds, as compared to prior study, 200 seconds. Error rate, average noise and detection rate reliability are 2.86%, 123 μVrms, and 99.6%, respectively. This chip could be suitable for application in cars, cell phones, watches, etc.
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Wang, Mu-Chun, Zhen-Ying Hsieh, Chieu-Ying Hsu, Shuang-Yuan Chen, and Heng-Sheng Huang. "A 2.4-GHz 0.18μm Full-CMOS Single-Stage Class-E Power Amplifier With Temperature Effect for ISM Band Wireless Communication." In 2007 First International Conference on Integration and Commercialization of Micro and Nanosystems. ASMEDC, 2007. http://dx.doi.org/10.1115/mnc2007-21085.

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In this paper, we present a single-stage class-E power amplifier with multiple-gated shape as well as 0.18μm complementary metal-oxide-semiconductor (CMOS) process for 2.4GHz Industry-Science-Medicine (ISM) band. This power amplifier is able to be easily integrated into the system-on-chip (SoC) circuit. For the competition of lower cost and high integration in marketing concern, CMOS technology is fundamentally better than GaAs technology. We adopt the Advanced Design System software in circuit simulation coming from Agilent Company through the Chip Implementation Center (CIC) channel plus TSMC 0.18 μm device models. The simulation results with temperature effect, show the good performance such as an output power achievement of +22dBm under a 1.8V supply voltage; the power-added efficiency (PAE) is over 30%; the output impedance (S22) and the input impedance (S11) are fully lower than −15dB; the power gain (S21) is +11dB; the inverse isolation (S12) is below −26dB. This amplifier reaches its 1-dB compression point at an output level of 16.5dBm related to the input power 6.5dBm position. The output power with temperature variation from 0°C to 125°C depicts an acceptable spec. range, too.
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Chao, Paul C. P., Li-Chi Hsu, and Trong-Hieu Tran. "A New Small-Sized Non-Dispersive Infrared (NDIR) Sensor and its Drive/Readout Circuits." In ASME 2016 Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/isps2016-9562.

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A new miniaturized, non-dispersive, infrared (NDIR) sensor for CO2 intended to be installed in mobile phones and its drive/readout circuits are presented in this study. A typical NDIR sensor consists of three main components; an infrared (IR) light-emitter (light source), a gas chamber, a photo detector (PD) light receiver) and the associated drive/readout circuits. The geometry of the gas chamber is optimized to minimize the total module size to approximately 10 mm × 5 mm × 5 mm, which is much smaller than commercially-available gas sensors. Driver and readout circuits are successfully designed and taped out. The driver circuit intends to generate pulse width modulation (PWM) signal to control proper dimming of LED. The readout circuit, which acquires small signal from photo detector then converts to digital values, includes amplifier, low pass filter and analog-to-digital converter (ADC). The proposed circuit is fabricated by the TSMC 0.35-μm CMOS process, where the area is 4.527 mm2 while power consumption is 60.16 mW for the whole chip. The resolution is less than 12 ppm along with time constant is 0.1 sec.
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Chen, Hung-Che, Yung-Hua Kao, Paul C. P. Chao, and Chin-Long Wey. "A New Automatic Readout Circuit for a Gas Sensor With Organic Vertical Nano-Junctions." In ASME 2016 Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/isps2016-9582.

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The design of the proposed readout circuit provides benefits of detection speed, portability, low-cost and less human operational errors compared with the measurement by traditional instruments. Thus the added value is brought for biosensors and applied in home care. A novel readout circuit for a gas sensor based on an organic diode with vertical nano-junctions (VNJ) is proposed in this study. There are seven parts included in the readout system. First part is a preamplifier, second part is a peak-detect-and-hold circuit, third part is a divider, fourth part is the saturation detector, fifth part is the auto-reset circuit, sixth part is a logic gate and a buffer, seventh part is a micro-processor control unit (MCU). STM32 is the CPU of proposed MCU by ALIENTEK. The ADC of MCU is used to transform the output data of readout circuit. The designed circuit is accomplished by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 μm 2P4M 3.3 V mixed signal CMOS process, the area of chip is 0.74×0.75 mm2. Finally, the differences between experimental results with post-simulation results in 10 ppb ∼ 3 ppm of ammonia, the differences are within 7.24%. The sensing system is able to detect minimum ammonia concentration of 10 ppb, while the maximum one reaches around 3 ppm.
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Chang, C. P., W. W. Yen, and Paul C. P. Chao. "A New Wireless Power Transfer Circuit With a Single-Stage Regulating Rectifier for Flexible Sensor Patches." In ASME 2020 29th Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/isps2020-1951.

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Abstract A new wireless power transfer circuit with a single-stage regulating rectifier is designed and validated with satisfactory efficiency for flexible sensor patches. Since the battery is bulky and cannot be fabricated on a flexible substrate, the power source of the electronic patch is realized by wireless power transfer. Magnetic resonance transmission power at 13.56 MHz in the ISM band is adopted to make possible wireless power transfer. Furthermore, for high conversion efficiency, a new single-stage regulating rectifier is designed and implemented at the receiver side of the sensor patch. An active switching full-wave bridge rectifier is designed to reduce conduction loss and increase the voltage-conversion rate. A delay lock loop feedback controller overcomes the switching delays at high frequencies that significantly undermine power conversion efficiency. The voltage rectification and regulation are achieved simultaneously in a single-stage rectifier through 1X/0X mode control. The PFM control is adopted to select the switching frequency of the system in order to maximize the transient response during heavy load and to minimize the switching power losses during light load. The circuit is fabricated via the TSMC 0.35 μm process. The output efficiency of the circuitry was improved by 5–10% in light load as compared with the circuit without PFM control, while the peak efficiency reaches favorable 86%.
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