Relevant bibliographies by topics / Xilinx ISE

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Xilinx ISE'

Author: Grafiati
Published: 28 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Xilinx ISE"

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Palanisamy, R., C. S. Boopathi, K. Selvakumar, and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1722. http://dx.doi.org/10.11591/ijece.v10i2.pp1722-1727.

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This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.
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Palanisamy, R., and K. Vijayakumar. "Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (July 1, 2019): 81. http://dx.doi.org/10.11591/ijres.v8.i2.pp81-85.

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<p>This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.</p>
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G, Rekha, Arunkumar P. Chavan, and Ravish Aradhya H. V. "Bio-Inspired Motion Detector Model Simulated on Xilinx ISE." International Journal of Computer Applications 72, no. 13 (June 26, 2013): 23–32. http://dx.doi.org/10.5120/12554-9129.

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SALEH, ANDHI RACHMAN, and SUNNY ARIEF SUDIRO. "CRC 8-bit Encoder-Decoder Component in FPGA using VHDL." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, no. 1 (January 31, 2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

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AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i
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., Swati Sharma. "DESIGNING OF CORDIC PROCESSOR IN VERILOG USING XILINX ISE SIMULATOR." International Journal of Research in Engineering and Technology 03, no. 05 (May 25, 2014): 342–49. http://dx.doi.org/10.15623/ijret.2014.0305064.

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Chetia, Rajib. "Behavioral Design and Synthesis of 64 BIT ALU using Xilinx ISE." IOSR Journal of Electronics and Communication Engineering 7, no. 4 (2013): 37–41. http://dx.doi.org/10.9790/2834-0743741.

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Abdulraheem Fadhel, Mohammed, Omran Al-Shamaa, and Bahaa Husain Taher. "Real-Time detection and tracking moving vehicles for video surveillance systems using FPGA." International Journal of Engineering & Technology 7, no. 2.31 (May 29, 2018): 117. http://dx.doi.org/10.14419/ijet.v7i2.31.13422.

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With the growth of the electronic and communication devices, computer vision has become an significant application of smart cities. A smart city is controlled by smart autonomous systems. Many algorithms have been developed to satisfy these smart cities. This paper concerned with addressing the moving objects (vehicles) by using morphological techniques. For computational cheapness. The simulation has been built by a MATLAB 2012a and its implementation was done using Xilinx-ISE 14.6 (2013) XC3S700A-FPGA board that provides an exceptional tool for mixing between two platforms, the ISE 14.6(2013) and the MATLAB (2012a) platforms. MATLAB provides components for FPGA that invoke Verilog code of Xilinx platform, to avoid the size weakness of XC3S700A-FPGA board.
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Muslim, Imaduddin Amrullah, R. Rizal Isnanto, and Eko Didik Widianto. "Perancangan dan Implementasi Algoritma DES untuk Mikroprosesor Enkripsi dan Dekripsi pada FPGA." Jurnal Teknologi dan Sistem Komputer 3, no. 2 (April 20, 2015): 259. http://dx.doi.org/10.14710/jtsiskom.3.2.2015.259-266.

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Seiring dengan semakin luasnya penerapan teknologi komputasi di sekitar kita, menjadikan informasi menjadi sangat mudah dan cepat untuk disebarkan. Kita dapat mengakses informasi dan data-data yang kita butuhkan dengan mudah. Namun permasalahan yang kita hadapi saat ini kerhasiaan informasi menjadi sangat riskan. Oleh karena itu Sistem keamanan merupakan hal penting yang perlu diperhatikan dalam mengembangkan suatu sistem komputer hal ini lah yang menjadikan enkripsi dan dekripsi data menjadi hal yang penting. Modul rancangan IP Core ini dirancang menggunakan aplikasi Xilinx ISE Design Suite 12.4. Kemudian rancangan IP Core ini diimplementasikan pada papan Xilinx FPGA Spartan-3E XC3S500E-4FG320C dari keluarga Xilinx FPGA Spartan-3E dengan 500K sistem gerbang. Verifikasi fungsional dari IP Core yang dirancang menggunakan testbench dan simulasi diagram pewaktuan menggunakan aplikasi Xilinx ISE Simulator. Tugas akhir ini ditujukan untuk mengembangkan IP Core yang mampu menjalankan fungsi enkripsi DES (Data Encryption Standard) dan ditulis menggunakan bahasa Verilog. Implementasi algoritma enkripsi dan dekripsi algoritma DES telah berhasil dilakukan. Hasil analisis menunjukkan sistem telah dapat melakukan enkripsi dan dekripsi data sesuai dengan spesifikasi algoritma DES. Sebaiknya penelitian ini dikembangkan kembali dengan menguji sistem untuk melakukan transmisi data berupa file ataupun teks. Selain itu juga perlu meningkatkan unjuk kerja sistem dengan optimasi sumber daya dan kecepatan waktu proses pada perancangan rekonstruksi kode verilog.
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Kamar, Sara, Abdelmoniem Fouda, Abdelhalim Zekry, and Abdelmoniem Elmahdy. "FPGA implementation of RS codec with interleaver in DVB-T using VHDL." International Journal of Engineering & Technology 6, no. 4 (November 28, 2017): 171. http://dx.doi.org/10.14419/ijet.v6i4.8205.

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Digital television (DTV) provides a huge amount of information to many users at low cost. Recently, it can be packaged and fully integrated into completely digital transmission networks. Reed-Solomon code (RS) is one type of error correcting codes that can be used to enhance the performance of DTV. Interleaving/deinterleaving process enhances the performance of channel errors by spreading out random errors, very high-speed hardware description language (VHDL) is used in electronic design automation. It can be used as a general-purpose parallel programming language.This paper presents VHDL program for Reed-Solomoncodec (204, 188) and convolutional interleaver/deinterleaver, used in Digital Video Broadcasting-terrestrial system (DVB-T), according to ETSI EN 300 744 V1.5.1 standard. The VHDL programs are implemented on Xilinx 12.3 ISE and then simulated and tested via ISE simulator then the code is synthesized on FPGA device the results are compared with IP core for Xilinx 12.3 ISE, which gives the same results.
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rani, Archana, and Naresh Grover. "Area & Power Optimization of Asynchronous Processor Using Xilinx ISE & Vivado." International Journal of Information Engineering and Electronic Business 10, no. 4 (July 8, 2018): 8–15. http://dx.doi.org/10.5815/ijieeb.2018.04.02.

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Dissertations / Theses on the topic "Xilinx ISE"

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Houška, David. "Poloautomatizovaný návrh vysoce výkonných číslicových obvodů s Xilinx FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2021. http://www.nusl.cz/ntk/nusl-442592.

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Tato diplomová práce se zabývá návrhem sekvenčních digitálních obvodů s ohledem na optimalizaci zpoždění. V práci je popsána problematika dvou technik, které jsou běžně používané při optimalizaci – stručně je popsána technika tzv. synchronizace registrů (angl. retiming), větší pozornost je však věnována technice tzv. zřetězení (angl. pipelining). V rámci praktické části byla vypracována forma abstrakce sekvenčních digitálních obvodů pomocí acyklických orientovaných grafů. Obvod je tak přenesen do roviny, ve které je jednodušší jej transformovat. Zároveň je představen nástroj pro polo-automatickou optimalizaci digitálních obvodů vyvíjených v prostředí Xilinx ISE Design Suite využitím techniky zřetězení.
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Kerber, Rostislav. "IP generátor mikroprocesorového systému." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219170.

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This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.
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Kao, chingshan, and 高晴山. "Simulation of DS/SS-BPSK Communications System on Xilinx ISE." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/75746854934049770800.

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碩士
中華科技大學
電子工程研究所碩士班
99
This paper, mainly conducts simulation analysis to the communication modulation system of binary phase-shift keying (BPSK) combined with direct-sequence spread-spectrum(DS/SS-BPSK) under the single frequency interference of Simulink and Xilinx, and makes detailed simulation discussion of DS/SS-BPSK communication system by Xilinx ISim simulation software. The study first conducts performance analysis of DS/SS-BPSK communication system under the interference signal and additive white Gaussian noise (AWGN) effect, and takes Field Programmable Gate Array (FPGA) as the design platform developed by Xilinx Company, then uses Xilinx ISE to complete the digital circuit design of DS/SS-BPSK communication system. The simulation software of Xilinx ISim is used to conduct the designed circuit modules functions and time sequence simulation analysis. The simulation results prove DS/SS-BPSK is correct and accurate under the design of this study.
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Zhou, Jie, and 周傑. "Simulation of DS/SS-QPSK Communication Systems Based on Xilinx ISE." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/31123187449526503909.

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碩士
中華科技大學
電子工程研究所碩士班
99
This article designs and simulates the Direct-Sequence Spread-Spectrum Quadrature Phase-Shift Keying (DS/SS-QPSK) communication system under the FPGA environment. It first discusses about the principle and structure of the transmitter and receiver of DS/SS-QPSK communication system, and designs DS/SS-QPSK system by taking Xilinx’s Integrated Synthesis Environment (ISE) software as the development tool. In the transmitter, the input data sequences are operated with DS/SS generator signals computation by in-phase, quadrature channels. The synthesized signal by these two channels will generate 4-phase sine wave transmitting signal through Direct Digital Synthesizer (DDS). The receiver completes the demodulation process by non-coherent method, and takes Box-Muller algorithm as the technical basis to design the Xilinx FPGA Additive White Gaussian Noise (AWGN) generator. This study also conducts function simulation and comparative verification on DS/SS-QPSK system by ISim simulator, in which the simulation results can completely recover the originally estimated binary data. Finally, it discusses about the influence of AWGN to the DS/SS-QPSK system on the receiving performance. After the simulation verification of ISim simulator, it can also recover the signal correctly and accurately. Therefore, it proves the noise-resistance of DS/SS-QPSK and the feasibility of FPGA design.
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Wen, Zhi-Huang, and 溫志煌. "Simulation of QAM Communication Systems in White Noise based on Xilinx ISE." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/02800430361649619729.

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碩士
中華科技大學
電子工程研究所碩士班
99
This paper discusses about the principle and structure of M-ary Quadrature Amplitude Modulation (MQAM), and then uses the results and functional block diagram deducted by MQAM equation to design and simulate the functional module by Xilinx FPGA. This study adopts the communication system of M being 4 as the example of design and simulation. The receiving end takes Box-Muller algorithm as the technical basis to design the Xilinx FPGA Additive White Gaussian Noise (AWGN) generator. The receiver in this article adopts the way of noncoherent demodulation, while 4QAM communication system and AWGN both take the Xilinx ISE software as the design and simulation platform. And ISim simulator is used to complete the simulation of system functional modules, signal comparison and verification. The signal simulation results of 4QAM communication system in this paper prove the signal data of binary sequence could be recovered successfully and accurately. The time delay caused by the computation of the functional circuit modules can result in slight difference of signal time sequence. Moreover, after AWGN is added in the communication system, the ISim simulation verification results find out the binary estimation signal sequence could be recovered. All these prove this QAM communication system is noise- resistant.
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Books on the topic "Xilinx ISE"

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Zotov, Valerij Ûr'evič. Proektirovanie cifrovyh ustrojstv na osnove plis firmy XILINX v SAPR WebPACK ISE. Moskva: Gorâčaâ liniâ - Telekom, 2003.

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Dailey, Denton J. Programmable Logic Fundamentals Using Xilinx ISE. Prentice Hall, 2004.

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Dailey, Denton J. Programmable Logic Fundamentals Using Xilinx ISE. Prentice Hall, 2004.

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Book chapters on the topic "Xilinx ISE"

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Deshwal, Abhishek, Aman Singh, Ashutosh Gupta, P. C. Joshi, and Chiranjeev Singhal. "Power Analyses in AMBA AHB Protocol and Synthesis Over Xilinx ISE." In Advances in Smart Communication and Imaging Systems, 693–701. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-9938-5_64.

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Sk, Kamarujjaman, Manali Mukherjee, and Mausumi Maitra. "FPGA-Based Re-Configurable Architecture for Window-Based Image Processing." In Computer Vision, 273–310. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-5204-8.ch011.

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In this proposed book chapter, a simple but efficient presentation of Median Filter, Switching Median Filter, Adaptive Median Filter and Decision-Based Adaptive Filtering Method and their hardware architecture for FPGA is described for removal of up to 99% impulse noise from Digital Images. For hardware architecture, simulation is done using Xilinx ISE 14.5 software of XILINX. For implementation, these approaches utilize Genesys VIRTEX V FPGA device of XC5VLX50T device family. In this approach, we proposed an efficient design for suppression of impulse noise from digital images corrupted by up to 99% impulse noise using decision based adaptive filtering method as well as preserve the details of image. The method works in two different stages – noise detection using switching technique and finally noise suppression and restoration. Experimental results show that our method perform better in terms of PSNR below 80% noise density but above 80% noise density it is almost comparable with the latest methods.
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Sk, Kamarujjaman, Manali Mukherjee, and Mausumi Maitra. "FPGA-Based Re-Configurable Architecture for Window-Based Image Processing." In Advances in Computational Intelligence and Robotics, 1–46. IGI Global, 2017. http://dx.doi.org/10.4018/978-1-5225-0889-2.ch001.

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In this proposed book chapter, a simple but efficient presentation of Median Filter, Switching Median Filter, Adaptive Median Filter and Decision-Based Adaptive Filtering Method and their hardware architecture for FPGA is described for removal of up to 99% impulse noise from Digital Images. For hardware architecture, simulation is done using Xilinx ISE 14.5 software of XILINX. For implementation, these approaches utilize Genesys VIRTEX V FPGA device of XC5VLX50T device family. In this approach, we proposed an efficient design for suppression of impulse noise from digital images corrupted by up to 99% impulse noise using decision based adaptive filtering method as well as preserve the details of image. The method works in two different stages – noise detection using switching technique and finally noise suppression and restoration. Experimental results show that our method perform better in terms of PSNR below 80% noise density but above 80% noise density it is almost comparable with the latest methods.
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Gharaee, Hossein, Abdolreza Nabavi, and Jalil ("Joe") Etminan. "Performance and Complexity Evaluation of OTR-UWB Receiver." In Networking and Telecommunications, 1945–58. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-986-1.ch123.

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This article presents a new transmitted reference UWB receiver, which utilizes the orthogonal property of even and odd order derivatives of Gaussian pulses in neighboring chips for synchronization. This system, referred to as orthogonal TR-UWB (OTR-UWB), employs only a single spreading code, which results in much lower mean detection time compared to DS-UWB systems. The hardware complexity for OTR-UWB receiver is significantly reduced against conventional TR-UWB systems. In addition, simulation results show that BER performance is improved, while the new system is capable of supporting higher data rates. Also, this article presents the FPGA implementation of OTR-UWB, with a bit-rate of 25Mb/s without using equalizer. In addition, we present the DSP algorithm of baseband. Hardware of this system is implemented on two different FPGAs from ALTERA and XILINX, CycloneII (EP2C35F672C6) and Spartan 3 (3s4000fg676-5). Gate estimation and power analysis are performed by Quartus II 7.2 (ALTERA) and ISE 8.1 (XILINX) softwares.
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Conference papers on the topic "Xilinx ISE"

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Fadzilah Mokhtar, Nor, Afaf Rozan Mohd Radzol, and Suzana Ab Rahim. "Xilinx ISE software teaching aid for Diploma's students." In 2009 International Conference on Engineering Education (ICEED). IEEE, 2009. http://dx.doi.org/10.1109/iceed.2009.5490614.

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Kumar, Palle Prasanth, K. V. Gowreesrinivas, and P. Samundiswary. "Design and analysis of turbo encoder using Xilinx ISE." In 2016 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT). IEEE, 2016. http://dx.doi.org/10.1109/iccicct.2016.7987968.

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Kaur, Harkinder, Divanshi Aggarwal, Swaranjeet Singh, Priyanka Tandon, Chandni Thakur, and Harsh Sohal. "Design and performance analysis of RAM_RD_CONTROL module using Xilinx ISE 14.2." In 2016 5th International Conference on Wireless Networks and Embedded Systems (WECON). IEEE, 2016. http://dx.doi.org/10.1109/wecon.2016.7993476.

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Doshi, Jinalkumar, Pratiksha Patil, Zalak Dave, Ganesh Gore, Jonathan Joshi, Reena Sonkusare, and Surendra Rathod. "Implementing a cloud based Xilinx ISE FPGA design platform for integrated remote labs." In 2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2015. http://dx.doi.org/10.1109/icacci.2015.7275663.

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Malinin, Grigoriy, and S. Yankevich. "LOGIC AUTOMATIC DRIVER CONTROL IN THE SYSTEM OF CONTROL OF POWERFUL POWER CONVERTERS." In CAD/EDA/SIMULATION IN MODERN ELECTRONICS 2019. Bryansk State Technical University, 2019. http://dx.doi.org/10.30987/conferencearticle_5e02821252ea43.36490574.

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The paper presents an analysis of possible emergency conditions in a voltage converter controlled from an FPGA or a microcontroller and a method for eliminating them using a logical machine. The principle of operation of the machine is explained using a model assembled in CAD Xilinx ISE Design Suite.
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Jaafar, A., N. Soin, and S. Wan Muhammad Hatta. "An educational FPGA design process flow using Xilinx ISE 13.3 project navigator for students." In 2017 IEEE 13th International Colloquium on Signal Processing & its Applications (CSPA). IEEE, 2017. http://dx.doi.org/10.1109/cspa.2017.8064915.

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Krishna, V. V. S. Vijay, A. Monisha, Sk Sadulla, and J. Prathiba. "Design and implementation of an automatic beverages vending machine and its performance evaluation using Xilinx ISE and Cadence." In 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT). IEEE, 2013. http://dx.doi.org/10.1109/icccnt.2013.6726639.

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Lei, Shuliang, Andy Provenza, Alan Palazzolo, and Raymond Beach. "Implementation of Magnetic Suspension Control With FPGA." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-44057.

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This paper presents a methodology for an alternative implementation of DSP-based controllers typically used for magnetic bearing (MB) levitation and control on FPGA hardware. The approach takes s-domain transfer functions of the controller components and discretizes them using z-transform conversions into discrete time domain expressions. These expressions, which are essentially digital IIR filters, are synthesized and implemented to obtain downloadable bit-stream using Xilinx ISE software packages. In the example presented, the executable code was sent to configure the two FPGAs for control. An equivalent PD with notch filter FPGA-based controller was constructed to replicate an existing two-axis DSP controller used to control a radial magnetic bearing on a vertical rotor in the Dynamic Spin Rig Facility at NASA Glenn Research Center. The FPGA controller was successfully demonstrated on the NASA hardware.
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Arshak, Khalil, Essa Jafer, and Christian Ibala. "Testing FPGA based digital system using XILINX ChipScope logic analyzer." In 2006 29th International Spring Seminar on Electronics Technology. IEEE, 2006. http://dx.doi.org/10.1109/isse.2006.365129.

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Carline, D., and P. Coulton. "Partial reconfiguration in Xilinx Virtex FPGAs: pitfalls and solutions for SoC implementations." In IEE Colloquium on DSP enabled Radio. IET, 2003. http://dx.doi.org/10.1049/ic.2003.0296.

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