Academic literature on the topic 'Wide-band Input Matching'

In this paper, a wide-band noise-canceling (NC) current conveyor (CC)-based CMOS low-noise amplifier (LNA) is presented. The circuit employs a CC-based approach to obtain wide-band input matching without the need for bulky inductances, allowing broadband performance with a very small area used. The NC technique is applied by subtracting the input transistor’s noise contribution to the output and achieves a noise figure (NF) reduction from 4.8 dB to 3.2 dB. The NC LNA is implemented in a UMC 65-nm CMOS process and occupies an area of only 160 × 80 μm2. It achieves a stable frequency response from 0 to 6.2 GHz, a maximum gain of 15.3 dB, an input return loss (S11) < −10 dB, and a remarkable IIP3 of 7.6 dBm, while consuming 18.6 mW from a ±1.2 V DC supply. Comparisons with similar works prove the effectiveness of this new implementation, showing that the circuit obtains a noteworthy performance trade-off.

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

In this paper, an ultra-wide band (UWB) low noise amplifier (LNA) is implemented by using 90nm RF CMOS technology. The designed LNA achieves high flat band gain (S21) and low noise figure (NF) in the frequency of interest. The proposed LNA operates in the frequency range of 3GHz to 8GHz. In this work, wide band matching is achieved by designing common gate configuration at the input stage. The current reuse and noise cancellation techniques are introduced to improve flat band gain and minimize both noise figure and power consumption. The noise figure is improved by cancelling dominant noise sources with additional hardware. The proposed LNA attains flat band gain of 26.5dB and input matching less than -12dB for entire UWB band. This work achieves noise figure of 2.1dB to 2.59dB in frequency band of interest. Additionally, power consumption of the circuit is 20mW at 1.8V supply voltage.

In this paper, an ultra-wide band 0.18 μm CMOS common-gate low-noise amplifier (LNA) is presented. Designed in the ultra-wide band frequency range of 3.1–10.6 GHz, it uses a current-reused technique with modified input matching. This approach allowed obtaining a flat broadband gain of 12.75 ± 0.83 dB with an input reflection coefficient less than -5.5 dB, an output reflection coefficient less than -7 dB, and a noise figure less than 3.7 dB. Furthermore, the proposed low-power LNA consumes only 12.14 mW (excluding buffer) from a 1.2 V supply voltage.

In this paper, a dual-band wide-input-range adaptive radio frequency-to-direct current (RF–DC) converter operating in the 0.9 GHz and 2.4 GHz bands is proposed for ambient RF energy harvesting. The proposed dual-band RF–DC converter adopts a dual-band impedance-matching network to harvest RF energy from multiple frequency bands. To solve the problem consisting in the great degradation of the power conversion efficiency (PCE) of a multi-band rectifier according to the RF input power range because the available RF input power range is different according to the frequency band, the proposed dual-band RF rectifier adopts an adaptive configuration that changes the operation mode so that the number of stages is optimized. Since the optimum peak PCE can be obtained according to the RF input power, the PCE can be increased over a wide RF input power range of multiple bands. When dual-band RF input powers of 0.9 GHz and 2.4 GHz were applied, a peak PCE of 67.1% at an input power of −12 dBm and a peak PCE of 62.9% at an input power of −19 dBm were achieved. The input sensitivity to obtain an output voltage of 1 V was −17 dBm, and the RF input power range with a PCE greater than 20% was 21 dB. The proposed design achieved the highest peak PCE and the widest RF input power range compared with previously reported CMOS multi-band rectifiers.

In this work, the influence of the inductor quality factor in wide band low noise amplifiers has been studied. Electromagnetic simulations have been used to model the integrated inductor broad band response. The influence of the quality factor on LNA performance of the inductors that compound the impedance matching networks, inductive degeneration and broadband load has been studied, obtaining design guidelines for optimizing the amplifier gain flatness. Using this guidelines, an LNA with wideband input matching, shunt-peaking load, and an output buffer was designed. Using Austria Mikro Systems BiCMOS 0.35 m process, a prototype has been fabricated achieving the following measured specifications: maximum gain of 12.5 dB at 3.4 GHz with a -3 dB bandwidth of 1.7–5.3 GHz, noise figure from 4.3 to 5.2 dB, and unity gain at 9.4 GHz.

Abstract Considering the narrow bandwidth of microstrip antennas, but also their applicability in upcoming technologies, this paper addresses the problem of wide-band matching, the theoretical bounds on the matching bandwidth and low-cost and low-complexity matching strategies. In this context the Bode-Fano bounds of single mode, linearly polarized aperture-coupled microstrip antennas is evaluated, optimized and compared to the theoretical bounds on matching bandwidth of other common feeding technologies. A detailed study of the input impedance of aperture-coupled patch antennas shows how to widen the Fano bounds. Based on this, a straight-forward and effective method to optimize the Fano bound is given. After optimization of the antennas input impedance, basic matching techniques can be applied, to exploit the enlarged bandwidth potential. As an example a $\lambda/4$-transformer as matching element is proposed. Design equations and simulation and measurement results of X-band prototypes are given as verification.

A traveling wave matching (TWM) network is proposed for broadband variable gain amplifier design. The TWM network lessens input return loss and noise figure dependence on VGA’s gain, which is adjusted by biasing of the gain control circuit. A wide band (DC to 12 GHz) VGA with the novel TWM network as input matching is implemented in 2μm InGaP/GaAs HBT (fT of 29.5GHz) technology with die size of 1×2 mm2. As gain control voltage sweeps, the VGA shows a gain tuned from -15 dB to 15 dB and an average noise figure ranging from 8dB to 6.5dB, while S11 (lower than -20dB) and S22 (lower than -10dB) almost unchanged over the operation frequency band.

碩士
國立交通大學
電信工程研究所
102
In this thesis, a novel wide band low noise amplifier combined negative resistance with common gate structure for LTE applications are presented. The research focused on how to reduce the power consumption and noise figure, and using negative resistance to achieve the effect of input impedance matching. In the past, the design of low-noise amplifier used RLC feedback or lengthy inductance, capacitance in series and parallel to achieve broadband matching circuit at the input, however our circuit used fewer of components to increase the bandwidth. In our design, a common gate amplifier with negative resistance using the frequency independent of the transistor current is to replace the traditional architecture of passive inductor at input, and with the gm-boost technique to achieve low power and noise reduction effectively. The shunt peaking network at drain is drawn to further suppress the high-frequency noise and a low noise level is achieved. The proposed LNA is implemented by the TSMC 0.18-μm CMOS technology process, and measured by use of CIC instruments. The measured results are as follows: bandwidth of 0.5 ~ 3.7 GHz, input and output reflection loss are greater than -12 dB, the maximum power gain is 17.8 dB, the minimum noise figure is 3.3 dB, at 2.7 GHz, the P1dB gain compression point is -20 dBm, the IIP3 cut-off point is -10.3 dBm, the core circuit power consumption is 6.48 mW, and the overall layout area including the pads is 0.716 * 0.744 = 0.533 mm2.

The ever growing demand for higher data rates and the heavy usage of wireless communication devices have created frequency congestion on certain bands of the radio spectrum. The push has been towards new standards that can quench this thirst for data capacity and more space on the spectrum. This has led to added complexity and cost for radio platforms. In particular, the increase in the number of antennas, switch banks and pre-select filters have made it challenging to implement these platforms cost-effectively. Therefore, concepts such as software-defined radio(SDR) and cognitive radio(CR) have been proposed to tackle this problem. These concepts, allow the use of a single wideband receiver which can handle multiple radio standards spread across the entire spectrum of interest. The introduction of a common flexible hardware platform eliminates the use of multiple off-chip RF pre-filters and thus lowers cost, reduces complexity and form factor. While attractive, these future radio receivers pose a number of unique challenges to the designer. This thesis focuses on frequency translation (FT) techniques and addresses two key SDR/CR challenges: the robustness to out-of-band interference (OBI) or block-ers and the compatibility with CMOS scaling and system-on-chip (SoC) integration. The thesis studies the principles and the performance limitations of existing FT tech-niques and proposes new circuit-and-system techniques to improve the performance of wideband receivers suitable for SDR and CR applications. First, the performance of the frequency translational resistive feedback receiver frontend is studied and analyzed. Instead of using a conventional LNA, the job of the LNA is shared along the receiver chain through the utilization of frequency translation techniques. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. Though frequency translation is at the core of the receiver functionality, it is accomplished using time-varying, strongly nonlinear passive mixer circuits. So the operation and noise performance cannot be understood using standard LTI circuit analysis techniques. To this end, an in-depth LTV analysis is presented which accurately captures the gain, input matching and the noise performance of the receiver. Next, a wideband blocker tolerant receiver with an RF frequency range of 0.1 GHz to 2.2 GHz is proposed. By using frequency-translational resistive shunt-feedback, the receiver achieves frequency selective input match across its entire range of operation. Four techniques for improving blocker tolerance of the receiver have been utilized: 1) voltage amplification only after baseband filtering 2) blocker rejection at the antenna interface using an N-path filter 3) blocker current cancellation in the baseband 4) frequency translational noise cancellation which uses an auxiliary path to cancel the noise of the main path. By introducing an auxiliary path, the value of the RF transconductor in the main path is halved which in turn relaxes the requirements of the main path and further improves the overall linearity of the receiver while degradation in the noise figure is prevented due to noise-cancellation. As a proof of concept, a receiver prototype is fabricated in a 130 nm CMOS process. The measurement results demonstrate that the receiver achieves +2dBm in-band IIP3 and +27dBm out-of-band IIP3. The measured noise figure varies from 2.6 dB at low frequencies to 3.2 dB at 2.2 GHz. The receiver can tolerate a +2.5 dBm blocker beyond a 40 MHz offset while achieving a blocker noise figure of 4.6 dB for a 0-dBm blocker at 40 MHz offset. Finally, architecture and circuit techniques are proposed to improve the receiver’s resilience to strong harmonic blockers. Designed in a 40nm standard CMOS process, the receiver can tolerate up to -1 dBm harmonic blockers. On the other hand, it achieves a 1-dB standard blocker compression point of +3 dBm and OB-IIP3 of +24 dBm at a 40 MHz offset from the LO frequency.
Department of Electronics and Information Technology, Govt. of India.