Relevant bibliographies by topics / Vrram

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Vrram'

Author: Grafiati
Published: 19 July 2023

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Journal articles on the topic "Vrram"

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Sun, Wookyung, Sujin Choi, Bokyung Kim, and Hyungsoon Shin. "Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses." Journal of Nanoscience and Nanotechnology 20, no. 8 (August 1, 2020): 4730–34. http://dx.doi.org/10.1166/jnn.2020.17798.

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Amidst the considerable attention artificial intelligence (AI) has attracted in recent years, a neuromorphic chip that mimics the biological neuron has emerged as a promising technology. Memristor or Resistive random-access memory (RRAM) is widely used to implement a synaptic device. Recently, 3D vertical RRAM (VRRAM) has become a promising candidate to reducing resistive memory bit cost. This study investigates the operation principle of synapse in 3D VRRAM architecture. In these devices, the classification response current through a vertical pillar is set by applying a training algorithm to the memristors. The accuracy of neural networks with 3D VRRAM synapses was verified by using the HSPICE simulator to classify the alphabet in 7×7 character images. This simulation demonstrated that 3D VRRAMs are usable as synapses in a neural network system and that a 3D VRRAM synapse should be designed to consider the initial value of the memristor to prepare the training conditions for high classification accuracy. These results mean that a synaptic circuit using 3D VRRAM will become a key technology for implementing neural computing hardware.
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Chen, Zhisheng, Renjun Song, Qiang Huo, Qirui Ren, Chenrui Zhang, Linan Li, and Feng Zhang. "Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array." Micromachines 12, no. 6 (May 26, 2021): 614. http://dx.doi.org/10.3390/mi12060614.

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Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays.
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Sun, Wookyung, Sujin Choi, Bokyung Kim, and Junhee Park. "Three-Dimensional (3D) Vertical Resistive Random-Access Memory (VRRAM) Synapses for Neural Network Systems." Materials 12, no. 20 (October 22, 2019): 3451. http://dx.doi.org/10.3390/ma12203451.

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Memristor devices are generally suitable for incorporation in neuromorphic systems as synapses because they can be integrated into crossbar array circuits with high area efficiency. In the case of a two-dimensional (2D) crossbar array, however, the size of the array is proportional to the neural network’s depth and the number of its input and output nodes. This means that a 2D crossbar array is not suitable for a deep neural network. On the other hand, synapses that use a memristor with a 3D structure are suitable for implementing a neuromorphic chip for a multi-layered neural network. In this study, we propose a new optimization method for machine learning weight changes that considers the structural characteristics of a 3D vertical resistive random-access memory (VRRAM) structure for the first time. The newly proposed synapse operating principle of the 3D VRRAM structure can simplify the complexity of a neuron circuit. This study investigates the operating principle of 3D VRRAM synapses with comb-shaped word lines and demonstrates that the proposed 3D VRRAM structure will be a promising solution for a high-density neural network hardware system.
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Alimkhanuly, Batyrbek, Sanghoek Kim, Lok-won Kim, and Seunghyun Lee. "Electromagnetic Analysis of Vertical Resistive Memory with a Sub-nm Thick Electrode." Nanomaterials 10, no. 9 (August 20, 2020): 1634. http://dx.doi.org/10.3390/nano10091634.

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Resistive random access memories (RRAMs) are a type of resistive memory with two metal electrodes and a semi-insulating switching material in-between. As the persistent technology node downscaling continues in transistor technologies, RRAM designers also face similar device scaling challenges in simple cross-point arrays. For this reason, a cost-effective 3D vertical RRAM (VRRAM) structure which requires a single pivotal lithography step is attracting significant attention from both the scientific community and the industry. Integrating an extremely thin plane electrode to such a structure is a difficult but necessary step to enable high memory density. In addition, experimentally verifying and modeling such devices is an important step to designing RRAM arrays with a high noise margin, low resistive-capacitive (RC) delays, and stable switching characteristics. In this work, we conducted an electromagnetic analysis on a 3D vertical RRAM with atomically thin graphene electrodes and compared it with the conventional metal electrode. Based on the experimental device measurement results, we derived a theoretical basis and models for each VRRAM design that can be further utilized in the estimation of graphene-based 3D memory at the circuit and architecture levels. We concluded that a 71% increase in electromagnetic field strength was observed in a 0.3 nm thick graphene electrode when compared to a 5 nm thick metal electrode. Such an increase in the field led to much lower energy consumption and fluctuation range during RRAM switching. Due to unique graphene properties resulting in improved programming behavior, the graphene-based VRRAM can be a strong candidate for stacked storage devices in new memory computing platforms.
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Choi, Sujin, Wookyung Sun, and Hyungsoon Shin. "Analysis of Read Margin and Write Power Consumption of a 3-D Vertical RRAM (VRRAM) Crossbar Array." IEEE Journal of the Electron Devices Society 6 (2018): 1192–96. http://dx.doi.org/10.1109/jeds.2018.2873016.

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Wu, Min‐Ci, Yi‐Hsin Ting, Jui‐Yuan Chen, and Wen‐Wei Wu. "Low Power Consumption Nanofilamentary ECM and VCM Cells in a Single Sidewall of High‐Density VRRAM Arrays." Advanced Science 6, no. 24 (October 7, 2019): 1902363. http://dx.doi.org/10.1002/advs.201902363.

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Choi, Sujin, Wookyung Sun, and Hyungsoon Shin. "Analysis of Cell Variability Impact on a 3-D Vertical RRAM (VRRAM) Crossbar Array Using a Modified Lumping Method." IEEE Transactions on Electron Devices 66, no. 1 (January 2019): 759–65. http://dx.doi.org/10.1109/ted.2018.2878440.

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Yu, Jie, Woyu Zhang, Danian Dong, Wenxuan Sun, Jinru Lai, Xu Zheng, Tiancheng Gong, et al. "Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array." Micromachines 13, no. 2 (February 17, 2022): 308. http://dx.doi.org/10.3390/mi13020308.

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In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system’s operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 105 s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications.
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Lo, Shih-Che, and Hung-Hsu Tsai. "Design of 3D Virtual Reality in the Metaverse for Environmental Conservation Education Based on Cognitive Theory." Sensors 22, no. 21 (October 30, 2022): 8329. http://dx.doi.org/10.3390/s22218329.

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Background: Climate change causes devastating impacts with extreme weather conditions, such as flooding, polar ice caps melting, sea level rise, and droughts. Environmental conservation education is an important and ongoing project nowadays for all governments in the world. In this paper, a novel 3D virtual reality architecture in the metaverse (VRAM) is proposed to foster water resources education using modern information technology. Methods: A quasi-experimental study was performed to observe a comparison between learning involving VRAM and learning without VRAM. The 3D VRAM multimedia content comes from a picture book for learning environmental conservation concepts, based on the cognitive theory of multimedia learning to enhance human cognition. Learners wear VRAM helmets to run VRAM Android apps by entering the immersive environment for playing and/or interacting with 3D VRAM multimedia content in the metaverse. They shake their head to move the interaction sign to initiate interactive actions, such as replaying, going to consecutive video clips, displaying text annotations, and replying to questions when learning soil-and-water conservation course materials. Interactive portfolios of triggering actions are transferred to the cloud computing database immediately by the app. Results: Experimental results showed that participants who received instruction involving VRAM had significant improvement in their flow experience, learning motivation, learning interaction, self-efficacy, and presence in learning environmental conservation concepts. Conclusions: The novel VRAM is highly suitable for multimedia educational systems. Moreover, learners’ interactive VRAM portfolios can be analyzed by big-data analytics to understand behaviors for using VRAM in the future to improve the quality of environmental conservation education.
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Chaudhry, Arif, Jeremie D. Oliver, Krishna S. Vyas, Nho V. Tran, Jorys Martinez-Jorge, David Larson, Eric Dozois, Heidi Nelson, and Oscar J. Manrique. "Comparison of Outcomes in Oncoplastic Pelvic Reconstruction with VRAM versus Omental Flaps: A Large Cohort Analysis." Journal of Reconstructive Microsurgery 35, no. 06 (January 18, 2019): 425–29. http://dx.doi.org/10.1055/s-0038-1677524.

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Background The purpose of this study is to describe our experience and outcomes in oncoplastic pelvic reconstruction for patients who underwent either vertical rectus abdominis musculocutaneous (VRAM) or omental flap following abdominoperineal resection (APR) at a single tertiary care institution. Methods All patients who underwent pelvic reconstruction following APR with either VRAM or omental flaps from January 1992 to January 2017 were retrospectively reviewed. Patient demographics and relevant comorbidities including chemotherapy and radiation therapy data were collected and analyzed. In addition, margin status at the time of oncologic resection was analyzed. Flap-specific data were collected for each approach. Oncologic data collected included cancer type, stage at time of APR, and rate of tumor recurrence within the flap. Results A total of 562 patients were identified who underwent pelvic reconstruction with either VRAM or omental pedicle flaps. Of these, 274 (48.8%) underwent VRAM reconstruction and 288 (51.2%) underwent omental flap reconstruction. All margins were negative at time of cancer ablation surgery. Complications data included: seroma (VRAM = 2 [0.36%]; omentum = 32 [5.69%], p < 0.0001), wound dehiscence (VRAM = 31 [5.52%]; omentum = 17 [3.02%], p = 0.022), abscess (VRAM = 4 [0.71%]; omentum = 27 [4.8%], p < 0.0001), cellulitis (VRAM = 2 [0.36%]; omentum = 10 [1.78%], p = 0.025). Statistical comparison of tumor recurrence between these two reconstructive approaches showed a significantly higher recurrence rate in omental flaps compared with VRAM flaps (p = 0.000127). Conclusion The results of this study suggest a significantly higher tumor recurrence rate in omental flap pelvic reconstruction compared with VRAM flaps. This knowledge has the potential to influence surgical planning and flap selection in pelvic reconstruction.
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Dissertations / Theses on the topic "Vrram"

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Ezzadeen, Mona. "Conception d'un circuit dédié au calcul dans la mémoire à base de technologie 3D innovante." Electronic Thesis or Diss., Aix-Marseille, 2022. http://theses.univ-amu.fr.lama.univ-amu.fr/221212_EZZADEEN_955e754k888gvxorp699jljcho_TH.pdf.

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Avec le développement de l'internet des objets et de l'intelligence artificielle, le "déluge de données" est une réalité, poussant au développement de systèmes de calcul efficaces énergétiquement. Dans ce contexte, en effectuant le calcul directement à l'intérieur ou à proximité des mémoires, le paradigme de l'in/near-memory-computing (I/NMC) semble être une voie prometteuse. En effet, les transferts de données entre les mémoires et les unités de calcul sont très énergivores. Cependant, les classiques mémoires Flash souffrent de problèmes de miniaturisation et ne semblent pas facilement adaptées à l'I/NMC. Ceci n'est pas le cas de nouvelles technologies mémoires émergentes comme les ReRAM. Ces dernières souffrent cependant d'une variabilité importante, et nécessitent l'utilisation d'un transistor d'accès par bit (1T1R) pour limiter les courants de fuite, dégradant ainsi leur densité. Dans cette thèse, nous nous proposons de résoudre ces deux défis. Tout d'abord, l'impact de la variabilité des ReRAM sur les opérations de lecture et de calcul en mémoire est étudié, et de nouvelles techniques de calculs booléens robustes et à faible impact surfacique sont développées. Dans le contexte des réseaux de neurones, de nouveaux accélérateurs neuromorphiques à base de ReRAM sont proposés et caractérisés, visant une bonne robustesse face à la variabilité, un bon parallélisme et une efficacité énergétique élevée. Dans un deuxième temps, pour résoudre les problèmes de densité d'intégration, une nouvelle technologie de cube mémoire 3D à base de ReRAM 1T1R est proposée, pouvant à la fois être utilisée en tant que mémoire de type NOR 3D dense qu'en tant qu'accélérateur pour l'I/NMC
With the advent of edge devices and artificial intelligence, the data deluge is a reality, making energy-efficient computing systems a must-have. Unfortunately, classical von Neumann architectures suffer from the high cost of data transfers between memories and processing units. At the same time, CMOS scaling seems more and more challenging and costly to afford, limiting the chips' performance due to power consumption issues.In this context, bringing the computation directly inside or near memories (I/NMC) seems an appealing solution. However, data-centric applications require an important amount of non-volatile storage, and modern Flash memories suffer from scaling issues and are not very suited for I/NMC. On the other hand, emerging memory technologies such as ReRAM present very appealing memory performances, good scalability, and interesting I/NMC features. However, they suffer from variability issues and from a degraded density integration if an access transistor per bitcell (1T1R) is used to limit the sneak-path currents. This thesis work aims to overcome these two challenges. First, the variability impact on read and I/NMC operations is assessed and new robust and low-overhead ReRAM-based boolean operations are proposed. In the context of neural networks, new ReRAM-based neuromorphic accelerators are developed and characterized, with an emphasis on good robustness against variability, good parallelism, and high energy efficiency. Second, to resolve the density integration issues, an ultra-dense 3D 1T1R ReRAM-based Cube and its architecture are proposed, which can be used as a 3D NOR memory as well as a low overhead and energy-efficient I/NMC accelerator
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Bartholomé, Lenka [Verfasser], Vera [Akademischer Betreuer] Schellerer, and Vera [Gutachter] Schellerer. "Komplikationen am Hebedefekt nach vertikaler Rektus-abdominis-Muskel (VRAM)-Lappenplastik -Erfahrungen bei 192 Patienten- / Lenka Bartholomé ; Gutachter: Vera Schellerer ; Betreuer: Vera Schellerer." Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2019. http://d-nb.info/1201886821/34.

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Hsiung, W. C., and 熊玟清. "A Frame Store Designed with VRAM Approach to Radar Information." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/00034741765688514060.

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碩士
義守大學
電機工程研究所
83
A non-interlaced raster scan display which has a screen resolution of 1280X1024 pixels with 256 colors is suitable to be used to display the sampled radar data. There are 1280X1024X8 bits data stored in an eight plane frame store. The frame store is constructed by ten video random access memory devices (VRAM) with size of 256kX4 bits each. Using 386/486 CPU's protected mode and IBM ISA bus architecture, the frame store can be accessed by the microprocessors and multiple radar scan converters to store and transfer the data to the raster scan radar display improving the disadvantages of traditional radar display (Plan Position Indicator: PPI). This makes the architecture of frame store central to the radar display system. So, the major purpose of this paper is to describe the design and construction of a frame store. The access rate of frame store is an important factor which affects the performance of the radar display system. The multipe I/O port VRAM device are chosen to make up the frame store. VRAM has dual ports, the DRAM port and SAM prot, which can be operated independently. This increases the access rate of frame store. The line scan rate is divided cyclely to three memory access cycles. There are update read, update write, and read tranfer cycle (DRAM tranfers data to SAM for next screen refresh). The screen read cycle is executed in active video time during line scan rate as the SAM port operates independently. Five bytes data is read parallelly from frame store transfered into screen processor in 41.7ns time period. During the screen read cycle, the 8 bit data is fed serially to D/A converter to generate the red, green, and blue analog signals respectively for raster scan display. The pixel rate is 119.843 Mhz.
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Books on the topic "Vrram"

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Corporation, Toshiba. MOS memory (VRAM, SRAM). Tokyo: Toshiba Corporation, 1991.

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Corporation, Toshiba. MOS memory (VRAM): Data book. Tokyo: Toshiba Corporation, 1993.

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Book chapters on the topic "Vrram"

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Weik, Martin H. "VRAM." In Computer Science and Communications Dictionary, 1906. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_20965.

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Flügel, M. "VRAM-Lappen." In Fortschritte in der Chirurgie im letzten Jahrzehnt, 199. Berlin, Heidelberg: Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/978-3-662-07303-2_88.

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Erdmann, D., A. Petracic, M. Sauerbier, H. Menke, and G. Germann. "Der „Vertical/Transverse Rectus abdominis Muscle“ (VRAM/TRAM)-Lappen zur Deckung langstreckiger osteokutaner Defekte der Sternumregion." In Bilanz zur Jahrtausendwende, 1344–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-60248-1_378.

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Silva, Jason, Amy Jackson, and Justin Broyles. "Plastic Surgery and Flap Graft Management of Radial Forearm, VRAM, and TRAM Flaps in Critically Ill Cancer Patients." In Oncologic Critical Care, 1–9. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-74698-2_161-1.

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Silva, Jason, Amy Jackson, and Justin Broyles. "Plastic Surgery and Flap Graft Management of Radial Forearm, VRAM, and TRAM Flaps in Critically Ill Cancer Patients." In Oncologic Critical Care, 1719–26. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-74588-6_161.

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Lefèvre, Jérémie, and Emmanuel Tiret. "VRAM flap." In Operative Surgery of the Colon, Rectum and Anus, Sixth Edition, 675–81. CRC Press, 2015. http://dx.doi.org/10.1201/b18337-78.

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"altenheim norra vram." In raumverloren, 114–17. Birkhäuser, 2014. http://dx.doi.org/10.1515/9783038210856.114.

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"Norra Vram Nursing Home." In lost in space, 114–17. Birkhäuser, 2014. http://dx.doi.org/10.1515/9783038211204-021.

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Conference papers on the topic "Vrram"

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Piccolboni, G., G. Molas, D. Garbin, T. Werner, E. Vianello, B. DeSalvo, G. Ghibaudo, and L. Perniola. "Investigation of variability in Vertical Resistive RAM (VRRAM): Physical Model." In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.b-7-04.

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Baek, I. G., C. J. Park, H. Ju, D. J. Seong, H. S. Ahn, J. H. Kim, M. K. Yang, et al. "Realization of vertical resistive memory (VRRAM) using cost effective 3D process." In 2011 IEEE International Electron Devices Meeting (IEDM). IEEE, 2011. http://dx.doi.org/10.1109/iedm.2011.6131654.

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Piccolboni, G., G. Molas, J. M. Portal, R. Coquand, M. Bocquet, D. Garbin, E. Vianello, et al. "Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications." In 2015 IEEE International Electron Devices Meeting (IEDM). IEEE, 2015. http://dx.doi.org/10.1109/iedm.2015.7409717.

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Zhang, Leqi, Stefan Cosemans, Dirk J. Wouters, Bogdan Govoreanu, Guido Groeseneken, and Malgorzata Jurczak. "Analysis of vertical cross-point resistive memory (VRRAM) for 3D RRAM design." In 2013 5th IEEE International Memory Workshop (IMW). IEEE, 2013. http://dx.doi.org/10.1109/imw.2013.6582122.

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Wu, T. Y., Y. S. Chen, P. Y. Gu, W. S. Chen, H. Y. Lee, P. S. Chen, K. H. Tsai, et al. "Vertical resistive switching memory (VRRAM): A real 3D device demonstration and analysis of high-density application." In 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-tsa.2014.6839683.

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Gong, Tiancheng, Qing Luo, Hangbing Lv, Xiaoxin Xu, Jie Yu, Peng Yuan, Danian Dong, et al. "Switching and Failure Mechanism of Self-Selective Cell in 3D VRRAM by RTN-Based Defect Tracking Technique." In 2018 IEEE International Memory Workshop (IMW). IEEE, 2018. http://dx.doi.org/10.1109/imw.2018.8388852.

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Haitong Li, Tony F. Wu, Subhasish Mitra, and H. S. Philip Wong. "Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)." In 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2017. http://dx.doi.org/10.1109/vlsi-tsa.2017.7942490.

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Li, Haitong, Tony F. Wu, Abbas Rahimi, Kai-Shin Li, Miles Rusch, Chang-Hsien Lin, Juo-Luen Hsu, et al. "Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition." In 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 2016. http://dx.doi.org/10.1109/iedm.2016.7838428.

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Park, Seong-Geon, Min Kyu Yang, Hyunsu Ju, Dong-Jun Seong, Jung Moo Lee, Eunmi Kim, Seungjae Jung, et al. "A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)." In 2012 IEEE International Electron Devices Meeting (IEDM). IEEE, 2012. http://dx.doi.org/10.1109/iedm.2012.6479084.

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Wong, Tamar Hei Ting, and Kee Ka Ki Wong. "VRgram." In SA '16: SIGGRAPH Asia 2016. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2996376.2996380.

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