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Dissertations / Theses on the topic 'VLSM'

Author: Grafiati

Published: 9 March 2023

Last updated: 10 March 2023

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1

COMI, ALESSANDRO. "Memoria verbale nei pazienti con glioma cerebrale." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2015. http://hdl.handle.net/10281/64636.

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Si sono studiati i correlati neurali dei sistemi di memoria verbale in pazienti con glioma cerebrale. Si tratta di pazienti sottoposti ad asportazione di lesioni cerebrali dell’emisfero dominante, in cui le funzioni mnestiche sono state valutate mediante prove specifiche prima e dopo l’intervento chirurgico, per verificare l’impatto funzionale dell’espanso e della rimozione della lesione. L’indagine anatomo-funzionale si è inoltre avvalsa delle tecniche di mappaggio cerebrale in awake surgery laddove l’intervento è stato eseguito in anestesia asleep-awake per la rimozione dei tumori estesi alle aree del linguaggio. Nel primo studio si esamina l’impatto della crescita tumorale sulla memoria verbale: le valutazioni neuropsicologiche effettuate pre-trattamento hanno permesso di identificare difficoltà conclamate o lievi compromissioni, che variano in funzione delle aree di infiltrazione tumorale; la prospettiva anatomo-clinica ha fornito una conferma dell’esistenza di sistemi di memoria verbale in distretti anatomo-funzionali differenti. Il secondo studio esamina i correlati neurali della memoria verbale a breve termine in un gruppo di pazienti sottoposti a mappaggio cerebrale in awake surgery: la stimolazione corticale e sottocorticale diretta ha permesso di identificare un circuito fronto-parietale coinvolto nei processi di MBT; l’analisi degli errori registrati durante i test intraoperatori ha permesso inoltre di distinguere il substrato neurale delle due componenti del circuito fonologico. Il terzo studio valuta gli effetti della lobectomia temporale sulla memoria a lungo termine; le prove mnestiche somministrate ad una settimana dall’intervento e dopo tre mesi hanno evidenziato prestazioni patologiche che non vanno incontro ad un rapido recupero nei pazienti che hanno subito la rimozione di un circuito cortico-sottocorticale esteso dalle regioni temporo-polari a quelle temporali mesiali; lo studio anatomico mediante voxel-based lesion-symptom mapping delle aree asportate ha permesso di verificare i correlati neurali di memoria semantica e apprendimento verbale. Questi risultati confermano che i pazienti con tumore cerebrali possono fornire dati interessanti nello studio dei deficit neuropsicologici.

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2

Tjan-Heijnen, Vivianne C. G. "De vlam." Maastricht : Maastricht : Maastricht University ; University Library, Universiteit Maastricht [host], 2007. http://arno.unimaas.nl/show.cgi?fid=13128.

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3

Chaudhray, Kamal. "VLSI routing." Thesis, University of Cambridge, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359367.

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4

Pope, Michael T. "VLSI systems simulation /." Title page, table of contents and abstract only, 1991. http://web4.library.adelaide.edu.au/theses/09PH/09php826.pdf.

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5

Alvelda, Phillip. "VLSI microdisplay technology." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/12019.

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6

Mhar, Javeed I. "VLSI design methodology." Thesis, University of Edinburgh, 1990. http://hdl.handle.net/1842/11855.

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The development of FIRST was a significant step in the field of silicon compilation. With FIRST, bit-serial signal processing systems could be rapidly implemented in silicon by high-level designers without requiring layout expertise. This thesis explores extensions to the compiler, but the methodology and techniques are not specific to FIRST and could be used in the more general VLSI arena. One major theme is the use of process independent layout, allowing the rapid update of a cell library to current state of the art process rules. After surveying other layout strategies, one particular layout style, gate matrix, was evaluated through the manual layout of a bit-serial, two's complement, multiplier utilising novel architectural features. The operation and architectural features of the multiplier are described, as these features were to be incorporated as options in newly generated cell libraries. SECOND, a full span silicon compiler; taking the high-level input description of FIRST but synthesizing layout to a process independent form (gate matrix) was developed using ideas gained from the manual assembly procedure. SECOND maintains and extends the hierarchy of FIRST using different assembly strategies for differing levels of hierarchy in the synthesis procedure. The hierarchy is described and the placement, routing and assembly procedures of the new elements of the hierarchy are covered. The automation tools used to generate the gate matrix layout of the lowest hierarchy level of SECOND are covered in a separate chapter. Using the same concepts of hierarchy, a tool ENGEN which transforms FIRST intermediate code to a gate level network description in HILO is also described as an alternative to SECOND in the search for process independence. The thesis ends with a suggestion of a bit-serial/bit-parallel frame for encouraging the acceptability of bit-serial systems.

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7

Nedelchev, Ivailo Marinov. "Asynchronous VLSI design." Thesis, University of Surrey, 1995. http://epubs.surrey.ac.uk/844150/.

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This thesis describes the background and implementation of a novel silicon compiler from a high-level programming language, OCCAM(async), to asynchronous CMOS circuits. The compilation scheme is based on a process algebra description of a concurrent system. This Algebra is called Delay-Insensitive Algebra and is based on CSP but allows the user more freedom in communication protocols. The thesis reviews and compares various, existing, design styles and their practical aspects for asynchronous design are also discussed. The syntax and the operational semantics of OCCAM(async) are defined and, on this basis, the new compilation technique is described with its underlying CMOS circuitry. The implementations of various, novel, library cells are also discussed. The compilation technique is illustrated throughout the thesis with practical examples. It is also compared to an existing synthesis tool, Tangram, which has been developed at Phillips Research Laboratories. The thesis concludes with the place and the role of OCCAM(async) in the contemporary CMOS design, and the future aspects in continuing this research into the full, design-process automation.

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8

Kao, De-Yu. "VLSI interconnect synthesis /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1998. http://wwwlib.umi.com/cr/ucsd/fullcit?p9824659.

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9

Henkelmann, Heiko. "Automatisierter Systementwurf in der digitalen Signalverarbeitung auf der Basis von Schaltungsstrukturen der Restklassenarithmetik." [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=975327941.

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10

Schimpfle, Christian Vinzenz. "Entwurfsmethoden für verlustarme integrierte Schaltungen." [S.l. : s.n.], 2000. http://deposit.ddb.de/cgi-bin/dokserv?idn=959795537.

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11

Mende, Ole. "Laserumschalterstruktur in CMOS-Technologie." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=969347189.

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12

Landwehr, Birger. "ILP-basierte Mikroarchitektur-Synthese mit komplexen Bausteinbibliotheken : Wege zu kleineren und schnelleren Schaltungen unter Einsatz algebraischer Optimierungen /." Düsseldorf : VDI-Verl, 1998. http://www.gbv.de/dms/bs/toc/251120007.pdf.

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13

Spray, Andrew J. C. "VLSI parallel processing architectures." Thesis, Bangor University, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278108.

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14

Šťastná, Hilda. "Simulace CMOS VLSI obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363732.

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This diploma thesis deals with processes of electrical circuits calculations in the last years' worldwide standards like Dymola, MATLAB, Maple or SPICE applications. Circuits calculations are linked with methods for solving linear differential equations, used in this work also by verification of functionality of designed models for CMOS inverter, CMOS NAND, CMOS NOR. Numerical integration method in combination with Taylor series is a suitable method also for parallel calculations of CMOS VLSI circuits. CMOS circuits simulation was implemented with this method in applications in MATLAB language, solving circuits, represented by differential equations. Functionality of the applications was verified by some real examples. Significant acceleration of calculations using Taylor series compared to other methods is an important factor in choosing methods used in circuit simulations.

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15

Zolghadrasli, Alireza Anceau François. "Correction et traitement d'images des circuits VLSI issues d'un microscope électronique à balayage." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00315579.

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16

Snepscheut, Jan L. A. van de Snepscheut Jan L. A. van de Snepscheut Jan L. A. van de Snepscheut Jan L. A. van de. "Trace theory and VLSI design /." Berlin : Springer, 1985. http://sfx.ethz.ch:9003/sfx_locater?sid=ALEPH:EBI01&issn=0302-9743&volume=200.

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17

Lüthi, Peter Jan. "VLSI circuits for MIMO preprocessing." Konstanz Hartung-Gorre, 2009. http://d-nb.info/100000290X/04.

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18

Yao, Bo. "Physical planning of VLSI layout /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2005. http://wwwlib.umi.com/cr/ucsd/fullcit?p3189794.

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19

Wang, Li. "VLSI design of heart model." College Park, Md. : University of Maryland, 2007. http://hdl.handle.net/1903/6747.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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20

Blum, Richard Alan. "An analog VLSI centroid imager." Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14826.

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21

Morris, Tonia Gay. "Analog VLSI visual attention systems." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/15010.

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22

Măndoiu, Ion I. "Approximation algorithms for VLSI routing." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/9128.

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23

Marnane, William Peter. "Structured test of VLSI arrays." Thesis, University of Oxford, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.238118.

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24

Swisher, Joel V. "Circuit recognition of VLSI layouts." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/25736.

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25

Zagourakis, Emmanouil N. "Recognition of VLSI module isomorphism." Thesis, Monterey, California. Naval Postgraduate School, 1990. http://hdl.handle.net/10945/30728.

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Approved for public release, distribution unlimited
The purpose of this study is to determine whether or not a program could be developed to examine isomorphism between parts of a VLSI layout. Many simulation files, obtained through Magic's hierarchical extractor, were analyzed in order to develop a C program to accomplish recognition in several types of gates. This recognition gives signatures in order to check for isomorphism. The development and design of the algorithms used in different parts of the program are described. Results demonstrate that recognition of elements in a CMOS circuit is possible, even with moderate complexity structures. An appendix with the C program listings is included.

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26

Read, Simon. "Formal methods for VLSI design." Thesis, University of Manchester, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239786.

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27

Crawley, David George. "Time optimal arithmetic for VLSI." Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239081.

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28

Alvelda, Phillip. "VLSI microdisplays and optoelectronic technology." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/11401.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Includes bibliographical references (leaves 103-105).
by Phillip Alvelda.
Ph.D.

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29

Wee, Keng Hoong. "An analog VLSI vocal tract." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/43053.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 165-168).
Increasingly, circuit models of biology are being used to improve performance in engineering systems. For example, silicon-cochlea-like models have led to improved speech recognition in noise and low-power cochlear-implant processors for the deaf. A promising approach to improve the naturalness of synthetic speech is to exploit bioinspired models of speech production with low bit-rate control parameters. In this work, we present the first experimental integrated-circuit vocal tract by mapping fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The 275 jW analog vocal tract chip can be used with auditory processors in a feedback speech locked loop to implement speech recognition that is potentially robust in noise. Our use of a physiological model of the human vocal tract enables the analog vocal tract chip to synthesize speech signals of interest, using articulatory parameters that are intrinsically compact and linearly interpolatable. Previous attempts that take advantage of the powerful analysis-by-synthesis method employed computationally expensive approaches to articulatory synthesis using digital computation. Our strategy uses an analog vocal tract to drastically reduce power consumption, enables real-time performance and could be useful in portable speech processing systems of moderate complexity, e.g., in cell phones, digital assistants and bionic speech-prosthesis systems.
by Keng Hoong Wee.
Ph.D.

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30

Sun, Chen Ph D. Massachusetts Institute of Technology. "Silicon-photonics for VLSI systems." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99784.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 173-183).
As raw compute power of a single chip continues to scale into the multi-teraflop regime, the processor I/O communication fabric must scale proportionally in order to prevent a performance bottleneck. As electrical wires suffer from high channel losses, pin-count constraints, and crosstalk, they are projected to fall short of the demands required by future memory systems. Silicon-photonic optical links overcome the fundamental tradeoffs of electrical wires; dense wavelength division multiplexing (DWDM) - where multiple data channels share a single waveguide or fiber to greatly extend bandwidth density - and the potential to combine at chip-scale with a very large scale integrated (VLSI) CMOS electrical chip make them a promising alternative for next-generation processor I/O. The key device for VLSI photonics is the optical microring resonator, a compact micrometer-scale device enabling energy-efficient modulation, DWDM channel selection, and sometimes even photo-detection. While these advantages have generated considerable interest in silicon-photonics, present-day integration efforts have been limited in scale owing to the difficulty of integration with advanced electronics and the sensitivity of microring resonators to both process and thermal variations. This thesis develops and demonstrates the pieces of a photonically-interconnected processor-to-memory system. We demonstrate a complete optical transceiver platform in a commercial 45 nm SOI process, showing that optical devices can be integrated into an advanced, commercial CMOS SOI process even without any changes to the manufacturing steps of the native process. To show that photonic interconnects are viable even for commoditized and cost-sensitive memory, we develop the first monolithic electronic-photonic links in bulk CMOS. As the stabilization of ring resonators is critical for use in VLSI systems, we contribute to the understanding of process and thermal variations on microring resonators, leading to the demonstration of a complete auto-locking microring tuning system that is agnostic to the transmitted data sequence and suitable for unencoded low-latency processor-to-memory traffic. Finally, the technology and methods developed in this work culminate in the demonstration of the world's first processor chip with integrated photonic interconnects, which uses monolithically integrated photonic devices to optically communicate to main memory.
by Chen Sun.
Ph. D.

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31

Smith, Stewart Gresty. "Serial-data computation in VLSI." Thesis, University of Edinburgh, 1987. http://hdl.handle.net/1842/11922.

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32

Wang, Guoyu. "CMOS VLSI circuits for imaging." Thesis, University of Edinburgh, 1993. http://hdl.handle.net/1842/13190.

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MOS technology is very attractive for achieving low-cost miniature cameras. It also permits the inclusion of the sensor with other control and processing functions on the same chip. However, this technique has never been developed to the point at which MOS sensor performance matches that of CCD cameras. The objective of this project has been to develop design techniques to achieve single chip video cameras, in unmodified CMOS processes, with improved performance (aimed to match the performance of CCD cameras) and enhanced functionality. In this thesis, following an overview of solid state image sensors, the fundamentals and basic sensor array structure suitable for CMOS implementation is presented. The pixel structure and sensor array, the sense amplifier, scan circuitry, and the output amplifier and buffer are described. Noise analysis is also presented with the main noise sources highlighted and compensation schemes proposed. Other useful on-chip techniques including auto-exposure control, gain control, and data conversion are then discussed. A successfully designed device, named ASIS-1011 which incorporates all these circuit techniques, is finally reported. This design shows that the aim of achieving good picture quality and incorporating sensors and control logic on one chip can be achieved.

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33

Grebowsky, Gerald J., and Carol T. Dominy. "VLSI High Speed Packet Processor." International Foundation for Telemetering, 1988. http://hdl.handle.net/10150/615067.

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International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada
The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a Packet Processor card utilizing semi-custom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multi-channel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the Packet Processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semi-custom VLSI logic.

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34

Rosser, Paul John. "Titanium disilicide for VLSI applications." Thesis, University of Surrey, 1987. http://epubs.surrey.ac.uk/847968/.

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This thesis demonstrates that the formation of titanium disilicide for gate level interconnects in silicon VLSI processes is possible, and is compatible with the processes considered. By using this new material the operating speed of fine geometry integrated circuits can be increased. The first two chapters consider the choice of titanium disilicide as a replacement for polysilicon. A process schedule is developed which enables the deposition and annealing of cosputtered films of titanium and silicon. By carefully controlling their deposition, cosputtered films have been annealed in both standard diffusion furnaces and also in rapid isothermal anneal (RIA) systems. This success in annealing titanium disilicide films in a RIA system is a world first. Next a process schedule for the deposition and anneal of titanium films over silicon is determined. The reaction of the film with the anneal ambient and the movement of impurities inevitably present in the titanium film is considered in some detail. This work was the first to highlight the benefits gained from the use of nitrogen as the anneal ambient. Self-aligned processes rely on the interaction between titanium and silicon dioxide being negligible. The silicide formation anneal is therefore optimised to minimise this. Finally, reaction of the silicide with common dopants and with both oxidising and nitriding ambients is presented. A novel method of forming a titanium nitride over silicide contact structure is developed. In summary, this thesis demonstrates how a titanium disilicide based metallisation can be implemented into an existing MOS process.

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35

Reimann, Tiago Jose. "Roteamento global de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/71269.

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Este trabalho apresenta a implementação de um roteador global de circuitos integrados capaz de tratar os problemas de roteamento atuais, utilizando como referência para avaliação os circuitos de benchmark publicados durante as competições de roteamento global realizadas no ACM International Symposium on Physical Design 2007 e 2008. O roteador global desenvolvido utiliza como ferramenta principal a técnica de ripup and reroute associada às técnicas de roteamento monotônico e maze routing, ambas com grande histórico de uso nas ferramentas acadêmicas descritas também neste trabalho. O desenvolvimento da ferramenta também possui características diferenciadas e únicas, com um novo método de ordenamento das redes durante a fase de rip-up and reroute. Para a geração dos resultados foram definidas duas versões diferentes da ferramenta, sendo estas duas versões analisadas com duas diferentes técnicas de construção das árvores de roteamento, gerando no total quatro configurações da ferramenta. Como decisão de projeto, a versão principal utilizada no desenvolvimento e discussão dos resultados é a versão que prioriza a qualidade do roteamento, utilizando MSTs para construção das árvores de roteamento. Os resultados mostram que o roteador global desenvolvido é capaz de gerar resultados com boa qualidade mesmo sem fazer uso de técnicas de identificação de áreas de congestionamento, sem otimizações pós-roteamento e sem nenhuma forma de ajuste (tuning) para os diferentes circuitos de benchmark, apesar de ainda ter tempo de execução acima dos apresentados por outras ferramentas acadêmicas. O foco durante o processo de desenvolvimento e implementação da ferramenta foram os circuitos mais recentes, entretanto a ferramenta obteve ótimos resultados também para os circuitos publicados no ISPD 1998, gerando soluções com qualidade similar ou melhor que as reportadas na literatura. A diferença dos resultados deste trabalho em relação aos melhores resultados dos roteadores globais com código disponível, para circuitos 3D lançados no ISPD 2008 é de, em média, 1,78%1 na métrica de comprimento de fio sem considerar o custo das vias e de 15,56% considerando o custo da via como uma unidade de comprimento de fio (ISPD 2008), para a versão voltada a qualidade de roteamento. Já para a versão da ferramenta que busca a convergência o mais rápido possível a diferença foi de 3,39% e 16,32%, respectivamente. As maiores diferenças são encontradas nos circuitos mais difíceis de gerar uma solução sem violações. Isso mostra como as técnicas de identificação de região podem contribuir tanto para uma convergência mais rápida quanto para evitar que fios passem por rotas desnecessárias durante a fase de negociação. Na métrica que avalia as vias como custo de uma unidade de comprimento, os resultados obtidos apresentam em média 18,67% maior comprimento de fio que os melhores resultados da literatura, sendo que dois circuitos com solução sem violações2 apresentam resultado com violações utilizando a ferramenta desenvolvida neste trabalho.
This work describes the implementation of an integrated circuit global router capable of handling the current routing problems, using as a reference the evaluation of benchmark circuits from the two global routing contests held in ISPD 2007 and 2008. The developed global router uses rip-up and reroute as the main technique associated with monotonic and maze routing techniques, both with large history of use in academic tools, also described in this work. The tool also has distinctive and unique characteristics, with a new method of net ordering during the rip-up and reroute stage. In order to generate the results were defined two different versions of the tool analyzed with two different techniques of routing tree construction, generating a total of four configurations. As a design decision, the major version used in the development and discussion of results is the version that prioritizes the routing quality, using MSTs for tree construction. The results show that the global router developed is able to generate good results even without making use of techniques to identify congestion areas, without post-routing optimizations and without any form of tuning for the different benchmark circuits, despite having run time above other academic tools. The focus during the development and implementation of the tool were the newer circuits, however the tool also obtained excellent results for the circuits released in ISPD 1998, generating solutions with similar quality or better than those reported in the literature. The difference in the results of this work over the best results generated with the available code global routers for 3D circuits released in ISPD 2008 is, on average, 2.53% in wirelength metric without considering the cost of vias and 18.34% considering the cost of the vias as one wirelength unit (ISPD 2008), for the best routing quality version. As for the version of the tool that seeks convergence as soon as possible the difference was 3.82% and 17.03%, respectively. The largest differences were found in the most difficult circuits to generate a solution without violations. This shows how the techniques of congested region identification can contribute to both a faster convergence and to avoid unnecessary wire detours during the negotiation phase. In the metric that evaluates the cost of vias as one wirelength unit, the results show an average of 22.5% greater wirelength than the best results found in literature. Also, the developed global router was unable to find a violation free solution for two circuits that are known to have a violation free solution3.

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36

GUIGNET, JEAN-BRUCE. "Abstraction fonctionnelle des composants vlsi." Paris 6, 1998. http://www.theses.fr/1998PA066154.

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L'abstraction fonctionnelle des composants vlsi est une methode qui permet de remonter le descriptif comportemental d'un composant vlsi a partir de sa description informatique au niveau masque. La methode qui fait l'objet de cette these met en oeuvre des techniques de reconnaissance de formes. Un langage de description des circuits a reconnaitre a aussi ete specialement elabore a cet effet.

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37

Sprague, Alan P. "Problems in VLSI layout design /." The Ohio State University, 1988. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487597424138645.

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38

So, Frank Cheung Tao Nicolet Marc-A. Nicolet Marc-A. "Diffusion barriers for VLSI applications /." Diss., Pasadena, Calif. : California Institute of Technology, 1988. http://resolver.caltech.edu/CaltechETD:etd-02012007-110846.

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39

Benson, Ronald Gary Hopfield John J. "Analog VLSI supervised learning system /." Diss., Pasadena, Calif. : California Institute of Technology, 1994. http://resolver.caltech.edu/CaltechETD:etd-06152004-095124.

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40

Liu, Bao. "VLSI interconnect synthesis and prediction /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3077807.

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41

Shope, David Allen 1958. "Thermal characterization of VLSI packaging." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276686.

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With electronic packaging becoming more complex, simple hand methods to model the thermal performance of the package are insufficient. As computer aided modeling methods came into use, a test system was developed to verify the predictions produced by such modeling methods. The test system is evaluated for operation and performance. Further, the premise of this type of test (the accurate calibration of packaged temperature-sensitive-parameter devices can be done) is investigated using a series of comparative tests. From this information, causes of possible/probable errors in calibration are identified and related to the different methodologies and devices used. Finally, conclusions are presented regarding the further improvement of the test system and methodologies used in this type of testing.

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Tang, Maolin. "Intelligent approaches to VLSI routing." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2000. https://ro.ecu.edu.au/theses/1375.

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Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including symbolic intelligence and computational intelligence, to solve three VLSI routing problems: Three-Dimensional (3-D) Shortest Path Connection, Switchbox Routing and Constrained Via Minimization. The 3-D shortest path connection is a fundamental problem in VLSI routing. It aims to connect two terminals of a net that are distributed in a 3-D routing space subject to technological constraints and performance requirements. Aiming at increasing computation speed and decreasing storage space requirements, we present a new A* algorithm for the 3-D shortest path connection problem in this thesis. This new A*algorithm uses an economical representation and adopts a novel back- trace technique. It is shown that this algorithm can guarantee to find a path if one exists and the path found is the shortest one. In addition, its computation speed is fast, especially when routed nets are spare. The computational complexities of this A* algorithm at the best case and the worst case are O(Ɩ) and 0(Ɩ3), respectively, where Ɩ is the shortest path length between the two terminals. Most importantly, this A' algorithm is superior to other shortest path connection algorithms as it is economical in terms of storage space requirement, i.e., 1 bit/grid. The switchbox routing problem aims to connect terminals at regular intervals on the four sides of a rectangle routing region. From a computational point of view, the problem is NP-hard. Furthermore, it is extremely complicated and as the consequence no existing algorithm can guarantee to find a solution even if one exists no matter how high the complexity of the algorithm is. Previous approaches to the switch box routing problem can be divided into algorithmic approaches and knowledge-based approaches. The algorithmic approaches are efficient in computational time, but they are unsucessful at achieving high routing completion rate, especially for some dense and complicated switchbox routing problems. On the other hand, the knowledge-based approaches can achieve high routing completion rate, but they are not efficient in computation speed. In this thesis we present a hybrid approach to the switchbox routing problem. This hybrid approach is based on a new knowledge-based routing technique, namely synchronized routing, and combines some efficient algorithmic routing techniques. Experimental results show it can achieve the high routing completion rate of the knowledge-based approaches and the high efficiency of the algorithmic approaches. The constrained via minimization is an important optimization problem in VLSI routing. Its objective is to minimize the number of vias introduced in VLSI routing. From computational perspective, the constrained via minimization is NP-complete. Although for a special case where the number of wire segments splits at a via candidate is not more than three, elegant theoretical results have been obtained. For a general case in which there exist more than three wire segment splits at a via candidate few approaches have been proposed, and those approaches are only suitable for tackling some particular routing styles and are difficult or impossible to adjust to meet practical requirements. In this thesis we propose a new graph-theoretic model, namely switching graph model, for the constrained via minimization problem. The switching graph model can represent both grid-based and grid less routing problems, and allows arbitrary wire segments split at a via candidate. Then on the basis of the model, we present the first genetic algorithm for the constrained via minimization problem. This genetic algorithm can tackle various kinds of routing styles and be configured to meet practical constraints. Experimental results show that the genetic algorithm can find the optimal solutions for most cases in reasonable time.

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Tumelero, Diego. "Exploração de paralelismo no roteamento global de circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/119081.

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Com o crescente aumento das funcionalidades dos circuitos integrados, existe um aumento consequente da complexidade do projeto dos mesmos. O fluxo de projeto de circuitos integrados inclui em um de seus passos o roteamento, que consiste em criar fios que interconectam as células do circuito. Devido à complexidade, o roteamento é dividido em global e detalhado. O roteamento global de circuitos VLSI é uma das tarefas mais complexas do fluxo de síntese física, sendo classificado como um problema NP-completo. Neste trabalho, além de realizar um levantamento de trabalhos que utilizam as principais técnicas de paralelismo com o objetivo de acelerar o processamento do roteamento global, foram realizadas análises nos arquivos de benchmark do ISPD 2007/08. Com base nestas análises foi proposto um método que agrupa as redes para então verificar a existência de dependência de dados em cada grupo. Esta verificação de dependência de dados, que chamamos neste trabalho de colisor, tem por objetivo, criar fluxos de redes independentes umas das outras para o processamento em paralelo, ou seja, ajudar a implementação do roteamento independente de redes. Os resultados demonstram que esta separação em grupos, aliada com a comparação concorrente dos grupos, podem reduzir em 67x o tempo de execução do colisor de redes se comparada com a versão sequencial e sem a utilização de grupos. Também foi obtido um ganho de 10x ao comparar a versão com agrupamentos sequencial com a versão paralela.
With the increasing of the functionality of integrated circuits, there is a consequent increase in the complexity of the design. The IC design flow includes the routing in one of its steps, which is to create wires that interconnect the circuit cells. Because of the complexity, routing is divided into global and detailed. The global routing of VLSI circuits is one of the most complex tasks in the flow of physical synthesis and it's classified as an NP-complete problem. In this work, a parallel computing techniques survey was applied to the VLSI global routing in order to accelerate the global routing processing analyzes. This analyzes was performed on the ISPD 2007/08 benchmark files. We proposed a method that groups the networks and then check for data dependence in each group based on these analyzes. This data dependency checking, we call this checking of collider, aims to create flow nets independent of each other for processing in parallel, or help implement the independent routing networks. The results demonstrate that this separation into groups, together with the competitor comparison of groups, can reduce 67x in the collider networks runtime compared with the sequential release and without the use of groups. It was also obtained a gain of 10x when comparing the version with sequential clusters with the parallel version.

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BADAOUI, RAOUL. "APPROACHES FOR PARASITIC-INCLUSIVE SYMBOLIC CIRCUIT REPRESENTATION AND EXTRACTION FOR SYNTHESIS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132193275.

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Jayakumar, Nikhil. "Minimizing and exploiting leakage in VLSI." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1249.

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Carrabina, Bordoll Jordi. "Xarxes neuronals VLSI d'alta velocitat/capacitat." Doctoral thesis, Universitat Autònoma de Barcelona, 1991. http://hdl.handle.net/10803/3062.

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Brenner, Ulrich. "Theory and practice of VLSI placement." [S.l.] : [s.n.], 2005. http://deposit.ddb.de/cgi-bin/dokserv?idn=980166659.

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Fragnière, Eric. "Analogue VLSI emulation of the cochlea /." Lausanne, 1998. http://library.epfl.ch/theses/?nr=1796.

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Zhou, Shuo. "Static timing analysis in VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3207193.

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Thesis (Ph. D.)--University of California, San Diego, 2006.
Title from first page of PDF file (viewed May 18, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 110-113).

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Wang, Qinke. "Analytical methods for VLSI module placement." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3211381.

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Thesis (Ph. D.)--University of California, San Diego, 2006.
Title from first page of PDF file (viewed June 13, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 126-139).

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