Relevant bibliographies by topics / VLSM

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'VLSM'

Author: Grafiati
Published: 9 March 2023
Last updated: 10 March 2023

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Journal articles on the topic "VLSM"

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Cameron, S. M., V. I. Nikora, and M. T. Stewart. "Very-large-scale motions in rough-bed open-channel flow." Journal of Fluid Mechanics 814 (February 9, 2017): 416–29. http://dx.doi.org/10.1017/jfm.2017.24.

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Long-duration particle image velocimetry measurements in rough-bed open-channel flows (OCFs) reveal that the pre-multiplied spectra of the streamwise velocity have a bimodal distribution due to the presence of large- and very-large-scale motions (LSMs and VLSMs, respectively). The existence of VLSMs in boundary layers, pipes and closed channels has been acknowledged for some time, but strong supporting evidence for their presence in OCF has been lacking. The data reported in this paper fill this gap. Length scales of the LSMs and VLSMs in OCF exhibit different scaling properties; whereas the streamwise length of the LSM scales with the flow depth, the VLSM streamwise length does not scale purely with flow depth and may additionally depend on other scales such as the channel width, roughness height or viscous length. The transverse extent of the LSMs was found to increase with increasing elevation, but the VLSM transverse scale is anchored around two flow depths. The origin and nature of LSMs and VLSMs are still to be resolved, but differences in their scaling suggest that VLSMs in rough-bed OCFs form independently rather than as a spatial alignment of LSMs.
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Dasmen, Rahmat Novrianda. "IMPLEMENTASI METODE VLSM (VARIABLE LENGTH SUBNET MASK) PADA PEMETAAN IP ADDRESS LAN (LOCAL AREA NETWORK) STIPER SRWIGAMA PALEMBANG." Computatio : Journal of Computer Science and Information Systems 2, no. 2 (October 31, 2018): 112. http://dx.doi.org/10.24912/computatio.v2i2.1703.

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Pemetaan IP (Internet Protocol) Address pada setiap user yang ada di LAN (Local Area Network) STIPER Sriwigama Palembang saat ini masih dilakukan secara manual dan terkadang tanpa mencatat IP address yang telah diberikan pada user-user sebelumnya sehingga terjadi kesamaan IP address yang menyebabkan bentrokan saat pengiriman data. Hal inilah yang menjadi penyebab dasar sehingga peneliti bermaksud mengimplementasikan metode VLSM (Variable Length Subnet Mask) sehingga dapat memetakan IP address untuk user ke dalam beberapa bagian. Pada STIPER Sriwigama Palembang dibagi beberapa bagian user yaitu : Ketua, Wakil Ketua, LPPM, Administrasi, Dosen, Staff, Perpustakaan dan Mahasiswa. Perhitungan pemetaan IP address dengan metode VLSM ini diawali dari jumlah user yang terbanyak dari beberapa bagian yang telah dibagi di atas. Pemetaan IP ini menjadi solusi dari permasalahan yang terjadi pada STIPER Sriwigama Palembang sehingga dengan metode VLSM tidak lagi terjadi bentrokan IP address karena setiap user telah memperoleh IP address dan subnet mask yang berbeda-beda.
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Niki, Chiharu, Takatsune Kumada, Takashi Maruyama, Manabu Tamura, Takakazu Kawamata, and Yoshihiro Muragaki. "Primary Cognitive Factors Impaired after Glioma Surgery and Associated Brain Regions." Behavioural Neurology 2020 (March 25, 2020): 1–9. http://dx.doi.org/10.1155/2020/7941689.

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Previous studies have shown that cognitive impairments in patients with brain tumors are not severe. However, to preserve the postsurgical QOL of patients with brain tumors, it is important to identify “primary” cognitive functions and associated brain regions that are more vulnerable to cognitive impairments following surgery. The objective of this study was to investigate primary cognitive factors affecting not only simple cognitive tasks but also several other cognitive tasks and associated brain regions. Patients with glioma in the left (n=33) and the right (n=21) hemisphere participated in the study. Seven neuropsychological tasks from five cognitive domains were conducted pre- and 6 months postoperation. Factor analyses were conducted to identify “primary” common cognitive functions affecting the task performance in left and right glioma groups. Next, lesion analyses were performed using voxel-based lesion-symptom mapping (VLSM) to identify critical brain regions related to impairments of the primary cognitive functions. Factor analysis revealed two primary cognitive components in each glioma group. The first cognitive component in the left glioma group affected the digit span forward and backward tasks and concept shifting and the letter-digit substitution tasks. VLSM analysis revealed significant regions from the posterior middle temporal gyri to the supramarginal gyrus. The second cognitive component affected verbal memory, and verbal fluency tasks and VLSM analysis indicated two different significant regions, the medial temporal regions and the middle temporal gyrus to the posterior parietal lobes. The first cognitive component in the right glioma group affected positive and negative factor loadings on the task, such that the positive cognitive component affected only the Stroop color-word task. VLSM related to deficits of the Stroop task revealed significant regions in the anterior medial frontal cortex. On the other hand, the negative component affected concept shifting, word fluency, and digit span forward tasks, and VLSM revealed significant regions in the right inferior frontal cortex. It is suggested that primary cognitive functions related to specific brain regions were possibly affected by glioma resection.
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Wang, G., and D. H. Richter. "Two mechanisms of modulation of very-large-scale motions by inertial particles in open channel flow." Journal of Fluid Mechanics 868 (April 15, 2019): 538–59. http://dx.doi.org/10.1017/jfm.2019.210.

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Very-large-scale motions (VLSMs) and large-scale motions (LSMs) coexist at moderate Reynolds numbers in a very long open channel flow. Direct numerical simulations two-way coupled with inertial particles are analysed using spectral information to investigate the modulation of VLSMs. In the wall-normal direction, particle distributions (mean/preferential concentration) exhibit two distinct behaviours in the inner flow and outer flow, corresponding to two highly anisotropic turbulent structures, LSMs and VLSMs. This results in particle inertia’s non-monotonic effects on the VLSMs: low inertia (based on the inner scale) and high inertia (based on the outer scale) both strengthen the VLSMs, whereas moderate and very high inertia have little influence. Through conditional tests, low- and high-inertia particles enhance VLSMs following two distinct routes. Low-inertia particles promote VLSMs indirectly through the enhancement of the regeneration cycle (the self-sustaining mechanism of LSMs) in the inner region, whereas high-inertia particles enhance the VLSM directly through contribution to the Reynolds shear stress at similar temporal scales in the outer region. This understanding also provides more general insight into inner–outer interaction in high-Reynolds-number, wall-bounded flows.
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Cameron, Stuart, Vladimir Nikora, Mark Stewart, and Andrea Zampiron. "Large and very large scale motions in roughbed open-channel flow." E3S Web of Conferences 40 (2018): 05061. http://dx.doi.org/10.1051/e3sconf/20184005061.

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Long duration PIV measurements in rough-bed (glass beads) open-channel flow (OCF) reveal that the pre-multiplied spectra of the streamwise velocity has a bimodal distribution due to the presence of large and very large scale motions (LSMs and VLSMs, respectively). The existence of VLSMs in boundary layers, pipes and closed channels has been acknowledged for some time, but strong supporting evidence for their presence in OCF has been lacking. Length scales of the large and very large scale motions in OCF exhibit different scaling properties; whereas the streamwise length of the LSM scales with the flow depth, the VLSM streamwise length does not scale purely with flow depth and may additionally depend on other scales such as the channel width, roughness height, or viscous length. Supplementary data for flows over self-affine fractal rough beds support these findings and additionally indicate that the length of VLSMs may grow along the extensive distance from the channel entrance. The origin and nature of LSMs and VLSMs are still to be resolved, but differences in their scaling suggest that VLSMs in rough-bed open-channel flows form independently rather than as a spatial alignment of LSMs.
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Lee, Kyoung Bo, Seong Hoon Lim, Geun-Young Park, and Sun Im. "Effect of Brain Lesions on Voluntary Cough in Patients with Supratentorial Stroke: An Observational Study." Brain Sciences 10, no. 9 (September 10, 2020): 627. http://dx.doi.org/10.3390/brainsci10090627.

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Patients with stroke are known to manifest a decreased cough force, which is associated with an increased risk of aspiration. Specific brain lesions have been linked to impaired reflexive coughing. However, few studies have investigated whether specific stroke lesions are associated with impaired voluntary cough. Here, we studied the effects of stroke lesions on voluntary cough using voxel-based lesion-symptom mapping (VLSM). In this retrospective cross-sectional study, the peak cough flow was measured in patients who complained of weak cough (n = 39) after supratentorial lesions. Brain lesions were visualized via magnetic resonance imaging (MRI) at the onset of stroke. These lesions were studied using VLSM. The VLSM method with non-parametric mapping revealed that lesions in the sub-gyral frontal lobe and superior longitudinal and posterior corona radiata were associated with a weak cough flow. In addition, lesions in the inferior parietal and temporal lobes and both the superior and mid-temporal gyrus were associated with a weak peak cough flow during voluntary coughing. This study identified several brain lesions underlying impaired voluntary cough. The results might be useful in predicting those at risk of poor cough function and may improve the prognosis of patients at increased risk of respiratory complications after a stroke.
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Ruggieri, Serena, Fulvia Fanelli, Letizia Castelli, Nikolaos Petsas, Laura De Giglio, and Luca Prosperini. "Lesion symptom map of cognitive–postural interference in multiple sclerosis." Multiple Sclerosis Journal 24, no. 5 (March 24, 2017): 653–62. http://dx.doi.org/10.1177/1352458517701313.

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Objective: To investigate the disease-altered structure–function relationship underlying the cognitive–postural interference (CPI) phenomenon in multiple sclerosis (MS). Methods: We measured postural sway of 96 patients and 48 sex-/age-matched healthy controls by force platform in quiet standing (single-task (ST)) while performing the Stroop test (dual-task (DT)) to estimate the dual-task cost (DTC) of balance. In patient group, binary T2 and T1 lesion masks and their corresponding lesion volumes were obtained from magnetic resonance imaging (MRI) of brain. Normalized brain volume (NBV) was also estimated by SIENAX. Correlations between DTC and lesion location were determined by voxel-based lesion symptom mapping (VLSM) analyses. Results: Patients had greater DTC than controls ( p < 0.001). Among whole brain MRI metrics, only T1 lesion volume correlated with DTC ( r = −0.27; p < 0.01). However, VLSM analysis did not reveal any association with DTC using T1 lesion masks. By contrast, we found clusters of T2 lesions in distinct anatomical regions (anterior and superior corona radiata, bilaterally) to be correlated with DTC ( p < 0.01 false discovery rate (FDR)-corrected). A multivariable stepwise regression model confirmed findings from VLSM analysis. NBV did not contribute to fit the model. Conclusion: Our findings suggest that the CPI phenomenon in MS can be explained by disconnection along specific areas implicated in task-switching abilities and divided attention.
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BAILEY, SEAN C. C., and ALEXANDER J. SMITS. "Experimental investigation of the structure of large- and very-large-scale motions in turbulent pipe flow." Journal of Fluid Mechanics 651 (March 24, 2010): 339–56. http://dx.doi.org/10.1017/s0022112009993983.

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Multi-point velocity measurements have been performed in turbulent pipe flow at ReD = 1.5 × 105 and combined with cross-spectral and proper orthogonal decomposition analysis to elucidate information on the structure of the large- and very-large-scale motions in the outer layer of wall-bounded flows. The results indicate that in the outer layer the large-scale motions (LSM) may be composed of detached eddies with a wide range of azimuthal scales, whereas in the logarithmic layer they are attached. The very-large-scale motions (VLSM) have large radial scales, are concentrated around a single azimuthal mode and make a smaller angle with the wall compared to the LSM. The results support a hypothesis that only the detached LSM in the outer layer align to form the VLSM.
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Lee, Jin, Jae Hwa Lee, Jung-Il Choi, and Hyung Jin Sung. "Spatial organization of large- and very-large-scale motions in a turbulent channel flow." Journal of Fluid Mechanics 749 (May 23, 2014): 818–40. http://dx.doi.org/10.1017/jfm.2014.249.

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AbstractDirect numerical simulations were carried out to investigate the spatial features of large- and very-large-scale motions (LSMs and VLSMs) in a turbulent channel flow ($\def \xmlpi #1{}\def \mathsfbi #1{\boldsymbol {\mathsf {#1}}}\let \le =\leqslant \let \leq =\leqslant \let \ge =\geqslant \let \geq =\geqslant \def \Pr {\mathit {Pr}}\def \Fr {\mathit {Fr}}\def \Rey {\mathit {Re}}\mathit{Re}_{\tau }=930$). A streak detection method based on the streamwise velocity fluctuations was used to individually trace the cores of LSMs and VLSMs. We found that both the LSM and VLSM populations were large. Several of the wall-attached LSMs stretched toward the outer regions of the channel. The VLSMs consisted of inclined outer LSMs and near-wall streaks. The number of outer LSMs increased linearly with the streamwise length of the VLSMs. The temporal features of the low-speed streaks in the outer region revealed that growing and merging events dominated the large-scale (1–$3\delta $) structures. The VLSMs $({>}3\delta )$ were primarily created by merging events, and the statistical analysis of these events supported that the merging of large-scale upstream structures contributed to the formation of VLSMs. Because the local convection velocity is proportional to the streamwise velocity fluctuations, the streamwise-aligned structures of the positive- and negative-$u$ patches suggested a primary mechanism underlying the merging events. The alignment of the positive- and negative-$u$ structures may be an essential prerequisite for the formation of VLSMs.
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Lee, Kyoung Bo, Sang Won Yoo, Eun Kyu Ji, Woo Seop Hwang, Yeun Jie Yoo, Mi-Jeong Yoon, Bo Young Hong, and Seong Hoon Lim. "Is Lateropulsion Really Related with a Specific Lesion of the Brain?" Brain Sciences 11, no. 3 (March 10, 2021): 354. http://dx.doi.org/10.3390/brainsci11030354.

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Lateropulsion (pusher syndrome) is an important barrier to standing and gait after stroke. Although several studies have attempted to elucidate the relationship between brain lesions and lateropulsion, the effects of specific brain lesions on the development of lateropulsion remain unclear. Thus, the present study investigated the effects of stroke lesion location and size on lateropulsion in right hemisphere stroke patients. The present retrospective cross-sectional observational study assessed 50 right hemisphere stroke patients. Lateropulsion was diagnosed and evaluated using the Scale for Contraversive Pushing (SCP). Voxel-based lesion symptom mapping (VLSM) analysis with 3T-MRI was used to identify the culprit lesion for SCP. We also performed VLSM controlling for lesion volume as a nuisance covariate, in a multivariate model that also controlled for other factors contributing to pusher behavior. VLSM, combined with statistical non-parametric mapping (SnPM), identified the specific region with SCP. Lesion size was associated with lateropulsion. The precentral gyrus, postcentral gyrus, inferior frontal gyrus, insula and subgyral parietal lobe of the right hemisphere seemed to be associated with the lateropulsion; however, after adjusting for lesion volume as a nuisance covariate, no lesion areas were associated with the SCP scores. The size of the right hemisphere lesion was the only factor most strongly associated with lateropulsion in patients with stroke. These results may be useful for planning rehabilitation strategies of restoring vertical posture and understanding the pathophysiology of lateropulsion in stroke patients.
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Dissertations / Theses on the topic "VLSM"

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COMI, ALESSANDRO. "Memoria verbale nei pazienti con glioma cerebrale." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2015. http://hdl.handle.net/10281/64636.

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Si sono studiati i correlati neurali dei sistemi di memoria verbale in pazienti con glioma cerebrale. Si tratta di pazienti sottoposti ad asportazione di lesioni cerebrali dell’emisfero dominante, in cui le funzioni mnestiche sono state valutate mediante prove specifiche prima e dopo l’intervento chirurgico, per verificare l’impatto funzionale dell’espanso e della rimozione della lesione. L’indagine anatomo-funzionale si è inoltre avvalsa delle tecniche di mappaggio cerebrale in awake surgery laddove l’intervento è stato eseguito in anestesia asleep-awake per la rimozione dei tumori estesi alle aree del linguaggio. Nel primo studio si esamina l’impatto della crescita tumorale sulla memoria verbale: le valutazioni neuropsicologiche effettuate pre-trattamento hanno permesso di identificare difficoltà conclamate o lievi compromissioni, che variano in funzione delle aree di infiltrazione tumorale; la prospettiva anatomo-clinica ha fornito una conferma dell’esistenza di sistemi di memoria verbale in distretti anatomo-funzionali differenti. Il secondo studio esamina i correlati neurali della memoria verbale a breve termine in un gruppo di pazienti sottoposti a mappaggio cerebrale in awake surgery: la stimolazione corticale e sottocorticale diretta ha permesso di identificare un circuito fronto-parietale coinvolto nei processi di MBT; l’analisi degli errori registrati durante i test intraoperatori ha permesso inoltre di distinguere il substrato neurale delle due componenti del circuito fonologico. Il terzo studio valuta gli effetti della lobectomia temporale sulla memoria a lungo termine; le prove mnestiche somministrate ad una settimana dall’intervento e dopo tre mesi hanno evidenziato prestazioni patologiche che non vanno incontro ad un rapido recupero nei pazienti che hanno subito la rimozione di un circuito cortico-sottocorticale esteso dalle regioni temporo-polari a quelle temporali mesiali; lo studio anatomico mediante voxel-based lesion-symptom mapping delle aree asportate ha permesso di verificare i correlati neurali di memoria semantica e apprendimento verbale. Questi risultati confermano che i pazienti con tumore cerebrali possono fornire dati interessanti nello studio dei deficit neuropsicologici.
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Tjan-Heijnen, Vivianne C. G. "De vlam." Maastricht : Maastricht : Maastricht University ; University Library, Universiteit Maastricht [host], 2007. http://arno.unimaas.nl/show.cgi?fid=13128.

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Chaudhray, Kamal. "VLSI routing." Thesis, University of Cambridge, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359367.

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Pope, Michael T. "VLSI systems simulation /." Title page, table of contents and abstract only, 1991. http://web4.library.adelaide.edu.au/theses/09PH/09php826.pdf.

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Alvelda, Phillip. "VLSI microdisplay technology." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/12019.

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Mhar, Javeed I. "VLSI design methodology." Thesis, University of Edinburgh, 1990. http://hdl.handle.net/1842/11855.

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The development of FIRST was a significant step in the field of silicon compilation. With FIRST, bit-serial signal processing systems could be rapidly implemented in silicon by high-level designers without requiring layout expertise. This thesis explores extensions to the compiler, but the methodology and techniques are not specific to FIRST and could be used in the more general VLSI arena. One major theme is the use of process independent layout, allowing the rapid update of a cell library to current state of the art process rules. After surveying other layout strategies, one particular layout style, gate matrix, was evaluated through the manual layout of a bit-serial, two's complement, multiplier utilising novel architectural features. The operation and architectural features of the multiplier are described, as these features were to be incorporated as options in newly generated cell libraries. SECOND, a full span silicon compiler; taking the high-level input description of FIRST but synthesizing layout to a process independent form (gate matrix) was developed using ideas gained from the manual assembly procedure. SECOND maintains and extends the hierarchy of FIRST using different assembly strategies for differing levels of hierarchy in the synthesis procedure. The hierarchy is described and the placement, routing and assembly procedures of the new elements of the hierarchy are covered. The automation tools used to generate the gate matrix layout of the lowest hierarchy level of SECOND are covered in a separate chapter. Using the same concepts of hierarchy, a tool ENGEN which transforms FIRST intermediate code to a gate level network description in HILO is also described as an alternative to SECOND in the search for process independence. The thesis ends with a suggestion of a bit-serial/bit-parallel frame for encouraging the acceptability of bit-serial systems.
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Nedelchev, Ivailo Marinov. "Asynchronous VLSI design." Thesis, University of Surrey, 1995. http://epubs.surrey.ac.uk/844150/.

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This thesis describes the background and implementation of a novel silicon compiler from a high-level programming language, OCCAM(async), to asynchronous CMOS circuits. The compilation scheme is based on a process algebra description of a concurrent system. This Algebra is called Delay-Insensitive Algebra and is based on CSP but allows the user more freedom in communication protocols. The thesis reviews and compares various, existing, design styles and their practical aspects for asynchronous design are also discussed. The syntax and the operational semantics of OCCAM(async) are defined and, on this basis, the new compilation technique is described with its underlying CMOS circuitry. The implementations of various, novel, library cells are also discussed. The compilation technique is illustrated throughout the thesis with practical examples. It is also compared to an existing synthesis tool, Tangram, which has been developed at Phillips Research Laboratories. The thesis concludes with the place and the role of OCCAM(async) in the contemporary CMOS design, and the future aspects in continuing this research into the full, design-process automation.
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Kao, De-Yu. "VLSI interconnect synthesis /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 1998. http://wwwlib.umi.com/cr/ucsd/fullcit?p9824659.

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Henkelmann, Heiko. "Automatisierter Systementwurf in der digitalen Signalverarbeitung auf der Basis von Schaltungsstrukturen der Restklassenarithmetik." [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=975327941.

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Schimpfle, Christian Vinzenz. "Entwurfsmethoden für verlustarme integrierte Schaltungen." [S.l. : s.n.], 2000. http://deposit.ddb.de/cgi-bin/dokserv?idn=959795537.

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Books on the topic "VLSM"

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IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration (1987 Vancouver, Canada). VLSI 87: VLSI design of digital systems. Amsterdam: North-Holland, 1988.

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Tarui, Yasuo, ed. VLSI Technology. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/978-3-642-69192-8.

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Feinberg, V., A. Levin, and E. Rabinovich. VLSI Planarization. Dordrecht: Springer Netherlands, 1997. http://dx.doi.org/10.1007/978-94-011-5740-7.

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Dhiman, Rohit, and Rajeevan Chandel, eds. Nanoscale VLSI. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7937-0.

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Chandrasetty, Vikram Arkalgud. VLSI Design. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-1120-8.

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G, Einspruch Norman, Cohen Simon S, and Gildenblat Gennady Sh, eds. VLSI metallization. Orlando: Academic Press, 1987.

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1936-, Sze S. M., ed. VLSI technology. 2nd ed. New York: McGraw-Hill, 1988.

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Chen, Wai-Kai. VLSI technology. Boca Raton: CRC Press, 2003.

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VLSI design. Boca Raton, FL: CRC Press, 2001.

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VLSI reliability. San Diego: Academic Press, 1990.

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Book chapters on the topic "VLSM"

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Cheon, SeongKwon, DongXue Jin, and ChongGun Kim. "A VLSM Address Management Method for Variable IP Subnetting." In Computational Science and Its Applications - ICCSA 2006, 73–83. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11751595_9.

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Frumkin, M. A. "VLSI Models." In Systolic Computations, 1–27. Dordrecht: Springer Netherlands, 1992. http://dx.doi.org/10.1007/978-94-011-2514-7_1.

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Warnes, L. A. A. "VLSI Technology." In Electronic Materials, 118–54. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4615-6893-3_5.

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Kourtev, Ivan S., and Eby G. Friedman. "VLSI Systems." In Timing Optimization Through Clock Skew Scheduling, 7–18. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4411-1_2.

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Klar, Heinrich. "VLSI-Entwurfsstile." In Integrierte Digitale Schaltungen MOS / BICMOS, 275–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/978-3-662-07937-9_9.

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Jensen, Kurt. "VLSI Chip." In Coloured Petri Nets, 149–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/978-3-642-60794-3_10.

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Warnes, L. A. A. "VLSI Technology." In Electronic Materials, 118–54. London: Macmillan Education UK, 1990. http://dx.doi.org/10.1007/978-1-349-21045-9_5.

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Klar, Heinrich, and Tobias Noll. "VLSI-Entwurfsmethoden." In Integrierte Digitale Schaltungen, 669–89. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-540-69017-7_8.

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Klar, Heinrich. "VLSI-Entwurfsstile." In Integrierte Digitale Schaltungen MOS/BICMOS, 267–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/978-3-662-22037-5_9.

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Post, Hans-Ulrich. "VLSI-Entwurfsstile." In Entwurf und Technologie hochintegrierter Schaltungen, 131–47. Wiesbaden: Vieweg+Teubner Verlag, 1989. http://dx.doi.org/10.1007/978-3-322-84815-4_7.

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Conference papers on the topic "VLSM"

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"Proceedings IEEE Workshop on Variational and Level Set Methods in Computer Vision." In Proceedings of 1st IEEE Workshop on Variational and Level Set Methods in Computer Vision. IEEE, 2001. http://dx.doi.org/10.1109/vlsm.2001.938874.

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"Author Index." In Proceedings of 1st IEEE Workshop on Variational and Level Set Methods in Computer Vision. IEEE, 2001. http://dx.doi.org/10.1109/vlsm.2001.938901.

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Werner, Rene, Matthias Wilmsy, Bastian Cheng, and Nils D. Forkert. "Beyond cost function masking: RPCA-based non-linear registration in the context of VLSM." In 2016 International Workshop on Pattern Recognition in Neuroimaging (PRNI). IEEE, 2016. http://dx.doi.org/10.1109/prni.2016.7552344.

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4

Narendra, Pat. "VLSI Architectures for Real-Time Image Processing." In Machine Vision. Washington, D.C.: Optica Publishing Group, 1985. http://dx.doi.org/10.1364/mv.1985.fd4.

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Real-time image processing has come of age in numerous industrial and military applications. Now is the opportune moment to define architectures which can yield low cost generic VLSI building blocks spanning the various algorithm and system requirements. In this paper, we summarize typical sensor formats and algorithms to identify common data flow and computational structures required for their real-time VLSI implementation. A set of criteria for evaluating architectures for VLSI is developed and used to examine several representative architectures. Recommendations for common VLSI building blocks are made for the representative architectures.
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5

Chae, Soo-Ik, James T. Walker, Chong-Cheng Fu, David H. Dameron, and R. Fabian Pease. "Template-Set Approach to Defect Detection and Classification for VLSI Patterns." In Machine Vision. Washington, D.C.: Optica Publishing Group, 1987. http://dx.doi.org/10.1364/mv.1987.thc5.

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Automatic inspection of VLSI circuit patterns on photomasks and wafers is increasingly important as the minimum feature size decreases. Real-time inspection at the standard video rate is demanding because the volume of information in VLSI circuits patterns is enormously large. Similar to printed wiring board inspection[1], the goal of VLSI pattern inspection is not only to detect defects, but also to automatically interpret defects for patterning process analysis and control, which is essential to manufacturing automation. However, die-to-die or die-to-database comparison methods employed in most state-of-the-art VLSI pattern inspection systems have only defect detection capability. Simultaneous detection and classification of defects in real time has been challenging because of the complexity of computation required in statistical and syntactic classification methods[2]. We have developed a new approach based on template matching of local binary images with content-addressable memories (CAMs), which can easily be implemented in VLSI circuits because of its modularity and regularity. In a work reported previously[3], this approach was applied primarily to defect detection. Here we focus on its application to defect classification and its system implementation in VLSI circuits.
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Wagner, Kelvin, and Tim Slagle. "Competitive Optical Learning with Winner-Take-All Modulators." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1991. http://dx.doi.org/10.1364/optcomp.1991.wa5.

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Modern neural network learning models such as competitive learning networks[2,4], resonance correlation networks, and back propagation networks[1] require a wider range of neuron behavior than a simple saturating threshold non-linearity. However, optical implementation of neurons that incorporate non-local, non-linear functions such as shunting inhibition, winner-take-all, and history-dependent behavior is beyond the capability of conventional optical devices. A new class of light modulator has been developed that combines the flexibility of analog and digital electronic VLSI circuits, optical detectors, and the switchable electo-optic capabilities of liquid crystal materials. In this paper we will show how these liquid crystal/VLSI modulators can be used in optical implementations of these learning networks. We discuss in detail a competitive optical learning network which uses LC/VLSI winner-take-all neurons on fractal grids to program adaptive volume holographic interconnections. We will present results from tests of the LC/VLSI winner-take-all modulator arrays, and in addition will show preliminary results from an optical competitive learning system that uses the LC/VLSI modulators as neurons.
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7

Gaber, Lamya, Aziza I. Hussein, and Mohammed Moness. "Incremental Automatic Correction for Digital VLSI Circuits." In 10th International Conference on Advances in Computing and Information Technology (ACITY 2020). AIRCC Publishing Corporation, 2020. http://dx.doi.org/10.5121/csit.2020.101508.

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The impact of the recent exponential increase in complexity of digital VLSI circuits has heavily affected verification methodologies. Many advances toward verification and debugging techniques of digital VLSI circuits have relied on Computer Aided Design (CAD). Existing techniques are highly dependent on specialized test patterns with specific numbers increased by the rising complexity of VLSI circuits. A second problem arises in the form of large sizes of injecting circuits for correction and large number of SAT solver calls with a negative impact on the resultant running time. Three goals arise: first, diminishing dependence on a given test pattern by incrementally generating compact test patterns corresponding to design errors during the rectification process. Second, to reduce the size of in-circuit mutation circuit for error-fixing process. Finally, distribution of test patterns can be performed in parallel with a positive impact on digital VLSI circuits with large numbers of inputs and outputs. The experimental results illustrate that the proposed incremental correction algorithm can fix design bugs of type gate replacements in several digital VLSI circuits from ISCAS'85 with high speed and full accuracy. The speed of proposed Auto-correction mechanism outperforms the latest existing methods around 4.8x using ISCAS'85 benchmarks. The parallel distribution of test patterns on digital VLSI circuits during generating new compact test patterns achieves speed around 1.2x compared to latest methods.
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Livramento, Vinícius Dos Santos, and José Luís Güntzel. "Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits." In XXX Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação - SBC, 2017. http://dx.doi.org/10.5753/ctd.2017.3465.

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The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.
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Jared, David A., Timothy M. Slagle, Kristina M. Johnson, and Kelvin Wagner. "Optically addressed CMOS VLSI liquid-crystal spatial light modulators." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.fv2.

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A new class of optically addressed spatial light modulators (SLMs) based on complementary metal-oxide semiconductor (CMOS) very-large-scale integration (VLSI) CMOS VLSI and liquid-crystal technology is discussed. The SLMs consist of a liquid-crystal modulator on a CMOS VLSI backplane containing photodetectors and analog electronics. In this manner, by combining the flexibility of semiconductor electronics and the parallelism of liquid-crystal modulator, SLMs can be designed to perform a wider variety of computational functions. New optoelectronic computing architectures are possible by providing a tighter coupling between the electronic and the optical processing.
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Mao, C. C., K. M. Johnson, and Z. Y. Huang. "High-voltage electrical circuitry for fast-switching VLSI/FLC spatial light modulators." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.thb.3.

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Very-large-scale-integration-ferroelectric-liquid-crystal (VLSI/FLC) devices have many applications, including image display, optical correlation, and neural networks.1,2 With typical CMOS transistors, the VLSI circuitry can provide 0 V or 5 V to switch the liquid crystals.
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Reports on the topic "VLSM"

1

Hu, Chenming. VLSI Reliability Research. Fort Belvoir, VA: Defense Technical Information Center, August 1992. http://dx.doi.org/10.21236/ada254883.

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O'Leary, Gerald C. Restructurable VLSI Program. Fort Belvoir, VA: Defense Technical Information Center, March 1985. http://dx.doi.org/10.21236/ada160935.

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O'Leary, Gerald C. Restructurable VLSI Program. Fort Belvoir, VA: Defense Technical Information Center, September 1985. http://dx.doi.org/10.21236/ada165718.

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Pina, Cesar A. ARPA/CSTO Rapid VLSI Implementation. Fort Belvoir, VA: Defense Technical Information Center, July 1993. http://dx.doi.org/10.21236/ada269170.

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Liem, Meei-Chiueh Y. Declarative Descriptions for VLSI Generators. Fort Belvoir, VA: Defense Technical Information Center, June 1986. http://dx.doi.org/10.21236/ada169952.

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Roberts, Richard A. VLSI Implementations for Digital Signal Processing. Fort Belvoir, VA: Defense Technical Information Center, December 1987. http://dx.doi.org/10.21236/ada189612.

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Ringhofer, Christian. Mathematical Models for VLSI Device Simulation. Fort Belvoir, VA: Defense Technical Information Center, November 1987. http://dx.doi.org/10.21236/ada191125.

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Alspector, Joshua. VLSI Implementation of Neuromorphic Learning Networks. Fort Belvoir, VA: Defense Technical Information Center, March 1993. http://dx.doi.org/10.21236/ada270825.

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Dally, William J., and Steve Lacy. VLSI Architecture: Past, Present, and Future. Fort Belvoir, VA: Defense Technical Information Center, January 1998. http://dx.doi.org/10.21236/ada419586.

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Kurdahi, F. J., and A. C. Parker. Area Estimation of VLSI Integrated Circuits. Fort Belvoir, VA: Defense Technical Information Center, July 1985. http://dx.doi.org/10.21236/ada160335.

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