Journal articles: 'Virtex-7'

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Kalyaev, I. A., I. I. Levin, A. I. Dordopulo, and L. M. Slasten. "Reconfigurable Computer Systems Based on Virtex-6 and Virtex-7 FPGAs." IFAC Proceedings Volumes 46, no. 28 (2013): 210–14. http://dx.doi.org/10.3182/20130925-3-cz-3023.00009.

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ILES, G., J. Jones, and A. Rose. "Experience powering Xilinx Virtex-7 FPGAs." Journal of Instrumentation 8, no. 12 (December 20, 2013): C12037. http://dx.doi.org/10.1088/1748-0221/8/12/c12037.

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Rashid, Muhammad, Mohammad Mazyad Hazzazi, Sikandar Zulqarnain Khan, Adel R. Alharbi, Asher Sajid, and Amer Aljaedi. "A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography." Electronics 10, no. 21 (November 4, 2021): 2698. http://dx.doi.org/10.3390/electronics10212698.

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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

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Иванов, А., and Д. Никишин. "ВХОДНОЙ КОНТРОЛЬ МИКРОСХЕМ XILINX VIRTEX-7 С ПОМОЩЬЮ ПЕРИФЕРИЙНОГО СКАНИРОВАНИЯ." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 210, no. 9 (November 3, 2021): 94–98. http://dx.doi.org/10.22184/1992-4178.2021.210.9.94.98.

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Рассмотрено использование периферийного сканирования для реализации входного контроля микросхем Xilinx Virtex-7. Отмечено, что представленные решения могут быть использованы на предприятиях радиоэлектронной промышленности для проведения процедуры входного контроля.

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Pandey, Bishwajeet, Geetam S. Tomar, Rajina R. Mohamed, D. M. Akbar Hussain, and Amit Kant Pandit. "Energy Efficient Design on 16 nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate." Journal of Computational and Theoretical Nanoscience 17, no. 11 (November 1, 2020): 5122–24. http://dx.doi.org/10.1166/jctn.2020.9351.

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Scientists in 2010 were using a 40 nanometer Process based FPGA called Virtex-6 and 45 nm Process Technology based FPGA called Spartan-6. After 2010, researchers shifted their focus towards 28 nm technology based 7 series FPGA (Artix-7, Kintex-7, and Virtex-7) due to their intrinsic capability of low power consumption than both 40 nm and 45 nm technology based FPGA. In December, 2013, Xilinx introduced the 20 nm process technology based UltraScale series: Virtex UltraScale and Kintex UltraScale families. But now in 2020, researchers are using 16 nm technology based UltraScale+ FPGA. In our work, we are also using 16 nm technology based UltraScale+ FPGA for implementing our memory using VIVADO 2018.3 hardware programming tool and Verilog Hardware Description Language. There is 49.42%, 25.28% saving in design power on UltraScale+ FPGA when we minimize static probabilities to 0.1 and 0.2 respectively.

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Sajid, Asher, Muhammad Rashid, Malik Imran, and Atif Raza Jafri. "A Low-Complexity Edward-Curve Point Multiplication Architecture." Electronics 10, no. 9 (May 3, 2021): 1080. http://dx.doi.org/10.3390/electronics10091080.

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The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over GF(2233). There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32-bit finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over GF(2233) on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 µs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time.

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Chen, Baoju, Simin Yu, Ping Chen, Liangshan Xiao, and Jinhu Lü. "Design and Virtex-7-Based Implementation of Video Chaotic Secure Communications." International Journal of Bifurcation and Chaos 30, no. 05 (April 2020): 2050075. http://dx.doi.org/10.1142/s0218127420500753.

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In this paper, a Virtex-7-based video chaotic secure communication scheme is investigated. First, the network sending and receiving controller Intellectual Property (IP) cores are designed. Next, the chaotic encryption and decryption IP cores are implemented using fixed-point algorithm, pipeline operation, and state machine control. Thus, video capturing, video displaying, network sending, network receiving, chaotic encrypting, and chaotic decrypting can be achieved via IP core integration design. An improved 7D chaotic stream cipher algorithm for resisting divide-and-conquer attack is then designed and realized on a Virtex-7 high-end FPGA platform. Hardware experimental results are also given to verify the feasibility of the scheme.

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Rumyantsev, Yu A. "Direct data transfer between FPGAs Virtex-7 via PCI Express bus." Proceedings of the Institute for System Programming of RAS 24 (2013): 107–26. http://dx.doi.org/10.15514/ispras-2013-24-6.

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Sajid, Asher, Muhammad Rashid, Sajjad Shaukat Jamal, Malik Imran, Saud S. Alotaibi, and Mohammed H. Sinky. "AREEBA: An Area Efficient Binary Huff-Curve ARchitecture." Electronics 10, no. 12 (June 20, 2021): 1490. http://dx.doi.org/10.3390/electronics10121490.

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Elliptic curve cryptography is the most widely employed class of asymmetric cryptography algorithm. However, it is exposed to simple power analysis attacks due to the lack of unifiedness over point doubling and addition operations. The unified crypto systems such as Binary Edward, Hessian and Huff curves provide resistance against power analysis attacks. Furthermore, Huff curves are more secure than Edward and Hessian curves but require more computational resources. Therefore, this article has provided a low area hardware architecture for point multiplication computation of Binary Huff curves over GF(2163) and GF(2233). To achieve this, a segmented least significant digit multiplier for polynomial multiplications is proposed. In order to provide a realistic and reasonable comparison with state of the art solutions, the proposed architecture is modeled in Verilog and synthesized for different field programmable gate arrays. For Virtex-4, Virtex-5, Virtex-6, and Virtex-7 devices, the utilized hardware resources in terms of hardware slices over GF(2163) are 5302, 2412, 2982 and 3508, respectively. The corresponding achieved values over GF(2233) are 11,557, 10,065, 4370 and 4261, respectively. The reported low area values provide the acceptability of this work in area-constrained applications.

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Ye, Wen Hua, and Huan Li. "Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board." Applied Mechanics and Materials 719-720 (January 2015): 534–37. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.534.

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With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.

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Pandey, Sujeet, Bhagwan Das, and D. M. A. Hussain. "Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family." Gyancity Journal of Engineering and Technology 4, no. 1 (January 30, 2018): 31–38. http://dx.doi.org/10.21058/gjet.2018.41004.

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Rashid, Muhammad, Harish Kumar, Sikandar Zulqarnain Khan, Ismail Bahkali, Ahmed Alhomoud, and Zahid Mehmood. "Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol." Applied Sciences 12, no. 8 (April 18, 2022): 4091. http://dx.doi.org/10.3390/app12084091.

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This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

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Bansal, Manish, and Sangeeta Nakhate. "Implementation of fast FFT design for 128-point using Radix-22 CFA." International Journal of Engineering & Technology 7, no. 4 (September 24, 2018): 2646. http://dx.doi.org/10.14419/ijet.v7i4.16063.

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In this paper, implementation of fast FFT design for 128- point using Radix-22 CFA is presented. This research uses a common factor algorithm which is based on Radix-22. A 2-point DFT butterfly structure is the lowest complexity structure and Radix-22 CFA is used to reduce logic and area by reducing the number of twiddle factors. The VHDL code is written and synthesized using Xilinx FPGA device xc7vx330t-3ffg1761 to implement the proposed design. This design is coded in VHDL and MATLAB. VHDL code is targeted to synthesize into Xilinx Virtex-7 FPGA and simulated into ModelSim PE Student Edition 10.4a. MATLAB code is simulated into MATLAB 2012. The proposed design achieves 149.822 MHz clock frequency, used 2802 slices on the Virtex-7 and SQNR 33.49 dB at 16-bit I/O word length.

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Shashidhara, K. S., and H. C. Srinivasaiah. "Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs." European Journal of Engineering Research and Science 4, no. 9 (September 16, 2019): 81–88. http://dx.doi.org/10.24018/ejers.2019.4.9.1515.

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This Paper presents implementation of 1024-point Fast Fourier Transform (FFT). The MatLab simulink environment approach is used to implement the complex 1024-point FFT. The FFT is implemented on different FPGAs such as the following four: Artix-7, Kintex-7, Virtex-7, and Zynq-7000. The comparative study on power and resource consumption has been carried out as design parameters of prime concern. The results show that Artix-7 FPGA consumes less power of 3.402W when compared with its contemporary devices, mentioned above. The resource consumption remains same across all the devices. The resource estimation on each FPGA is carried on and its results are presented for 1024-point FFT function implementation. This Comprehensive analysis provides a deep insight with respect to power and resources. The synthesis and implementation results such as RTL Schematic, I/O Planning, and Floor Planning are generated and analyzed for all the above devices.

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Shashidhara, K. S., and H. C. Srinivasaiah. "Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs." European Journal of Engineering and Technology Research 4, no. 9 (September 16, 2019): 81–88. http://dx.doi.org/10.24018/ejeng.2019.4.9.1515.

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This Paper presents implementation of 1024-point Fast Fourier Transform (FFT). The MatLab simulink environment approach is used to implement the complex 1024-point FFT. The FFT is implemented on different FPGAs such as the following four: Artix-7, Kintex-7, Virtex-7, and Zynq-7000. The comparative study on power and resource consumption has been carried out as design parameters of prime concern. The results show that Artix-7 FPGA consumes less power of 3.402W when compared with its contemporary devices, mentioned above. The resource consumption remains same across all the devices. The resource estimation on each FPGA is carried on and its results are presented for 1024-point FFT function implementation. This Comprehensive analysis provides a deep insight with respect to power and resources. The synthesis and implementation results such as RTL Schematic, I/O Planning, and Floor Planning are generated and analyzed for all the above devices.

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Huemoeller, Ron. "TSV Market Drivers, Demand & Product Readiness." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (January 1, 2012): 000334–46. http://dx.doi.org/10.4071/2012dpc-ta11.

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The market has narrowed its approach and solidified its direction for the majority of 2.5 and 3D TSV product technologies. Forecasts have now become real for these technologies and the end game realized as evidenced by production launch of the Xilinx Virtex-7. This talk will discuss market trends, anticipated product launch dates as well as general capacity needs as the market begins to rollout these new products.

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Kalia, Kartik, Khyati Nanda, Arushi Aggarwal, Akshita Goel, and Shivani Malhotra. "Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA." Advanced Materials Research 1098 (April 2015): 37–43. http://dx.doi.org/10.4028/www.scientific.net/amr.1098.37.

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In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

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Sghaier, Anissa, Medien Zeghid, Chiraz Massoud, Hassan Yousif Ahmed, Abdellah Chehri, and Mohsen Machhout. "Fast Constant-Time Modular Inversion over Fp Resistant to Simple Power Analysis Attacks for IoT Applications." Sensors 22, no. 7 (March 25, 2022): 2535. http://dx.doi.org/10.3390/s22072535.

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The advent of the Internet of Things (IoT) has enabled millions of potential new uses for consumers and businesses. However, with these new uses emerge some of the more pronounced risks in the connected object domain. Finite fields play a crucial role in many public-key cryptographic algorithms (PKCs), which are used extensively for the security and privacy of IoT devices, consumer electronic equipment, and software systems. Given that inversion is the most sensitive and costly finite field arithmetic operation in PKCs, this paper proposes a new, fast, constant-time inverter over prime fields Fp based on the traditional Binary Extended Euclidean (BEE) algorithm. A modified BEE algorithm (MBEEA) resistant to simple power analysis attacks (SPA) is presented, and the design performance area-delay over Fp is explored. Furthermore, the BEE algorithm, modular addition, and subtraction are revisited to optimize and balance the MBEEA signal flow and resource utilization efficiency. The proposed MBEEA architecture was implemented and tested on Xilinx FPGA Virtex #5, #6, and #7 devices. Our implementation over Fp (length of p = 256 bits) with 2035 slices achieved one modular inversion in only 1.12 μs on Virtex-7. Finally, we conducted a thorough comparison and performance analysis to demonstrate that the proposed design outperforms the competing designs, i.e., has a lower area-delay product (ADP) than the reported inverters.

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Bibilo, P. N., Yu Yu Lankevich, and V. I. Romanov. "Logical minimization for combinatorial structure in FPGA." Informatics 18, no. 1 (March 29, 2021): 7–24. http://dx.doi.org/10.37661/1816-0301-2021-18-1-7-24.

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The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.

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Sakshi and Ravi Kumar. "A Novel Design and FPGA Implementation of Filters Adapted Using LMS Variants." Journal of Circuits, Systems and Computers 27, no. 08 (April 12, 2018): 1850125. http://dx.doi.org/10.1142/s0218126618501256.

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Adaptive filters have wide range of applications in areas such as echo or interference cancellation, prediction and system identification. Due to high computational complexity of adaptive filters, their hardware implementation is not an easy task. However, it becomes essential in many cases where real-time execution is needed. This paper presents the design and hardware implementation of a variable step size 40 order adaptive filter for de-noising acoustic signals. To ensure an area efficient implementation, a novel structure is being proposed. The proposed structure eliminates the requirement of extra registers for storage of delayed inputs thereby reducing the silicon area. The structure is compared with direct-form and transposed-form structures by adapting the filter coefficients using four different variants of the least means square (LMS) algorithm. Subsequently, the filters are implemented on three different field programmable gate arrays (FPGAs) viz. Spartan 6, Virtex 6 and Virtex 7 to find out the best device family that can be used to implement an Adaptive noise canceller (ANC) by comparing speed, power and area utilization. The synthesis results clearly reveal that ANC designed using the proposed structure has resulted in a reduction in silicon area without incurring any significant overhead in terms of power or delay.

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Tsaplin, S. V., and S. A. Bolychev. "Estimation and analysis of the influence of ionizing radiation on the operation of nanosatellite onboard radio electronic equipment." VESTNIK of Samara University. Aerospace and Mechanical Engineering 20, no. 3 (December 1, 2021): 77–96. http://dx.doi.org/10.18287/2541-7533-2021-20-3-77-96.

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The paper presents the results of a calculation aimed to study the influence of ionizing, bremsstrahlung radiation on the operation of a nanosatellite obtained during the implementation of the project 0777-2020-0018 in 2020. A comparative analysis of the results of calculating the specific ionization and radiation energy losses of protons (from 0.1 to 400 MeV) and electrons (from 0.04 to 7 MeV), as well as their path lengths in aluminum according to the formulas of various authors and the database of materials of the National Institute of Standards and Technologies is presented. Based on the analysis results, the annual dose in the aluminum structure of the SamSat ION nanosatellite in a circular sun-synchronous orbit (SSO) is calculated. All calculations are based on the data of the energy spectra of protons and electrons of the SSO given in the Information system Spenvis of the European Space Agency. The results of calculating the integral fluxes in aluminum under the action of protons and electrons of a circular SSO for different thicknesses are obtained, and the fraction of passed particles is shown in the approximation of a single-layer stack. The radiation resistance of the electronic elements ISL70321SEH, ISL73321SEH and Virtex-4QV, Virtex-5QV included in the SamSat ION avionics and its ability to operate during a year was assessed.

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Rani, Archana, and Naresh Grover. "An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM." Bulletin of Electrical Engineering and Informatics 7, no. 2 (June 1, 2018): 199–208. http://dx.doi.org/10.11591/eei.v7i2.818.

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This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route Placed design.

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Zhang, Jian, Yue Zhang, Zengping Chen, and Qianqiang Lin. "Research on design and key technology of wideband radar intermediate frequency direct acquisition module based on Virtex-7 series FPGA." Journal of Engineering 2019, no. 19 (October 1, 2019): 6331–35. http://dx.doi.org/10.1049/joe.2019.0233.

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Szplet, Ryszard, and Arkadiusz Czuba. "Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device." Electronics 10, no. 18 (September 7, 2021): 2190. http://dx.doi.org/10.3390/electronics10182190.

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This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).

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Pradhitha, C. Mani, and K. Kolangiammal. "Development and Implementation of Parallel to Serial data Transmitter Using Aurora Protocol for High Speed Serial Data Transmission on Virtex-7 FPGA." Indian Journal of Science and Technology 11, no. 23 (June 1, 2018): 1–8. http://dx.doi.org/10.17485/ijst/2018/v11i23/125648.

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Khalifa, Khaled Ben, and Mohamed Hédi Bedoui. "A Massively Parallel Implementation of a Modular Self-Organizing Map on FPGAs." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950054. http://dx.doi.org/10.1142/s0218126619500543.

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This paper describes the architecture design of novel massively parallel self-organizing map (SOM) neural networks. The proposed architecture, referred to as the planar SOM (PSOM), is described as a soft IP core synthesized in VHDL. The SOM neural network’s size and the input data vectors’ dimension are adjustable parameters. In this work, several SOM architectures are synthesized and their performance is evaluated for Xilinx Virtex-7 FPGAs. The presented hardware architecture allows online learning and can be easily adapted to a large variety of SOM topologies without a considerable design effort. A [Formula: see text] SOM hardware is validated through the FPGA implementation and its performances with an estimated working frequency of 297[Formula: see text]MHz for a 23-element input vector will reach 21,970 MCUPS in the learning phase and 35,902 MCPS in the recall one.

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Zha, Daolu, Xi Jin, Rui Shang, and Pengfei Yang. "A Real-Time Learning-Based Super-Resolution System on FPGA." Parallel Processing Letters 30, no. 04 (December 2020): 2050011. http://dx.doi.org/10.1142/s0129626420500115.

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This paper proposes a real-time super-resolution (SR) system. The proposed system performs a fast SR algorithm that generates a high-resolution image from a low-resolution image using direct regression functions with an up-scaling factor of 2. This algorithm contained two processes: feature learning and SR image prediction. The feature learning stage is performed offline, in which several regression functions were trained. The SR image prediction stage is implemented on the proposed system to generate high-resolution image patches. The system implemented on a Xilinx Virtex 7 field-programmable gate array achieves output resolution of [Formula: see text] (UHD) at 85 fps and 700Mpixels/s throughput. Structure similarity (SSIM) is measured for image quality. Experimental results show that the proposed system provides high image quality for real-time applications. And the proposed system possesses high scalability for resolution.

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Townsend, Kevin R., Osama G. Attia, Phillip H. Jones, and Joseph Zambreno. "A Scalable Unsegmented Multiport Memory for FPGA-Based Systems." International Journal of Reconfigurable Computing 2015 (2015): 1–12. http://dx.doi.org/10.1155/2015/826283.

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On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

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Ramezani, Hadise, Majid Mohammadi, and Amir Sabbagh Molahosseini. "An efficient look up table based approximate adder for field programmable gate array." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (January 1, 2022): 144. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp144-151.

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The approximate computing is an alternative computing approach which can lead to high-performance implementation of audio and image processing as well as deep learning applications. However, most of the available approximate adders have been designed using application specific integrated circuits (ASICs), and they would not result in an efficient implementation on field programmable gate arrays (FPGAs). In this paper, we have designed a new approximate adder customized for efficient implementation on FPGAs, and then it has been used to build the Gaussian filter. The experimental results of the implementation of Gaussian filter based on the proposed approximate adder on a Virtex-7 FPGA, indicated that the resource utilization has decreased by 20-51%, and the designed filter delay based on the modified design methodology for building approximate adders for FPGA-based systems (MDeMAS) adder has improved 10-35%, due to the obtained output quality.

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Nguyen, Tuy Tan, Sungjae Kim, Yongjun Eom, and Hanho Lee. "Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber." Applied Sciences 12, no. 11 (May 24, 2022): 5305. http://dx.doi.org/10.3390/app12115305.

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This paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards and Technology. By developing a dual-path delay feedback number theoretic transform multiplier dedicating for Kyber parameter set and deploying this multiplier in the Kyber architecture, the key generation, encryption, and decryption operations are accelerated substantially. Furthermore, the proposed architecture offers the best value of area-time product in comparison with existing approaches. The implementation results on Xilinx Vivado targeted for Virtex-7 FPGA board demonstrate that the proposed Kyber cryptoprocessor completes encryption and decryption operations in approximately 57.5 μs at the highest frequency of 226 MHz. Furthermore, the area-time product value when using the proposed Kyber architecture is improved by at least twofold compared with existing architectures.

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Awaludin, Asep Muhamad, Harashta Tatimma Larasati, and Howon Kim. "High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA." Sensors 21, no. 4 (February 19, 2021): 1451. http://dx.doi.org/10.3390/s21041451.

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In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

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Kryjak, Tomasz, Mateusz Komorkiewicz, and Marek Gorgon. "Real-time Foreground Object Detection Combining the PBAS Background Modelling Algorithm and Feedback from Scene Analysis Module." International Journal of Electronics and Telecommunications 60, no. 1 (March 1, 2014): 53–64. http://dx.doi.org/10.2478/eletel-2014-0006.

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Abstract The article presents a hardware implementation of the foreground object detection algorithm PBAS (Pixel-Based Adaptive Segmenter) with a scene analysis module. A mechanism for static object detection is proposed, which is based on consecutive frame differencing. The method allows to distinguish stopped foreground objects (e.g. a car at the intersection, abandoned luggage) from false detections (so-called ghosts) using edge similarity. The improved algorithm was compared with the original version on popular test sequences from the changedetection.net dataset. The obtained results indicate that the proposed approach allows to improve the performance of the method for sequences with the stopped objects. The algorithm has been implemented and successfully verified on a hardware platform with Virtex 7 FPGA device. The PBAS segmentation, consecutive frame differencing, Sobel edge detection and advanced one-pass connected component analysis modules were designed. The system is capable of processing 50 frames with a resolution of 720 × 576 pixels per second

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Nguyen Tan, Tuy, Tram Thi Bao Nguyen, and Hanho Lee. "High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components." Electronics 9, no. 7 (June 30, 2020): 1075. http://dx.doi.org/10.3390/electronics9071075.

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A high efficiency architecture for ring learning with errors (ring-LWE) cryptoprocessor using shared arithmetic components is presented in this paper. By applying a novel approach for sharing number theoretic transform (NTT) polynomial multiplier and polynomial adder in encryption and decryption operations, the total number of polynomial multipliers and polynomial adders used in the proposed ring-LWE cryptoprocessor are reduced. In addition, the processing time of NTT polynomial multiplier is speeded up by employing multiple-path delay feedback (MDF) architecture and deploying pipelined technique between all stages of NTT processes. As a result, the proposed architecture offers a great reduction in terms of the hardware complexity and computation latency compared with existing works. The implementation result for the proposed ring-LWE cryptoprocessor on Virtex-7 FPGA board using Xilinx VIVADO shows a significant decrease in the number of slices and LUTs compared with previous works. Moreover, the proposed ring-LWE cryptoprocessor offers higher throughput and efficiency than its predecessors.

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Luo, Hanguang, Guangjun Wen, and Jian Su. "An Efficient Hardware-Based Fault-Tolerant Method for SMS4." MATEC Web of Conferences 208 (2018): 02005. http://dx.doi.org/10.1051/matecconf/201820802005.

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The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.

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Deng, X., and Q. Chen. "A 4.32-ps precision Time-to-Digital Convertor using multisampling wave union method on a 28-nm FPGA." Journal of Instrumentation 16, no. 12 (December 1, 2021): P12031. http://dx.doi.org/10.1088/1748-0221/16/12/p12031.

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Abstract In this paper, a fully implemented field programmable gate array (FPGA) based time-to-digital converter (TDC) using multisampling wave union method (MSWU) is proposed to get higher measurement precision with lower resource utilization. Different from the previously published works based on wave union methods, an inverter-chain-based wave launcher is introduced to generate more low-jitter edges in the same operation range. Meanwhile, a new de-bubble solution combining with offline bin alignment and online bin sorting is applied to eliminate severe bubbles in FPGAs of advanced manufacturing technologies. The proposed TDCs are verified on a Virtex-7 (28 nm) of FPGA development board VC707. According to test results, the average measurement precision and mean resolution reach 4.32 ps and 0.82 ps, respectively with [-0.98;3.43] LSB DNL and [-6.06;34.1] LSB INL. A complete TDC channel only uses 831 D-type flip-flops (DFFs), 1305 look-up tables (LUTs) and 6 block random access memories (BRAMs) of 36k bits.

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Kieu-Do-Nguyen, Binh, Cuong Pham-Quoc, Ngoc-Thinh Tran, Cong-Kha Pham, and Trong-Thuc Hoang. "Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA." Cryptography 6, no. 2 (May 10, 2022): 25. http://dx.doi.org/10.3390/cryptography6020025.

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In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays an essential role in many security applications, such as transport layer security (TLS), internet protocol security (IPsec), and wireless sensor networks (WSNs). The proposed designs of ECC hardware implementation only focus on a single ECC variant and use many resources. These proposals cannot be used for resource-constrained applications or for the devices that need to provide multiple levels of security. This work provides a multi-functional elliptic curve digital signature algorithm (ECDSA) and Edwards-curve digital signature algorithm (EdDSA) hardware implementation. The core can run multiple ECDSA/EdDSA algorithms in a single design. The design consumes fewer resources than the other single-functional design, and is not based on digital signal processors (DSP). The experiments show that the proposed core could run up to 112.2 megahertz with Virtex-7 devices while consuming only 10,259 slices in total.

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Rashid, Muhammad, Sajjad Shaukat Jamal, Sikandar Zulqarnain Khan, Adel R. Alharbi, Amer Aljaedi, and Malik Imran. "Elliptic-Curve Crypto Processor for RFID Applications." Applied Sciences 11, no. 15 (July 31, 2021): 7079. http://dx.doi.org/10.3390/app11157079.

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This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

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Xiao, Feibao, Feng Liang, Bin Wu, Junzhe Liang, Shuting Cheng, and Guohe Zhang. "Posit Arithmetic Hardware Implementations with The Minimum Cost Divider and SquareRoot." Electronics 9, no. 10 (October 2, 2020): 1622. http://dx.doi.org/10.3390/electronics9101622.

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As a substitute for the IEEE 754-2008 floating-point standard, Posit, a new kind of number system for floating-point numbers, was put forward recently. Hitherto, some studies have proven that Posit is a better floating-point style than IEEE 754-2008 in some fields. However, most of these studies presented the advantages of Posit from the arithmetical aspect, but none of them suggested it had a better hardware implementation than that of IEEE 754-2008. In this paper, we propose several hardware implementations that contain the Posit adder/subtractor, multiplier, divider, and square root. Our goal is to achieve an arbitrary Posit format and exploit the minimum circuit area, which is required in embedded devices. To implement the minimum circuit area for the divider and square root, the alternating addition and subtraction method is used rather than the Newton–Raphson method. Compared with other works, the area of our divider is about 0.2×–0.7× (FPGA). Furthermore, this paper provides the synthesis results for each critical module with the Xilinx Virtex-7 FPGA VC709 platform.

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Rashid, Muhammad, Malik Imran, and Asher Sajid. "An Efficient Elliptic-Curve Point Multiplication Architecture for High-Speed Cryptographic Applications." Electronics 9, no. 12 (December 12, 2020): 2126. http://dx.doi.org/10.3390/electronics9122126.

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This work presents an efficient high-speed hardware architecture for point multiplication (PM) computation of Elliptic-curve cryptography using binary fields over GF(2163) and GF(2571). The efficiency is achieved by reducing: (1) the time required for one PM computation and (2) the total number of required clock cycles. The required computational time for one PM computation is reduced by incorporating two modular multipliers (connected in parallel), a serially connected adder after multipliers and two serially connected squarer units (one after the first multiplier and another after the adder). To optimize the total number of required clock cycles, the point addition and point double instructions for PM computation of the Montgomery algorithm are re-structured. The implementation results after place-and-route over GF(2163) and GF(2571) on a Xilinx Virtex-7 FPGA device reveal that the proposed high-speed architecture is well-suited for the network-related applications, where millions of heterogeneous devices want to connect with the unsecured internet to reach an acceptable performance.

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Rehman, Khalid, and Zahid Ullah. "PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs." Wireless Communications and Mobile Computing 2021 (June 7, 2021): 1–9. http://dx.doi.org/10.1155/2021/5544435.

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Networks are continuously growing, and the demand for fast communication is rapidly increasing. With the increase in network bandwidth requirement, efficient packet-classification techniques are required. To achieve the requirements of these future networks at component level, every module such as routers, switches, and gateways needs to be upgraded. Packet classification is one of the main characteristics of a stable network which differentiates the incoming flow into defined streams. Existing packet classifiers have lower throughput to cope with the higher demand of the network. In this work, we propose a novel high-speed packet classifier named as PackeX that enables the network to receive and forward the data packets in a simplest structure. A size of 128-rule 32-bit is successfully implemented on Xilinx Virtex-7 FPGA. Experimental findings show that our proposed packet classifier is versatile and dynamic compared to the current FPGA-based packet classifiers achieving a speed of 119 million packets per second (Mpps), while consuming 53% less power compared with the state-of-the-art architectures.

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Danesh, Ahmad Reza, and Mehdi Habibi. "A signed pulse-train-based image processor-array for parallel kernel convolution in vision sensors." Sensor Review 40, no. 4 (June 26, 2020): 521–28. http://dx.doi.org/10.1108/sr-10-2019-0242.

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Purpose The purpose of this paper is to design a kernel convolution processor. High-speed image processing is a challenging task for real-time applications such as product quality control of manufacturing lines. Smart image sensors use an array of in-pixel processors to facilitate high-speed real-time image processing. These sensors are usually used to perform the initial low-level bulk image filtering and enhancement. Design/methodology/approach In this paper, using pulse-width modulated signals and regular nearest neighbor interconnections, a convolution image processor is presented. The presented processor is not only capable of processing arbitrary size kernels but also the kernel coefficients can be any arbitrary positive or negative floating number. Findings The performance of the proposed architecture is evaluated on a Xilinx Virtex-7 field programmable gate array platform. The peak signal-to-noise ratio metric is used to measure the computation error for different images, filters and illuminations. Finally, the power consumption of the circuit in different operating conditions is presented. Originality/value The presented processor array can be used for high-speed kernel convolution image processing tasks including arbitrary size edge detection and sharpening functions, which require negative and fractional kernel values.

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Jafri, Atif Raza, Muhammad Najam ul Islam, Malik Imran, and Muhammad Rashid. "Towards an Optimized Architecture for Unified Binary Huff Curves." Journal of Circuits, Systems and Computers 26, no. 11 (April 19, 2017): 1750178. http://dx.doi.org/10.1142/s021812661750178x.

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Applying unified formula while computing point addition and doubling provides immunity to Elliptic Curve Cryptography (ECC) against power analysis attacks (a type of side channel attack). One of the popular techniques providing this unifiedness is the Binary Huff Curves (BHC) which got attention in 2011. In this paper we are presenting highly optimized architectures to implement point multiplication (PM) on the standard NIST curves over [Formula: see text] and [Formula: see text] using BHC. To achieve a high throughput over area ratio, first of all, we have used a simplified arithmetic and logic unit. Secondly, we have reduced the time to compute PM through Double and Add algorithm. This is achieved by increasing the frequency of operation through a 2-stage pipelined architecture. The increase in clock cycles caused by consequent pipeline hazards is controlled through optimal scheduling of computations involved in PM. The synthesis results show that our designs can work up to a frequency of 377[Formula: see text]MHz on Xilinx Virtex 7 FPGA. Moreover, the overall throughput/area ratio achieved through the adopted approach is up to 20% higher while comparing with available state-of-the-art solutions.

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Khalifa, Khaled Ben, Ahmed Ghazi Blaiech, Mehdi Abadi, and Mohamed Hedi Bedoui. "New Hardware Architecture for Self-Organizing Map Used for Color Vector Quantization." Journal of Circuits, Systems and Computers 29, no. 01 (March 15, 2019): 2050002. http://dx.doi.org/10.1142/s0218126620500024.

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In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [Formula: see text] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.

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Hussein, Dina M., Abdelhalim Zekry, Said Baioumy, and Fatma El-Newagy. "Implementation of a standard inner convolutional codec for DVB-T system using VHDL." International Journal of Engineering & Technology 6, no. 4 (October 4, 2017): 131. http://dx.doi.org/10.14419/ijet.v6i4.8038.

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Forward error correction (FEC) plays a vital role in digital communication systems. DVB-T system uses FEC as a channel coding technique to restore any data lost through transmission to the receiver. DVB-T system uses two levels of error protection. The first level is applied in the data transmitted by using a Reed-Solomon RS (204, 188) code followed by a convolutional interleaver. The other level of error protection is a punctured convolutional inner coding followed by an inner interleave in which the data sequence is rearranged again to minimize the influence of burst errors.This paper describes the implementation of inner convolutional codec (Convolutional coder and Viterbi Decoder) and inner de/interleaving of a standard DVB-T system with a constrained length of 7 and a code rate of 2/3 using VHDL on virtex-6 FPGA xc6vlx240t. The designed channel convolutional encoder and Viterbi decoder follow European Standard ETSI EN 300 744 for digital terrestrial television. Verification of the design is accomplished by loop back and by comparison with the corresponding Xilinx core. Utilization and timing re-ports of the implemented device on Vertex 6 are included.

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Davalos-Guzman, Ulises, Carlos E. Castañeda, Lina Maria Aguilar-Lobo, and Gilberto Ochoa-Ruiz. "Design and Implementation of a Real Time Control System for a 2DOF Robot Based on Recurrent High Order Neural Network Using a Hardware in the Loop Architecture." Applied Sciences 11, no. 3 (January 27, 2021): 1154. http://dx.doi.org/10.3390/app11031154.

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In this paper, a real-time implementation of a sliding-mode control (SMC) in a hardware-in-loop architecture is presented for a robot with two degrees of freedom (2DOF). It is based on a discrete-time recurrent neural identification method, as well as the high performance obtained from the advantages of this architecture. The identification process uses a discrete-time recurrent high-order neural network (RHONN) trained with a modified extended Kalman filter (EKF) algorithm. This is a method for calculating the covariance matrices in the EKF algorithm, using a dynamic model with the associated and measurement noises, and it increases the performance of the proposed methodology. On the other hand, the decentralized discrete-time SMC technique is used to minimize the motion error. A Virtex 7 field programmable gate array (FPGA) is configured based on a hardware-in-loop real-time implementation to validate the proposed controller. A series of several experiments demonstrates the robustness of the algorithm, as well as its immunity to noise and the inherent robustness to external perturbation, as are typically found in the input reference signals of a 2DOF manipulator robot.

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Hasan, Raza, Yasir Khizar, Salman Mahmood, and Muhammad Kashif Sheikh. "Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher." Mathematical Problems in Engineering 2021 (June 16, 2021): 1–14. http://dx.doi.org/10.1155/2021/2599500.

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This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

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Kyriakos, Angelos, Elissaios-Alexios Papatheofanous, Charalampos Bezaitis, and Dionysios Reisis. "Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification." Journal of Imaging 8, no. 4 (April 15, 2022): 114. http://dx.doi.org/10.3390/jimaging8040114.

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A plethora of image and video-related applications involve complex processes that impose the need for hardware accelerators to achieve real-time performance. Among these, notable applications include the Machine Learning (ML) tasks using Convolutional Neural Networks (CNNs) that detect objects in image frames. Aiming at contributing to the CNN accelerator solutions, the current paper focuses on the design of Field-Programmable Gate Arrays (FPGAs) for CNNs of limited feature space to improve performance, power consumption and resource utilization. The proposed design approach targets the designs that can utilize the logic and memory resources of a single FPGA device and benefit mainly the edge, mobile and on-board satellite (OBC) computing; especially their image-processing- related applications. This work exploits the proposed approach to develop an FPGA accelerator for vessel detection on a Xilinx Virtex 7 XC7VX485T FPGA device (Advanced Micro Devices, Inc, Santa Clara, CA, USA). The resulting architecture operates on RGB images of size 80×80 or sliding windows; it is trained for the “Ships in Satellite Imagery” and by achieving frequency 270 MHz, completing the inference in 0.687 ms and consuming 5 watts, it validates the approach.

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Alharbi, Mohammed, Semih Isik, Abdulaziz Alkuhayli, and Subhashish Bhattacharya. "Power Ripple Control Method for Modular Multilevel Converter under Grid Imbalances." Energies 15, no. 10 (May 12, 2022): 3535. http://dx.doi.org/10.3390/en15103535.

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Modular multilevel converters (MMCs) are primarily adopted for high-voltage applications, and are highly desired to be operated even under fault conditions. Researchers focused on improving current controllers to reduce the adverse effects of faults. Vector control in the DQ reference domain is generally adopted to control the MMC applications. Under unstable grid conditions, it is challenging to control double-line frequency oscillations in the DQ reference frame. Therefore, active power fluctuations are observed in the active power due to the uncontrolled AC component’s double line frequency component. This paper proposes removing the active power’s double-line frequency under unbalanced grid conditions during DQ transformation. Feedforward and feedback control methods are proposed to eliminate ripple in active power under fault conditions. An extraction method for AC components is also proposed for the power ripple control to eliminate the phase error occurring with the conventional high-pass filters. The system’s stability with the proposed controller is tested and compared with a traditional MMC controller using the Nyquist stability criterion. A real-time digital simulator (RTDS) and Xilinx Virtex 7-based FPGA were used to verify the proposed control methods under single-line-to-ground (SLG) faults.

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Zheng, Xin, Xianghong Hu, Jinglong Zhang, Jian Yang, Shuting Cai, and Xiaoming Xiong. "An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT." Electronics 8, no. 9 (September 14, 2019): 1033. http://dx.doi.org/10.3390/electronics8091033.

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The Internet-of-Things (IoT) has a security problem that has become increasingly significant. New architecture of SM3 which can be implemented in loT devices is proposed in this paper. The software/hardware co-design approach is put forward to implement the new architecture to achieve high performance and low costs. To facilitate software/hardware co-design, an AHB-SM3 interface controller (AHB-SIC) is designed as an AHB slave interface IP to exchange data with the embedded CPU. Task scheduling and hardware resource optimization techniques are adopted in the design of expansion modules. The task scheduling and critical path optimization techniques are utilized in the compression module design. The proposed architecture is implemented with ASIC using SMIC 130 nm technology. For the purpose of comparison, the proposed architecture is also implemented on Virtex 7 FPGA with a 36 MHz system clock. Compared with the standard implementation of SM3, the proposed architecture saves the number of registers for approximately 3.11 times, and 263 Mbps throughput is achieved under the 36 MHz clock. This design signifies an excellent trade-off between performance and the hardware area. Thus, the design accommodates the resource-limited IoT security devices very well. The proposed architecture is applied to an intelligent security gateway device.

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Islam, Md Mainul, Md Selim Hossain, Moh Khalid Hasan, Md Shahjalal, and Yeong Min Jang. "Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve." Sensors 20, no. 18 (September 10, 2020): 5148. http://dx.doi.org/10.3390/s20185148.

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With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

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Journal articles on the topic 'Virtex-7'

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