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Relevant bibliographies by topics / Virtex-7

Academic literature on the topic 'Virtex-7'

Author: Grafiati

Published: 30 May 2022

Last updated: 31 May 2022

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Journal articles on the topic "Virtex-7"

1

Kalyaev, I. A., I. I. Levin, A. I. Dordopulo, and L. M. Slasten. "Reconfigurable Computer Systems Based on Virtex-6 and Virtex-7 FPGAs." IFAC Proceedings Volumes 46, no. 28 (2013): 210–14. http://dx.doi.org/10.3182/20130925-3-cz-3023.00009.

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ILES, G., J. Jones, and A. Rose. "Experience powering Xilinx Virtex-7 FPGAs." Journal of Instrumentation 8, no. 12 (December 20, 2013): C12037. http://dx.doi.org/10.1088/1748-0221/8/12/c12037.

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Rashid, Muhammad, Mohammad Mazyad Hazzazi, Sikandar Zulqarnain Khan, Adel R. Alharbi, Asher Sajid, and Amer Aljaedi. "A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography." Electronics 10, no. 21 (November 4, 2021): 2698. http://dx.doi.org/10.3390/electronics10212698.

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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

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Иванов, А., and Д. Никишин. "ВХОДНОЙ КОНТРОЛЬ МИКРОСХЕМ XILINX VIRTEX-7 С ПОМОЩЬЮ ПЕРИФЕРИЙНОГО СКАНИРОВАНИЯ." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 210, no. 9 (November 3, 2021): 94–98. http://dx.doi.org/10.22184/1992-4178.2021.210.9.94.98.

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Рассмотрено использование периферийного сканирования для реализации входного контроля микросхем Xilinx Virtex-7. Отмечено, что представленные решения могут быть использованы на предприятиях радиоэлектронной промышленности для проведения процедуры входного контроля.

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Pandey, Bishwajeet, Geetam S. Tomar, Rajina R. Mohamed, D. M. Akbar Hussain, and Amit Kant Pandit. "Energy Efficient Design on 16 nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate." Journal of Computational and Theoretical Nanoscience 17, no. 11 (November 1, 2020): 5122–24. http://dx.doi.org/10.1166/jctn.2020.9351.

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Scientists in 2010 were using a 40 nanometer Process based FPGA called Virtex-6 and 45 nm Process Technology based FPGA called Spartan-6. After 2010, researchers shifted their focus towards 28 nm technology based 7 series FPGA (Artix-7, Kintex-7, and Virtex-7) due to their intrinsic capability of low power consumption than both 40 nm and 45 nm technology based FPGA. In December, 2013, Xilinx introduced the 20 nm process technology based UltraScale series: Virtex UltraScale and Kintex UltraScale families. But now in 2020, researchers are using 16 nm technology based UltraScale+ FPGA. In our work, we are also using 16 nm technology based UltraScale+ FPGA for implementing our memory using VIVADO 2018.3 hardware programming tool and Verilog Hardware Description Language. There is 49.42%, 25.28% saving in design power on UltraScale+ FPGA when we minimize static probabilities to 0.1 and 0.2 respectively.

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Sajid, Asher, Muhammad Rashid, Malik Imran, and Atif Raza Jafri. "A Low-Complexity Edward-Curve Point Multiplication Architecture." Electronics 10, no. 9 (May 3, 2021): 1080. http://dx.doi.org/10.3390/electronics10091080.

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The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over GF(2233). There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32-bit finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over GF(2233) on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 µs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time.

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Chen, Baoju, Simin Yu, Ping Chen, Liangshan Xiao, and Jinhu Lü. "Design and Virtex-7-Based Implementation of Video Chaotic Secure Communications." International Journal of Bifurcation and Chaos 30, no. 05 (April 2020): 2050075. http://dx.doi.org/10.1142/s0218127420500753.

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In this paper, a Virtex-7-based video chaotic secure communication scheme is investigated. First, the network sending and receiving controller Intellectual Property (IP) cores are designed. Next, the chaotic encryption and decryption IP cores are implemented using fixed-point algorithm, pipeline operation, and state machine control. Thus, video capturing, video displaying, network sending, network receiving, chaotic encrypting, and chaotic decrypting can be achieved via IP core integration design. An improved 7D chaotic stream cipher algorithm for resisting divide-and-conquer attack is then designed and realized on a Virtex-7 high-end FPGA platform. Hardware experimental results are also given to verify the feasibility of the scheme.

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Rumyantsev, Yu A. "Direct data transfer between FPGAs Virtex-7 via PCI Express bus." Proceedings of the Institute for System Programming of RAS 24 (2013): 107–26. http://dx.doi.org/10.15514/ispras-2013-24-6.

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Sajid, Asher, Muhammad Rashid, Sajjad Shaukat Jamal, Malik Imran, Saud S. Alotaibi, and Mohammed H. Sinky. "AREEBA: An Area Efficient Binary Huff-Curve ARchitecture." Electronics 10, no. 12 (June 20, 2021): 1490. http://dx.doi.org/10.3390/electronics10121490.

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Elliptic curve cryptography is the most widely employed class of asymmetric cryptography algorithm. However, it is exposed to simple power analysis attacks due to the lack of unifiedness over point doubling and addition operations. The unified crypto systems such as Binary Edward, Hessian and Huff curves provide resistance against power analysis attacks. Furthermore, Huff curves are more secure than Edward and Hessian curves but require more computational resources. Therefore, this article has provided a low area hardware architecture for point multiplication computation of Binary Huff curves over GF(2163) and GF(2233). To achieve this, a segmented least significant digit multiplier for polynomial multiplications is proposed. In order to provide a realistic and reasonable comparison with state of the art solutions, the proposed architecture is modeled in Verilog and synthesized for different field programmable gate arrays. For Virtex-4, Virtex-5, Virtex-6, and Virtex-7 devices, the utilized hardware resources in terms of hardware slices over GF(2163) are 5302, 2412, 2982 and 3508, respectively. The corresponding achieved values over GF(2233) are 11,557, 10,065, 4370 and 4261, respectively. The reported low area values provide the acceptability of this work in area-constrained applications.

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Ye, Wen Hua, and Huan Li. "Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board." Applied Mechanics and Materials 719-720 (January 2015): 534–37. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.534.

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With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.

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Dissertations / Theses on the topic "Virtex-7"

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Жданова, Ю. В., and І. В. Свид. "Огляд сьомої серії FPGA компанії Xilinx." Thesis, Кременчуцький льотний коледж, 2019. http://openarchive.nure.ua/handle/document/9371.

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Савкин, Л. В. "Варианты проектных обликов регенеративных электронных систем на базе ПЛИС Xilinx семейства Virtex-7." Thesis, Сумский государственный университет, 2016. http://essuir.sumdu.edu.ua/handle/123456789/46432.

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Работа посвящена разработке и исследованию способов аппаратнопрограммного построения регенеративных электронных систем (РегЭС) [1] в целях интеграции, унификации и повышения надежности функционирования бортовой аппаратуры современных космических систем и комплексов.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://doi.org/10.35598/mcfpga.2019.008.

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Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-008.

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Book chapters on the topic "Virtex-7"

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Arul Murugan C. and Banuselvasaraswathy B. "Challenges in FPGA Technology Paradigm for the Implementation of IoT Applications." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 1–21. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-5225-9806-0.ch001.

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Internet of things (IoT) is a recent technology, and it will become the next generation of internet that connects several physical objects to interact amongst themselves without the assistance of human beings. It plays a significant role in our day-to-day lives and is used in several applications. IoT is a boon to this modern world, but it lacks in security. It cannot protect the user data from assailants, hackers, and vulnerabilities. Field programmable gate arrays (FPGA) helps to achieve all these objectives by incorporating secured end-to-end layer into its architecture. In this chapter, ultralow power and reduced area AES architecture with energy efficient DSE-S box techniques and clock gating for IoT applications are introduced. The proposed AES architecture is implemented over different FPGA families such as Cyclone I, Cyclone II, Virtex 5, and Kintex 7, respectively. From the experimental results, it is observed that the Kintex 7 FPGA kit consumes less power than other FPGA families.

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Conference papers on the topic "Virtex-7"

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Mohsen, Abd El-Rahman, Mohamed Youssef GadAlrab, Zeina elhaya Mahmoud, Gameel Alshaer, Mahmoud Asy, and Hassan Mostafa. "Remote FPGA Lab For ZYNQ and Virtex-7 Kits." In 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2019. http://dx.doi.org/10.1109/mwscas.2019.8885064.

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Weirich, Marcel. "Level-1 Calorimeter Trigger: From Virtex-7 to UltraScale+." In The 39th International Conference on High Energy Physics. Trieste, Italy: Sissa Medialab, 2019. http://dx.doi.org/10.22323/1.340.0203.

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Jose, Wilson, Ana Rita Silva, Horacio Neto, and Mario Vestias. "Analysis of matrix multiplication on high density Virtex-7 FPGA." In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2013. http://dx.doi.org/10.1109/fpl.2013.6645604.

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Singh, Aslesa, Neil Franklin, Nidhi Gaur, and Paursuh Bhulania. "Design and Implementation of a 32-bit ISA RISC-V Processor Core using Virtex-7 and Virtex- UltraScale." In 2020 IEEE 5th International Conference on Computing Communication and Automation (ICCCA). IEEE, 2020. http://dx.doi.org/10.1109/iccca49541.2020.9250850.

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Wenhua Ye and Huan Li. "Virtex-7 FPGA-based high-speed signal processing hardware platform design." In 2013 IEEE 4th International Conference on Electronics Information and Emergency Communication (ICEIEC). IEEE, 2013. http://dx.doi.org/10.1109/iceiec.2013.6835466.

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Zhu, Ming, Yingtao Jiang, Mei Yang, and Louie De Luna. "A Scalable Parameterized NoC Emulator Built Upon Xilinx Virtex-7 FPGA." In 2017 25th International Conference on Systems Engineering (ICSEng). IEEE, 2017. http://dx.doi.org/10.1109/icseng.2017.44.

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El-Maksoud, Ahmed J. Abd, Amr Gamal, Aya Hesham, Gamal Saied, Mennat-Allah Ayman, Omnia Essam, Sara M. Mohamed, et al. "Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA." In 2021 International Conference on Microelectronics (ICM). IEEE, 2021. http://dx.doi.org/10.1109/icm52667.2021.9664956.

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Gad, Ali H., Seif Eldeen E. Abdalazeem, Omar A. Abdelmegid, and Hassan Mostafa. "Low power and area SHA-256 hardware accelerator on Virtex-7 FPGA." In 2020 2nd Novel Intelligent and Leading Emerging Sciences Conference (NILES). IEEE, 2020. http://dx.doi.org/10.1109/niles50944.2020.9257922.

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Nozaki, Yusuke, Shu Takemoto, Yoshiya Ikezaki, and Masaya Yoshikawa. "Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7." In 2021 International Symposium on Devices, Circuits and Systems (ISDCS). IEEE, 2021. http://dx.doi.org/10.1109/isdcs52006.2021.9397891.

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Jiang, Xin, Yang Zhou, Ning Wang, Dongrui Jia, and Leichen Zhou. "Theory and Simulation of High-speed Data Transmission Based on Virtex-7 GTH." In International Conference on Chemical,Material and Food Engineering. Paris, France: Atlantis Press, 2015. http://dx.doi.org/10.2991/cmfe-15.2015.150.

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