Relevant bibliographies by topics / VHDL / Journal articles

Journal articles on the topic 'VHDL'

To see the other types of publications on this topic, follow the link: VHDL.
Author: Grafiati
Published: 4 June 2021
Last updated: 25 July 2024

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'VHDL.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Swamy, S., A. Molin, and B. Covnot. "OO-VHDL. Object-oriented extensions to VHDL." Computer 28, no. 10 (1995): 18–26. http://dx.doi.org/10.1109/2.467587.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Dewey, Allen, and Anthony Gadient. "VHDL Motivation." IEEE Design & Test of Computers 3, no. 2 (1986): 12–16. http://dx.doi.org/10.1109/mdt.1986.294898.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Nash, J. D., and L. F. Saunders. "VHDL Critique." IEEE Design & Test of Computers 3, no. 2 (1986): 54–65. http://dx.doi.org/10.1109/mdt.1986.294917.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Ashenden, P. J. "VHDL standards." IEEE Design & Test of Computers 18, no. 5 (2001): 122–23. http://dx.doi.org/10.1109/54.953280.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Helbig, J., R. Schlör, W. Damm, G. Döhmen, and P. Kelb. "VHDL/S — integrating statecharts, timing diagrams, and VHDL." Microprocessing and Microprogramming 38, no. 1-5 (September 1993): 571–80. http://dx.doi.org/10.1016/0165-6074(93)90197-s.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Varga, László, Gábor Hosszú, and Ferenc Kovács. "Design Procedure Based on VHDL Language Transformations." VLSI Design 14, no. 4 (January 1, 2002): 349–54. http://dx.doi.org/10.1080/10655140290011159.

Full text
Abstract:
One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstract VHDL model and produces an RTL VHDL description through successive language transformations while preserving the VHDL standard simulation semantics. The steps of the synthesis do not use graph representation or other meta-language, but apply the standard VHDL only. This VHDL representation is simulatable and accessible, functional verification can be performed by simulation at any time, and the simulation results can be used to guide the synthesis process. The output VHDL format is suitable to continue the design flow with RTL based synthesis tools.
APA, Harvard, Vancouver, ISO, and other styles
7

Lipsett, Roger, Erich Marschner, and Moe Shahdad. "VHDL - The Language." IEEE Design & Test of Computers 3, no. 2 (April 1986): 28–41. http://dx.doi.org/10.1109/mdt.1986.294900.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Hands, J. P. "What is VHDL?" Computer-Aided Design 22, no. 4 (May 1990): 246–49. http://dx.doi.org/10.1016/0010-4485(90)90054-g.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Nagler, James J., and David R. Idler. "Ovarian uptake of vitellogenin and another very high density lipoprotein in winter flounder (Pseudopleuronectes americanus) and their relationship with yolk proteins." Biochemistry and Cell Biology 68, no. 1 (January 1, 1990): 330–35. http://dx.doi.org/10.1139/o90-045.

Full text
Abstract:
Ultracentrifugation analysis of female winter flounder plasma confirmed that in addition to vitellogenin another different lipoprotein is found as very high density lipoprotein (VHDL). Accordingly this protein (formerly known as peak A protein) has been named VHDL II, with respect to vitellogenin which we designate VHDL I. Both these proteins were shown to be taken up in vivo by the ovary of vitellogenic females. Based on total mass, vitellogenin and VHDL II could potentially contribute in similar amounts to yolk protein accumulated by developing oocytes. Sodium dodecyl sulfate – polyacrylamide gel electrophoresis of vitellogenic oocyte yolk proteins revealed five major protein subunits of 101.4, 94.4, 68.7, 25.5, and 22.5 kilodaltons (kDa). Western blots of these yolk protein subunits established three of them (104.4, 94.4, and 22.5 kDa) as originating from vitellogenin. Similar Western blots utilizing a VHDL II antisera identified the 68.7-kDa yolk protein subunit as arising from incorporated serum VHDL II.Key words: VHDL II, vitellogenin, oocyte yolk proteins, in vivo uptake, Western blot.
APA, Harvard, Vancouver, ISO, and other styles
10

Dickinson, Brian. "VHDL '92: The new features of the VHDL hardware description language." Microprocessors and Microsystems 19, no. 2 (January 1995): 106–7. http://dx.doi.org/10.1016/0141-9331(95)90002-0.

Full text
APA, Harvard, Vancouver, ISO, and other styles
11

Al-Sheikh, Zakaria Mohamed H., Abdullah Ali Qasem Qahtan, and Abdul Raqib Abdo Asaad. "Ternary Electronic Logic Systems Automation: A Novel Study Based on VHDL Language - First Part: Ternary Logic Gates." Journal of Science and Technology 22, no. 2 (February 26, 2018): 27–47. http://dx.doi.org/10.20428/jst.v22i2.1282.

Full text
Abstract:
In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. Keywords: Ternary logic, Ternary logic gates, VHDL language.
APA, Harvard, Vancouver, ISO, and other styles
12

Marcus, Lloyde George, and Joseph Brandon. "Development of a control path VHDL code generator for hardware development." i-manager’s Journal on Software Engineering 16, no. 3 (2022): 16. http://dx.doi.org/10.26634/jse.16.3.18660.

Full text
Abstract:
The Very High-Speed Integration Circuit HDL (VHDL) is widely used to implement digital electronic systems. The VHDL language can be difficult to learn, so it is necessary to simplify and speed up the process of implementing digital electronic components through a hardware description with a minimal understanding of the VHDL language. This paper entails the design and development of a Graphical User Interface (GUI) capable of generating VHDL code for ControlPaths using specified state transition tables and state diagrams. This application was created using the Matrix Laboratory (MATLAB). Application Builder as the development platform. After development, the system went through unit testing and integration testing, after which acceptance testing was carried out. The results of the acceptance tests showed that the software is very effective in quickly generating VHDL code for ControlPaths.
APA, Harvard, Vancouver, ISO, and other styles
13

Memon, Farida, Aamir Hussain Memon, Shahnawaz Talpur, Fayaz Ahmed Memon, and Rafia Naz Memon. "Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim." July 2016 35, no. 3 (July 1, 2016): 473–82. http://dx.doi.org/10.22581/muet1982.1603.17.

Full text
Abstract:
In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.
APA, Harvard, Vancouver, ISO, and other styles
14

Gilman, Alfred. "VHDL - The Designer Environment." IEEE Design & Test of Computers 3, no. 2 (April 1986): 42–47. http://dx.doi.org/10.1109/mdt.1986.294902.

Full text
APA, Harvard, Vancouver, ISO, and other styles
15

Alford, David B. "ASIC design with VHDL." ACM SIGDA Newsletter 20, no. 3 (January 22, 1991): 32–51. http://dx.doi.org/10.1145/122561.122562.

Full text
APA, Harvard, Vancouver, ISO, and other styles
16

Martello, Alan R., and Steven P. Levitan. "A VHDL design environment." ACM SIGDA Newsletter 20, no. 3 (January 22, 1991): 52–67. http://dx.doi.org/10.1145/122561.122563.

Full text
APA, Harvard, Vancouver, ISO, and other styles
17

Demian, Petru, and Aurel-Stefan Gontean. "TMS320C203 VHDL System Modelling." IFAC Proceedings Volumes 33, no. 1 (February 2000): 81–84. http://dx.doi.org/10.1016/s1474-6670(17)35591-x.

Full text
APA, Harvard, Vancouver, ISO, and other styles
18

Sciuto, D. "Special section on VHDL." Journal of Systems Architecture 44, no. 1 (October 1997): 1–2. http://dx.doi.org/10.1016/s1383-7621(97)00013-1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
19

Carroll, M. "VHDL-panacea or hype?" IEEE Spectrum 30, no. 6 (June 1993): 34–37. http://dx.doi.org/10.1109/6.214581.

Full text
APA, Harvard, Vancouver, ISO, and other styles
20

Reetz, Ralf, and Thomas Kropf. "A flowgraph semantics of VHDL: Toward a VHDL verification workbench in HOL." Formal Methods in System Design 7, no. 1-2 (August 1995): 73–99. http://dx.doi.org/10.1007/bf01383874.

Full text
APA, Harvard, Vancouver, ISO, and other styles
21

Saucedo-Flores, Salvador, and Roberto Galicia-Galicia. "Árbitros semi-rotatorios con VHDL." Científica 20, no. 2 (December 2016): 63–69. http://dx.doi.org/10.46842/ipn.cien.v20n2a01.

Full text
Abstract:
En los sistemas de buses en un chip (System on-Chip, SoC), las propiedades intelectuales (Intellectual Property, IP) necesitan comunicarse entre cada una para acceder a la funcionalidad requerida. Cuando el bus del SoC es conectado con más IP, la contención ocurre mientras múltiples IP requieren el uso del bus al mismo tiempo. Ello causa que la comunicación entre arquitecturas basadas en un chip bus sea un reto mayor para el diseñador del sistema con las actuales tecnologías SoC. Las arquitecturas de comunicación deben poder adaptarse por sí mismas de acuerdo con los requisitos de tiempo real de las IP. Por ello, los árbitros de buses son propuestos. El árbitro juega un papel importante en el bus de comunicación del SoC. Los máster en un bus de SoC pueden requerir simultáneamente y, por ello, un árbitro es requerido para decidir cuál máster es electo para el acceso del bus. Un árbitro de buses juega un rol vital en el manejo de peticiones desde el maestro y las respuestas del esclavo (como señal ACK, reintento, etc.). El principal objetivo del algoritmo de arbitración es asegurar que solo un maestro tenga acceso al bus en cualquier tiempo dado, los demás maestros son forzados a permanecer ociosos hasta que reciben la concesión de usar el bus.
APA, Harvard, Vancouver, ISO, and other styles
22

Avdeev, N. A., and P. N. Bibilo. "Design of Digital Operational Units with Low Power Consumption." Programmnaya Ingeneria 12, no. 2 (March 16, 2021): 63–73. http://dx.doi.org/10.17587/prin.12.63-73.

Full text
Abstract:
The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.
APA, Harvard, Vancouver, ISO, and other styles
23

SALEH, ANDHI RACHMAN, and SUNNY ARIEF SUDIRO. "CRC 8-bit Encoder-Decoder Component in FPGA using VHDL." ELKOMIKA: Jurnal Teknik Energi Elektrik, Teknik Telekomunikasi, & Teknik Elektronika 8, no. 1 (January 31, 2020): 58. http://dx.doi.org/10.26760/elkomika.v8i1.58.

Full text
Abstract:
AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i
APA, Harvard, Vancouver, ISO, and other styles
24

Alukaidey, Talib. "Book Review: Introduction to VHDL:." International Journal of Electrical Engineering & Education 34, no. 3 (July 1997): 286–88. http://dx.doi.org/10.1177/002072099703400314.

Full text
APA, Harvard, Vancouver, ISO, and other styles
25

Harrold, S. J. "Book Review: VHDL Made Easy." International Journal of Electrical Engineering Education 35, no. 2 (April 1998): 189. http://dx.doi.org/10.1177/002072099803500211.

Full text
APA, Harvard, Vancouver, ISO, and other styles
26

Chang, J. M., and S. K. Agun. "Design-for-reusability in VHDL." Computing & Control Engineering Journal 12, no. 5 (October 1, 2001): 231–39. http://dx.doi.org/10.1049/cce:20010505.

Full text
APA, Harvard, Vancouver, ISO, and other styles
27

Pandey, S. L., K. Umamageswaran, and P. A. Wilsey. "VHDL semantics and validating transformations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, no. 7 (July 1999): 936–55. http://dx.doi.org/10.1109/43.771177.

Full text
APA, Harvard, Vancouver, ISO, and other styles
28

Ashenden, P. J. "Modeling digital systems using VHDL." IEEE Potentials 17, no. 2 (1998): 27–30. http://dx.doi.org/10.1109/45.666643.

Full text
APA, Harvard, Vancouver, ISO, and other styles
29

Aylor, J. H., R. Waxman, and C. Scarratt. "VHDL - Feature Description And Analysis." IEEE Design & Test of Computers 3, no. 2 (April 1986): 17–27. http://dx.doi.org/10.1109/mdt.1986.294899.

Full text
APA, Harvard, Vancouver, ISO, and other styles
30

Ghatte, Najib, Shilpa Patil, and Deepak Bhoir. "Floating Point Engine using VHDL." International Journal of Engineering Trends and Technology 8, no. 4 (February 25, 2014): 198–203. http://dx.doi.org/10.14445/22315381/ijett-v8p236.

Full text
APA, Harvard, Vancouver, ISO, and other styles
31

DeGroat, J. E. "Transparent logic modeling in VHDL." IEEE Design & Test of Computers 7, no. 3 (June 1990): 42–48. http://dx.doi.org/10.1109/54.56466.

Full text
APA, Harvard, Vancouver, ISO, and other styles
32

d’Amore, Roberto. "A Synthesis-Oriented VHDL Course." ACM Transactions on Computing Education 10, no. 2 (June 2010): 1–24. http://dx.doi.org/10.1145/1789934.1789936.

Full text
APA, Harvard, Vancouver, ISO, and other styles
33

Navabi, Zainalabedin. "Report on VHDL methods workshop." ACM SIGDA Newsletter 20, no. 1 (June 1990): 105. http://dx.doi.org/10.1145/378886.380417.

Full text
APA, Harvard, Vancouver, ISO, and other styles
34

Woo, A. C., and L. E. Peppard. "System-level modelling in VHDL." Microelectronics Journal 23, no. 3 (May 1992): 223–30. http://dx.doi.org/10.1016/0026-2692(92)90014-r.

Full text
APA, Harvard, Vancouver, ISO, and other styles
35

White, Martin, Marcus D. Waller, Graham J. Dunnett, Paul F. Lister, and Richard L. Grimsdale. "Graphics ASIC design using VHDL." Computers & Graphics 19, no. 2 (March 1995): 301–8. http://dx.doi.org/10.1016/0097-8493(94)00156-s.

Full text
APA, Harvard, Vancouver, ISO, and other styles
36

Stojčev, M. "The designer's guide to VHDL." Microelectronics Journal 29, no. 3 (March 1998): 157–58. http://dx.doi.org/10.1016/s0026-2692(97)00015-3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
37

Hurst, Stanley L. "VHDL: A logic synthesis approach." Microelectronics Journal 29, no. 8 (August 1998): 572. http://dx.doi.org/10.1016/s0026-2692(98)80018-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
38

Hurst, S. L. "Structured logic design with VHDL." Microelectronics Journal 25, no. 2 (March 1994): 144. http://dx.doi.org/10.1016/0026-2692(94)90119-8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
39

Adamski, Marian. "Structured Logic Design with VHDL." Microprocessors and Microsystems 18, no. 10 (December 1994): 621–22. http://dx.doi.org/10.1016/0141-9331(94)90040-x.

Full text
APA, Harvard, Vancouver, ISO, and other styles
40

K L, Suseenthiran, Saravanan T, and Selvakumar K. "ATM Security Enhancement using VHDL." International Journal of VLSI & Signal Processing 3, no. 1 (April 25, 2016): 12–15. http://dx.doi.org/10.14445/23942584/ijvsp-v3i1p104.

Full text
APA, Harvard, Vancouver, ISO, and other styles
41

Egolf, T., M. Pettigrew, J. DeBardelaben, R. Hezar, S. Famorzadeh, A. Kavipurapu, M. Khan, et al. "VHDL-based rapid system prototyping." Journal of VLSI signal processing systems for signal, image and video technology 14, no. 2 (November 1996): 125–56. http://dx.doi.org/10.1007/bf00925496.

Full text
APA, Harvard, Vancouver, ISO, and other styles
42

Olcoz, Serafin, and JoséManuel Colom. "Analysis tools applied to VHDL." Microprocessing and Microprogramming 38, no. 1-5 (September 1993): 597–604. http://dx.doi.org/10.1016/0165-6074(93)90200-5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
43

Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (September 1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.

Full text
APA, Harvard, Vancouver, ISO, and other styles
44

Lindh, Lennart, Johan Stärner, and Joakim Adomat. "Experiences with VHDL and FPGAs." Journal of Systems Architecture 42, no. 2 (September 1996): 97–104. http://dx.doi.org/10.1016/1383-7621(96)00016-1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
45

Hammadi Jassim, Manal. "Floating Point Optimization Using VHDL." Engineering and Technology Journal 27, no. 16 (December 1, 2009): 3023–49. http://dx.doi.org/10.30684/etj.27.16.11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
46

Ashenden, Peter J., Henry Detmold, and Wayne S. McKeen. "Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms." VLSI Design 2, no. 1 (January 1, 1994): 1–16. http://dx.doi.org/10.1155/1994/86178.

Full text
Abstract:
In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware models written in VHDL. We survey central event queue, conservative distributed and optimistic distributed PDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of these algorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at the University of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. We present measurements taken from this kernel simulating some benchmark models. It appears that this technique, which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktop multiprocessor workstations), simulating behavioral and register transfer level models. However, the degree of useful parallelism achievable on gate level models with this technique appears to be limited.
APA, Harvard, Vancouver, ISO, and other styles
47

Kerschbaumer, Ricardo, Robson R. Linhares, Jean M. Simão, Paulo C. Stadzisz, and Carlos R. Erig Lima. "Notification-Oriented Paradigm to Implement Digital Hardware." Journal of Circuits, Systems and Computers 27, no. 08 (April 12, 2018): 1850124. http://dx.doi.org/10.1142/s0218126618501244.

Full text
Abstract:
The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.
APA, Harvard, Vancouver, ISO, and other styles
48

Yi, Zhao Xiang, Xiong Mei Zhang, Ning Li, and Xiao Dong Mu. "A Visual Dependency Analysis Method Based on VHDL." Applied Mechanics and Materials 738-739 (March 2015): 582–85. http://dx.doi.org/10.4028/www.scientific.net/amm.738-739.582.

Full text
Abstract:
Modern complex circuits are described in very high speed integrated circuit hardware description language (VHDL) and difficult to verify. This paper proposes a systematic and visual dependency analysis method based on VHDL. The dependency relationships including control dependency, data dependency, signal control dependency and signal data dependency are defined. The entity dependency graph is presented and its generation algorithm, which searches the dependency relationships in hardware processes and between hardware processes, are developed. The experiment of a typical keyboard demonstrates that it is a visual and efficient method to analyze dependency relationships of VHDL for formal verification.
APA, Harvard, Vancouver, ISO, and other styles
49

Baraona, Phillip, and Perry Alexander. "Abstract Architecture Representation Using VSPEC." VLSI Design 9, no. 2 (January 1, 1999): 181–201. http://dx.doi.org/10.1155/1999/95465.

Full text
Abstract:
Complex digital systems are often decomposed into architectures very early in the design process. Unfortunately, traditional simulation based languages such as VHDL do not allow the impact of these architectural decisions to be evaluated until a complete, simulatable design of the system is available. After a complete design is available, architectural errors are time-consuming and expensive to correct. However, there is an alternative to simulation based techniques: formal analysis of abstract architectures at the requirements level. This paper describes VSBEC'S approach for defining and analyzing abstract architectures. VSBEC is a Larch interface language for VHDL that allows a designer to specify the requirements of a VHDL entity using the canonical Larch approach. VHDL structural architectures that instantiate VSPEC entities define abstract architectures. These abstract architectures can be evaluated at the requirements level to determine the impact of architectural decisions. This paper briefly introduces VSPEC provides a formal definition of VSPEC abstract architectures and presents two examples that illustrate the architectural definition capabilities of the language.
APA, Harvard, Vancouver, ISO, and other styles
50

Bibilo, P. N. "Hardware Implementation of Digital Operational Low Power Units in FPGA." Programmnaya Ingeneria 14, no. 2 (February 8, 2023): 62–68. http://dx.doi.org/10.17587/prin.14.62-68.

Full text
Abstract:
The results of experiments on hardware implementation of various VHDL models of operating devices in FPGA oriented to reducing power consumption are described. Operating devices are also called finite state machines with data paths. It is established that the VHDL model based on clock gating, which is most effective for custom VLSI, can not be implemented in FPGA. Effective models for FPGA are VHDL models based on zeroing unused operands or storing their values in additional memory registers. After conducting an experimental comparison of various methods for a specific operating device (or other digital device), the designer can choose a suitable (compromise) method of VHDL description, considering the obtained values of the parameters of power consumption, performance and hard­ware complexity. The article is a direct continuation of the previous article [1], which describes in detail the models under study and presents the results of experiments on hardware implementation of the same operating devices as part of custom CMOS VLSI
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the bibliographies on the topic 'VHDL' for other source types:
Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography