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Dissertations / Theses on the topic 'VHDL'

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Published: 4 June 2021
Last updated: 25 July 2024

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1

Shu, Shin-Ming. "EPLD modeling with VHDL." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/25899.

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2

Hicks, William T., and Robert E. Yantorno. "CVSD MODULATOR USING VHDL." International Foundation for Telemetering, 2004. http://hdl.handle.net/10150/605317.

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California
IRIG-106 Chapter 5 describes a method for encoding voice using a simple circuit to reduce the overall bit rate and still achieve good quality voice. This well described Continuously Variable Slope Delta Modulation (CVSD) circuit can be obtained using analog parts. A more stable implementation of CVSD can be obtained by designing an anti-aliasing input filter, an A/D converter, and logic. This paper describes one implementation of the CVSD using a standard A/D converter and logic.
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3

BAPAT, SACHIN VASUDEO. "THE PERFORMANCE EVALUATION OF VHDL-AMS SIMULATORS BY CREATING LARGE, SCALABLE VHDL-AMS MODELS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1032179532.

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4

Tong, Yanhui. "VHDL implementation of turbo codec." Thesis, University of Ottawa (Canada), 2003. http://hdl.handle.net/10393/26405.

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Turbo coding is one of the most significant achievements in coding theory during the last decade. It has been shown in the literature that transmission systems employing turbo codes could achieve a performance close to the Shannon limit. Turbo decoding is the major contributor to the overall complexity of turbo coding. Therefore, the challenge is to implement turbo coding in various communications systems at affordable decoding complexity using current VLSI technology. Four different turbo decoding algorithms were investigated in this thesis. Comparisons on both their performances and implementation complexities were performed. Log-MAP based turbo decoding offers the best compromise among the different turbo decoding algorithms. A Register-Transfer-Level (RTL) fixed-point turbo decoder model based on Log-MAP algorithm was designed and simulated using VHDL as the hardware description language. The RTL model was verified by comparing its simulation results with those obtained from a behavioral model of the same turbo decoder written in C language.
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5

Ardeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.

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6

Sprunger, Steven J. "UML modeling for VHDL designs." Virtual Press, 2008. http://liblink.bsu.edu/uhtbin/catkey/1399192.

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Unified Modeling Language (UML) allows software engineers to use a standard way of expressing a design approach at a high level. The benefits of system modeling are well accepted in the software development community. Modeling of Very High Speed Integrated Circuit Hardware Description Language (VHDL) designs, for synthesizing into hardware, is a common practice also. The research herein looks at system modeling of a design using UML, in which there are both software and hardware components. The idea is to explore modeling of the system with the ability to abstract whether the implementation of a particular function is realized in software or hardware. The designer can then model/evaluate a given system design approach and later allocate functions to software and hardware, as appropriate to meet constraints such as performance, cost, schedule. Since using UML for software is a standard approach, this research investigates the UML to hardware path via VHDL.
Department of Computer Science
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7

Mecera, Martin. "Transformace jazyka C do VHDL." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-237149.

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The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.
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8

Novotný, Jaroslav. "Návrh vícejádrového procesoru ve VHDL." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-235548.

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The objective of the thesis is to design and implement in the VHDL language a simple multiprocessor supporting parallel computing. Furthemore, the author has designed and realized universal transparent generic interconnection layer with the objective to connect any given number of processor cores to shared address space using arbitrated bus. Parametrized cache has been allocated to each core in the layer. MSI protocol was used to deal with the issue of memory coherence of the implemented system. Direct and indirect synchornisation support is available to the user. In order to verify the functionality of the system, simple processor core has been designed and implemented, and its copies were connected to the interconnection layer. Various testing programmes have been used to verify the functionality of the system, which also confirmed that the acceleration of computing has been achieved successfully. Virtex6 chip has been used to test the whole system.
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9

CHACKO, BABU. "A VHDL-AMS BSIM4.1 MODEL." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1206121503.

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10

Ailes, John W. Lee Chin-Hwa. "Automated digital hardware synthesis using VHDL." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School; Available from the National Technical Information Service, 1991. http://handle.dtic.mil/100.2/ADA246976.

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11

Shah, Sandeep R. "A framework for synthesis from VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-03022010-020143/.

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12

Phillips, Walter. "VHDL design of computer vision tasks." Honors in the Major Thesis, University of Central Florida, 2001. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/240.

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This item is only available in print in the UCF Libraries. If this is your Honors Thesis, you can help us make it available online for use by researchers around the world by following the instructions on the distribution consent form at http://library.ucf.edu/Systems/DigitalInitiatives/DigitalCollections/InternetDistributionConsentAgreementForm.pdf You may also contact the project coordinator, Kerri Bottorff, at kerri.bottorff@ucf.edu for more information.
Bachelors
Engineering
Computer Science
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13

Ailes, John W. "Automated digital hardware synthesis using VHDL." Thesis, Monterey, California: U.S. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/34999.

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14

Burnette, David G. "A graphical representation for VHDL models." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43381.

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This paper describes a graphical representation technique for models in VHDL. The graphical representation is an extension of the Process Model Graph described in [1]. The Process Model Graph has representations for concurrent processes and signals. The representation described here, referred to as the Modified Process Model Graph, adds several new constructs to handle more features of VHDL. These new constructs include: variables inside process blocks, a visual notation for sensitivity lists, and a clear visual indication of the interface to an object. A software tool, called VHDLCad* (c)* * , has been developed that uses produces VHDL source code interactively from the graphical representation. The tool allows the user to use pre-defined modules, or create new modules and place them in the library. With the benefit of a graphical representation, a menu-driven system and re-usable code, VHDLCad can improve the productivity of VHDL modelers. *VHDLCad is a trademark of David G. Burnette. **Copyright 1988 by David G. Burnette. All rights reserved
Master of Science
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15

Kožený, Petr. "Implementace šifrovacích algoritmů v jazyku VHDL." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2008. http://www.nusl.cz/ntk/nusl-235444.

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This thesis deals with design and implementation of AES and DES encryption architectures for embedded systems. Architectures are implemented in VHDL language and design for FPGA technology. The proposed implementations are mapped on the Xilinx Spartan 3 technology. Both architectures are applied in simple ECB (Electronic Codebook) scheme with cache memories. A maximum throughput of design DES architecture 370 Mbps is achived with clock frequency of 104 MHz. The throughput of AES architecture at the maximum clock frequency of 118 MHz is 228 Mbps. Compared to software implementations for embedded systems, we achieve significantly higher throughput for both architectures.
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16

Madala, Raghu Sagar. "Modeling of BJT in VHDL-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1154637611.

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17

Nicoli, Félix. "Vérification formelle de descriptions VHDL comportementales." Aix-Marseille 1, 1999. http://www.theses.fr/1999AIX11031.

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Cette these s'inscrit dans le cadre de la verification formelle de circuits digitaux et traite plus particulierement de la certification de descriptions vhdl comportementales en vue de la synthese de haut niveau de composants electroniques. Notre approche consiste a modeliser une partie du langage vhdl dans le demonstrateur de theoremes nqthm. Pour ce faire, nous distinguons un sous-ensemble comportemental de vhdl qui inclut les process, toutes les instructions sequentielles de base et les fonctions utilisateur (en particulier les fonctions de resolution). Nous definissons ensuite la semantique denotationnelle de ce sous-ensemble, ce qui permet de donner un enonce extremement rigoureux et precis de la simulation des descriptions qui en sont issues en terme de cycle delta. Le comportement des signaux est modelise par des pilotes et des historiques. Nous deduisons de cette formalisation, des regles de traduction systematique de vhdl vers le demonstrateur nqthm. Nous obtenons un ensemble de fonctions recursives qui modelisent une description vhdl et sa simulation. La verification d'une description repose sur ces definitions ainsi que sur des bibliotheques generales de theoremes en particulier sur le modele du temps de vhdl, les pilotes, les historiques, et les primitives vhdl. Nous proposons une methode reutilisable de preuve pour une classe specifique de descriptions : une seule instruction de temporisation par process et des affectations de signal a delai nul. Cette strategie repose sur la preuve de proprietes qui doivent etre verifiees par la simulation d'une description.
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18

Gadagkar, Ashish. "Timing distribution in VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10102009-020318/.

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19

Wright, Philip A. "Rapid development of VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-11102009-020056/.

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20

Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.

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21

Gummadi, Ram. "Methodology for structured VHDL model development." Thesis, This resource online, 1995. http://scholar.lib.vt.edu/theses/available/etd-03172010-020739/.

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22

Hu, Ta-Hsiang. "Discrete cosine transform implementation in VHDL." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA245791.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 1990.
Thesis Advisor(s): Lee, Chin-Hwa ; Yang, Chyan. "December 1990." Description based on title screen as viewed on March 29, 2010. DTIC Identifier(s): Fast Fourier Transform, High Level Languages, CHIPS (Electronics), Computerized Simulation, Signal Processing, Theses, Algorithms, Floating Point Operation, VHDL (Vhsic Hardware Description Language). Author(s) subject terms: FFT System, DCT System Implementation. Includes bibliographical references (p. 152). Also available in print.
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23

Van, Tassel John Peter. "Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant." Thesis, University of Cambridge, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308190.

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24

Dacheng, Chen. "VHDL Implementation of a Fast Adder Tree." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3838.

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This thesis discusses the design and implementation of a VHDL generator for Wallace tree with (3:2) counter modules and (2:2) counter modules to solve fast addition problem.

The basic research has been carried out by MATLAB programming environment and automatic generation of VHDL file based on the result obtained from MATLAB simulation. MODELSIM has been used for compilation and simulation of the VHDL file.

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25

Hymans, Charles. "Vérification de descriptions VHDL par interprétation abstraite." Phd thesis, Ecole Polytechnique X, 2004. http://pastel.archives-ouvertes.fr/pastel-00000875.

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Cette thèse traite de la vérification automatique de composants matériels décrits en VHDL. C'est une étude de faisabilité d'un outil de vérification automatique qui réunit: exhaustivité, efficacité de calcul et simplicité d'utilisation. La méthodologie de l'interprétation abstraite a été adoptée: l'algorithme de simulation de VHDL est d'abord formalisé par une sémantique opérationnelle, de laquelle une analyse statique est dérivée de façon systématique par abstraction. L'analyse calcule un sur-ensemble des états accessibles. Le domaine numérique utilisé pour représenter les valeurs possibles des signaux de la description peut être choisi librement. Une instance possible de l'analyse a été implémenté en OCaml. Le domaine numérique choisi ici est celui des égalités linéaires entre variables booléennes. L'outil a permi de valider un code correcteur d'erreur de type Reed Solomon. Les performances sont excellentes, en particulier meilleures que celles du model checker à base de BDDs VIS.
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26

Cebelieu, Marie-Claude. "Utilisation de macro blocs en synthèse VHDL." Phd thesis, Grenoble INPG, 1995. http://tel.archives-ouvertes.fr/tel-00346055.

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Le contexte général de cette thèse se situe dans le domaine de la synthèse RTL (Register Transfer Level). Une spécification initiale en termes de transferts de registres décrite dans un langage de haut niveau (VHDL, Verilog) définit l'ordre des opérations. A partir de cette spécification, le système de synthèse RTL génère une description structurelle fonctionnellement équivalente interconnectant des portes de base et des macro blocs de la cible technologique. Le langage de description considéré ici est le langage VHDL standardisé par le groupe IEEE en 1987. Ce choix est justifié par une étude comparative entre différents langages. Les principales caractéristiques du langage VHDL ainsi que les améliorations apportées par la nouvelle norme de 1992 sont évoquées. Dans une seconde partie, les limitations du langage VHDL pour son utilisation en synthèse et le flot de conception à partir d'une spécification RTL sont présentés. Plusieurs modèles VHDL d'éléments simples et de macro blocs sont décrits pour la synthèse. Le flot général de conception utilisant ces macro blocs est analysé et détaillé pour deux cas pratiques: l'utilisation des générateurs XBLOX de Xilinx et ACTgen d'Actel dans le logiciel de synthèse ASYL+. La dernière partie s'attache plus précisément à la modélisation d'éléments de bibliothèques en vue de leur utilisation en synthèse. Un format de bibliothèque, permettant de décrire tout aussi bien des portes simples que des macro blocs, est défini. Le nouveau format de bibliothèque standard VITAL est analysé ainsi que ses perspectives d'utilisation en simulation et en synthèse. La norme LPM qui définit un ensemble d'éléments standards indépendants de la technologie est également présentée. Cette dernière partie a conduit à la définition d'un nouveau flot de synthèse unifié utilisant les macro blocs et à la mise en place de plusieurs optimisations basées sur la notion de dérivation
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27

Sama, Anil. "Behavior modeling of RF systems with VHDL." Thesis, This resource online, 1991. http://scholar.lib.vt.edu/theses/available/etd-10102009-020211/.

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28

Eriksson, Martin, and Martin Svensson. "Handledning för VHDL-programmering i Altium Designer." Thesis, Linköpings universitet, Institutionen för teknik och naturvetenskap, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-96316.

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Vårt arbete var att skriva en handledning för att studenter och lärare snabbt ska komma igång med programmet Altium Designer 6 och utvecklingskortet som Institutionen för Teknik och Naturvetenskap (ITN) har. Utrustningen som vi använt heter Altium Designer LiveDesign Evaluation Kit. Det är ett paket bestående av ett utvecklingskort som är försett med en FPGA-krets. FPGA (Field Programmable Gated Array) är en krets innehållande logiska komponenter. Denna krets kan man programmera till olika logiska funktioner med språket VHDL. För programmering används programmet Altium Designer 6 I vår handledning finns information om utvecklingskortet, lite om hur det hårdvarubeskrivande språket VHDL är uppbyggt. Rapporten innehåller sedan steg för steg beskrivningar av hur man går till väga för att programmera och provköra enklare VHDL-exempel från programmet Altium Designer 6. Allt för att man snabbt ska få grunderna så man kan skriva egna program.
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29

BELHADJ, MOHAMMED. "Conception d'architectures en utilisant signal et vhdl." Rennes 1, 1994. http://www.theses.fr/1994REN10188.

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Ce document presente une approche pour la conception de circuits, se basant sur le langage flot de donnees synchrone signal et le langage de description de materiel vhdl. Deux aspects sont importants pour la conception d'architectures: la synthese et la verification formelle. La synthese permet d'obtenir a partir d'une description abstraite une architecture materielle par des transformations automatiques. La verification formelle, quant a elle, permet d'etablir qu'une abstraction et une mise en uvre sont conformes via-a-vis d'un certain critere. Une partie est consacree a la synthese de circuits a partir de signal, et ceci en s'appuyant sur une traduction vers vhdl qui dispose de nombreux outils de synthese. Une methode pour la synthese de circuits globalement asynchrones localement synchrones est definie. Ce type d'architecture permet d'allier les avantages des circuits synchrones et des circuits asynchrones. Dans la deuxieme partie consacree a la verification formelle, une definition d'un sous-ensemble vhdl en signal est donnee en prelude a la verification des programmes vhdl dans l'environnement signal. Un sous-ensemble synchrone de vhdl est utilise pour la verification formelle a l'aide de l'outil de preuve associe a signal
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30

Boussebha, Djamel. "Vérification temporelle de descriptions comportementales en VHDL." Montpellier 2, 1993. http://www.theses.fr/1993MON20099.

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Le travail presente dans ce memoire propose une contribution a la verification temporelle de descriptions vhdl comportementales. Notre travail a porte d'abord sur l'etude et le developpement d'un formalisme de specification permettant de decrire les contraintes temporelles caracterisant les comportements temporels des modeles vhdl. Ce formalisme de specification repose sur une logique temporelle reifiee, qui permet d'exprimer une specification comme un ensemble de faits ou evenements temporellement contraints. Nous avons ensuite mis au point une technique de preuve formelle basee sur une methodologie de verification hierarchique qui decompose le probleme de la verification en deux sous-problemes moins complexes. Le premier traite la verification des modeles proceduraux (un seul process), le second la verification des modeles declaratifs (plusieurs process). La verification procedurale se resume a prouver (d'une maniere automatique) que l'ensemble des contraintes temporelles specifiees sont satisfaites, et a detecter des violations de contraintes. La verification declarative consiste a utiliser l'information procedurale deja verifiee afin d'obtenir le comportement temporel du modele vhdl en vue de le comparer avec les specifications. Les resultats obtenus, valides sur un ensemble de descriptions vhdl, ont permis de mettre en evidence la performance du systeme et sa capacite a localiser des erreurs temporelles
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31

Музичук, Олександр Романович. "Система автоматизованого обліку людей на основі VHDL." Бакалаврська робота, Хмельницький національний університет, 2021. http://elar.khnu.km.ua/jspui/handle/123456789/10441.

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32

Slavík, Daniel. "Návrh pokročilé architektury procesoru v jazyce VHDL." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-237134.

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The goal of this project was to study pipelined processor architectures along with instruction and data cache. Chosen pipelined architecture should be designed and implemented using VHDL language. Firstly, I decided to implement the subscalar architecture first, secondly, three versions of scalar architecture. For these architectures synthesis into FPGA was done and performance of these architectures was compared on chosen algorithm. In the next part of this thesis I designed and implemented instruction and data cache logic for both architectures. However I was not able to synthetise these caches. Last chapter of this thesis deals with the superscalar architecture, which is the architecture of nowadays.
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33

Crockett, Timothy Wayne. "Board level diagnosis techniques using VHDL modeling." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/30806.

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This thesis presents a program developed to implement techniques for troubleshooting digital boards. There are old boards still in service that have no built in testing circuits. This makes troubleshooting them time consuming and difficult. In making this program two questions were posed; â How would a technician normally perform this operation?â and â How can a program help him/her do this better?â Having experience as a technician himself, the author could easily answer the first question. The experienced technician would put a known sequence of inputs into the board and compare the actual outputs to the expected. Any outputs that did not compare would lead the technician to the section of board most closely related to the fault. Within this new section, new signals are probed while the same patterns of inputs are repeated. This technique is commonly referred to as bracketing. Bracketing involves these four steps: 1.Select where to probe. 2.Run test inputs and sample. 3.Use sampled information to reduce the suspect set. 4.If the suspect set is not a single component then repeat steps 1 through 4. The answer to the second question has no easy answer. That is where it is hoped this program can help. The program uses information from a non-faulted VHDL model of the board to learn what to expect. Since there is no interface to a real probed board, VHDL is also used to model the faulted board.
Master of Science
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34

SUNDARAM, KARTHIK. "A DYNAMIC MOSFET MODEL IN VHDL-AMS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1154637877.

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35

Hymans, Charles. "Vérification de composants VHDL par interprétation abstraite." Palaiseau, Ecole polytechnique, 2004. https://pastel.archives-ouvertes.fr/pastel-00000875.

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36

Alali, Oussama. "Modélisation vhdl-ams analogique et simultion spice." Paris, ENST, 1998. http://www.theses.fr/1998ENST0006.

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La conception de système passe par la description comportementale des différentes parties (sous-systèmes) du système et de leurs intercommunications. Le langage vhdl-ams, dont la norme est en train de sortir, vient à point pour favoriser cette description et ces échanges. Le mémoire de thèse a pour objectif : 1. De présenter le passage de la simulation analogique classique à la simulation comportementale et de savoir comment transformer un simulateur électrique (spice) en simulateur comportemental. 2. De montrer par des applications avec spice dans le domaine mécatronique et par extension multi-technologique, ce que peut apporter le langage vhdl-ams. Le mémoire comprend donc deux grandes parties. Dans la première partie simulation analogique et comportementale, nous avons étudié le fonctionnement et la structure d'un simulateur électrique analogique (spice), et les grands principes (analogiques) du langage vhdl-ams en vue d'élaborer un module traducteur-interface vhdl-ams/spice. Le module, appelé bvhdla permet donc à spice de reconnaitre des modelés écrits en vhdl-ams analogique. Bvhdla est en fait plus qu'un simple compilateur, car il fournit de nouvelles données requises par spice. Par exemple il contient un dérivateur symbolique, transparent à l'utilisateur, permettant le calcul automatique des conductances et des transconductances indispensable pour spice. La seconde partie mécatronique et multi-technologie, présente tout d'abord l'avantage que la mise en pratique de l'analogie permet de tirer entre la mécanique et l'électricité/l'électronique (la mécatronique) : avantage de pouvoir utiliser un simulateur électrique pour résoudre des problèmes de mécanique. Ceci n'est certes pas nouveau, mais l'établissement de l'analogie avec d'autres domaines technologiques (thermique, radiatif,) permet d'étendre la notion de mécatronique à celle de multi-technologie. Nous montrons alors que le langage vhdl-ams arrive à point. Pour cela nous présenterons des applications rendues possibles grâce à notre outil de simulation. En plus des applications s'appuyant sur des modèles multi-technologiques, nous présenterons des modèles purement fonctionnels, et des modèles physiques de type composant. Ceci en vue de montrer ce que potentiellement on peut attendre de vhdl-ams.
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37

Pan, Bi-Yu. "Hierarchical test generation for VHDL behavioral models." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-09052009-040449/.

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38

Shrivastava, Vikram M. "Mapping conceptual graphs to primitive VHDL processes." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040536/.

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39

Xu, Zhen. "Modeling SAR signals and sensors using VHDL." Thesis, This resource online, 1995. http://scholar.lib.vt.edu/theses/available/etd-06112009-063128/.

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40

Giannopoulos, Vassilis. "Efficient VHDL models for various PLD architectures /." Online version of thesis, 1995. http://hdl.handle.net/1850/12238.

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41

Alali, Oussama. "Modélisation VHDL-AMS analogique et simulation SPICE /." Paris : École nationale supérieure des télécommunications, 1998. http://catalogue.bnf.fr/ark:/12148/cb367111244.

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42

Cebelieu, Marie-Claude Saucier Gabrièle. "Utilisation de macro blocs en synthèse VHDL." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00346055.

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43

Massoumi, Mehran Mokhtar. "Structuring VHDL synthesis using the AHPL paradigm." Diss., The University of Arizona, 1994. http://hdl.handle.net/10150/186986.

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The widespread use of VHDL for RT synthesis in the design community and the problems associated with using the language for such a purpose is the driving force behind defining this research. Although VHDL includes constructs that can be useful in design representation, it will be demonstrated that synthesis from VHDL does not produce optimum results and is not computationally efficient. A number of real design scenarios will be analyzed and the pitfalls associated with each will be highlighted. The alternative is to use a language that is designed for synthesis and yet possesses all the representation power of VHDL. AHPL (A Hardware Programming Language) will be used for this purpose. Due to the one to one correspondence between AHPL constructs and the hardware primitives, derivation of hardware from the description is a natural process. Although AHPL has proved to be a robust and effective synthesis language, it requires modest extensions so that all models described in VHDL synthesis subsets can also be described in AHPL at the same level of abstraction as VHDL. The resulting language will be referred to as Extended AHPL or XAHPL for short. A synthesis methodology and implementation using XAHPL will be presented. Moreover, the results of synthesizing XAHPL and equivalent VHDL models under the same constraints and environment will be compared. This comparison can be interpreted as a cost metric for the VHDL synthesis methodology. Lastly, since many designers are and will be using VHDL for synthesis, a subset of VHDL which carries most correspondence with XAHPL will be defined.
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44

Radetzki, Martin. "Synthesis of digital circuits from object oriented specifications." [S.l. : s.n.], 2000. http://deposit.ddb.de/cgi-bin/dokserv?idn=960906045.

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45

Carter, Grant Russel. "System level simulation of digital designs : a case study." Master's thesis, Faculty of Engineering and the Built Environment, 1998. https://hdl.handle.net/11427/31852.

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Very High Speed Integrated Circuit Hardware Description Language (VHDL) is a hardware description language that is gaining increasing popularity among digital designers in South Africa, as it is both a synthesis and simulation language. Many designers make use of the language's synthesis ability but hardly tap into the power of its simulation abilities. This dissertation primarily investigated the feasibility of VHDL simulation during the design process. Secondary goals were to document the design methodology as well as state-of-the-art of the tools required for FPGA design and simulation. As a case study, a digital preprocessor for a synthetic aperture radar (SAR) was designed and simulated. The design was targeted for an FPGA in an attempt to determine the level of complexity of algorithm that can be obtained in an FPGA. This was a hardware solution to the design requirement; a completely software solution implemented in a DSP was attempted by Yann Tremeac [19]. In July 1993, the US Department of Defence instigated a program known as Rapid Application Specific Signal-processor Prototyping (RASSP). The purpose of this program was to review the process used in creating embedded digital signal processors in an attempt to decrease the time taken to produce a prototype by a factor of four. The methods proposed by RASSP for achieving this goal included the reuse of existing modules, concurrent design and virtual prototyping. The virtual prototyping that the RASSP initiative refers to includes a process of writing VHDL models to represent the system being designed. These models are first written at an abstract level where the mathematical equations which describe the processing are tested. Test data can be input to the model which will perform the required processing. The output can then be verified to ensure that the equations are correct. At this stage, the model contains no structural information as to how the processing is achieved, nor even the numerical method used to implement the equations. The level of abstraction of these models decreases with every model that is written. Obviously the number and type of models that are written depends upon the design. An example of the models which could be written are a mathematical model and an algorithm model which models the numerical methods used in implementing the mathematical equations. A behavioural or functional model can then be written to break the system into a number of sub-components. The sub-components are modelled so that their interfaces are correct but the internals contain no information on the structure used to implement the algorithms. These models can then be further refined to include implementation details until a final design is produced. At each stage, the test data that is used in the more abstract model can still be used for verification. This system of testing requires that testbenches be written. These are simply pieces of VHDL code that can read and write data files as well as provide known stimuli to the unit under test. To investigate the feasibility of VHDL modelling, a preprocessor for the South African Synthetic Aperture Radar (SAR) was designed and modelled. This preprocessor was required to low pass filter the data received by the radar and then sub-sample it safely to reduce the data rate of the data to be stored. Three methods were considered for implementing this data reduction: Using a presurnmer, using a FIR filter or a combination of the two. The last option was chosen since it produced the highest azimuth resolution after SAR processing and it required the least number of filter taps to produce. The method required a presurnmer which summed three PRis. The FIR filter was a 32 tap filter and incorporated a "skip" factor of 4. This method did not violate any constraints set by the SAR processing regarding the sampling rate of the data, and it was feasible to implement. Since the processing was divided into the presurnmer and prefilter, it was logical that the hardware be similarly divided. One of the first design issues to be overcome was how these two entities should interact. Both required the use of external RAM to facilitate temporary data storage. The first method was to have separate memories for each entity. The presurnmer would then output a presurnmed range line to the prefilter for processing. The greatest disadvantage of this method was that the prefilter would then have to store this data in its memory before processing could take place. This was inefficient as the prefilter would have to store the data again in its memory and this would prevent it from processing during that time. The second method was the one implemented. The implementation made use of dual ported RAM. The presummer was connected to one port and the prefilter to the other. The advantage of this method was that the prefilter did not have to perform any data storage which increased the amount of time it could spend processing dat~. An algorithm model was written for the presummer and prefilter operations to verify the effects of the precision of the stored data, the filter tap weights and the mathematical validity of the process. Test data was produced and read into the model. The processed data was output and the results analysed. This data set was then used to verify the operations of the other more detailed models. The second model that was written was an abstract functional model. This modelled the interfaces of the presummer and prefilter but .contained no details of the internal implementation or timing. The abstract functional model was however able to process data and the test data which was used in the algorithm simulation was used to verify the operation of the model. A model of the RAM had to be written to allow the presummer and prefilter to store data. A functional model was written which contained no timing information but contained the full functionality of the device being modelled. Finally the presummer and prefilter descriptions were written to allow synthesis. A VHDL synthesiser was used to specify the logic required to implement the devices. FPGA design software was then used to place-and-route the logic and finally a FPGA configuration file was produced. Back-annotated VHDL source code was also produced by the FPGA design software. This was a gate level VHDL model of the device and included timing information which reflected the internal delays of the FPGA. This model was used in the test bench for the functional model since it contained the same I/O ports. The same test data was again used and the results compared to the functional simulation for verification. In conclusion, the modelling provided a method of verification that would normally only be achievable with a physical prototype. The largest problem encountered with the virtual prototyping was the simulation time of the gate level models. These would have taken up to 60 days on an Intel PII-300MHz processor with 196MB RAM to perform - longer than the time required to build and debug a physical prototype. The second problem was the availability of VHDL models. Without simulation models of all the components used, system level simulation was a pointless exercise. There are some web sites which contain a number of free models but the majority of available models are commercial and are therefore expensive. For companies starting out in the field of VHDL modelling, the cost of a VHDL simulator package can also be prohibitive. If the required models are available and software to simulate and synthesise them, the goals ofRASSP can be achieved.
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46

Gustafsson, Carl Johan. "VHDL-implementering av drivkrets för en alfanumerisk display." Thesis, Jönköping University, JTH, Computer and Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-7667.

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Allting började med att jag fick i uppdrag av Euromaint Industry i Skövde att konstruera en alfanumerisk display i syfte att ersätta en utgången display som inte längre nytillverkas. Jag fick i uppdrag att välja ut en modern, lämplig grafisk display och bygga ett interface mellan den nya displayen och den industriella maskin som displayen skall sitta på. Efter att ha letat hos någraelektronikleverantörer kom jag fram till att en TFT-skärm från det japanska företaget Kyocera var den som passade bäst. Skärmen hade ett VGA-liknandeinterface och min uppgift blev att sätta mig in i hur VGA fungerar. Efter att ha konstaterat att det krävdes en snabbare krets än en microcontroller för att använda VGA, var det endast en programmerbar logikkrets, en FPGA, som gällde. Denna FPGA sköter nu ensam om såväl VGA-interfacet som inläsningen av informationen från den industriella NC-maskinen.


Everything started when I got a task from Euromaint Industry in Skövde, Sweden, to develop an alphanumerical display that could replace an old one, which was sold out. I got a task to choose a modern, suitable, graphical display and develop an interface between the new display and the industrial machine, which the old one was connected to. I have searched for a display at some suppliers of electronic components and I have found a TFT-display from the Japanese company Kyocera. The display had an interface similar to VGA so I had to study VGA to see how it works. Then I realized that I needed a faster circuit than a microcontroller. Then I chose a programmable logic circuit, an FPGA, to control the VGA-sweep. Today the FPGA-circuit controls the whole system.

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47

Lashko, Anastasia, and Oleg Zakaznov. "VHDL Implementation of CORDIC Algorithm for Wireless LAN." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2202.

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This work is focused on the CORDIC algorithm for wireless LAN. The primary task is to create a VHDL description for CORDIC vector rotation algorithm.

The basic research has been carried out in MATLAB. The VHDL implementation of the CORDIC algorithm is based on the results obtained from the MATLAB simulation. Mentor Graphics FPGA Advantage© for Xilinx 4010XL FPGA has been used for the hardware implementation.

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48

Ek, Tobias. "GALS,Design och simulering för FPGA med VHDL." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2644.

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Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced.

GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload.

Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.

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49

Guihal, David. "Modélisation en langage VHDL-AMS des systèmes pluridisciplinaires." Phd thesis, Université Paul Sabatier - Toulouse III, 2007. http://tel.archives-ouvertes.fr/tel-00157570.

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Ce travail de thèse porte sur la problématique d'élaboration de modèles de systèmes hétérogènes. Il a associé le laboratoire de recherche LAAS-CNRS et la société MENTOR GRAPHICS. Il prend place au sein d'un processus de conception qui se fonde sur les recommandations de l'EIA-632 et sur une ingénierie guidée par les modèles. L'objectif de notre travail est de montrer en quoi le langage VHDL-AMS est adapté à la problématique de modélisation et de simulation de la solution physique au sens des recommandations de l'EIA-632. Dans un premier temps, ce manuscrit présente un état de l'art sur les besoins en modélisation pour la conception système, et dresse un bilan sur les différents langages de modélisation susceptibles d'y répondre. Afin de proposer la norme VHDL-AMS (IEEE 1076.1-1999) comme solution, notre travail s'est attaché à présenter et proposer une méthode à mettre en oeuvre pour converger vers cette norme. Notre démarche s'appuie sur l'ingénierie guidée par les modèles avec une place prépondérante jouée par les transformations de modèle. Nous avons développé ce concept de transformation en vue d'une convergence vers le VHDL-AMS : nous développons la notion de meta modèle avec, entre autre, la création d'un meta modèle du langage VHDL-AMS. Celui-ci va permettre une vérification de la conformité des modèles créés, mais aussi l'écriture de règles de transformations au niveau meta modèle. L'intérêt des industriels possédant un existant de modèles écrits dans un langage de description de matériel propriétaire autre (par exemple le langage MAST) en vue d'une migration vers la norme VHDL-AMS, nous a permis d'éprouver cette méthodologie dans de nombreux cas concrets. Nous avons aussi comparé cette approche à une méthodologie que nous avions précédemment définie, nécessitant une expertise dans les deux langages source et cible. Cela nous a permis de conclure positivement sur la faisabilité d'une telle transformation avec une semi-automatisation et une expertise encore n écessaire à certaines étapes. A titre de démonstration, nous avons développé de nombreux modèles mixtes confirmant les aptitudes du VHDL-AMS à pouvoir être le support principal du prototypage virtuel, ainsi que la validité de notre méthode de transformation. Nous avons notamment réalisé la modélisation VHDL-AMS d'un système très hétérogène de mise à feu d'une charge pyrotechnique, qui valide notre méthodologie. La validation des modèles en conformité avec les spécifications est une des perspectives identifiées de nos travaux, à approfondir.
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50

Aklys, Andrius. "UML aprašų transformacijos į srities kalbą (VHDL,SystemC)." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2006. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2006~D_20060605_200924-56976.

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To increase the productivity of electronic systems design we offer to use UML – the standard specification language of high level systems. The higher level of abstraction and automatic design methods could decrease a gap of hardware design. We offer to use UML class diagrams for the specification of electronic systems structure and UML state diagrams to specify the behavior of electronic systems. We introduce metamodels which describe mapping between UML class and state diagrams and hardware description languages (VHDL, SystemC), as the possible realization of ideas we introduced earlier. Also we provide code generator which translates notations of UML class and state diagrams to VHDL and SystemC languages.
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