Relevant bibliographies by topics / VHDL

Academic literature on the topic 'VHDL'

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Published: 4 June 2021
Last updated: 25 July 2024

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Journal articles on the topic "VHDL"

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Swamy, S., A. Molin, and B. Covnot. "OO-VHDL. Object-oriented extensions to VHDL." Computer 28, no. 10 (1995): 18–26. http://dx.doi.org/10.1109/2.467587.

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Dewey, Allen, and Anthony Gadient. "VHDL Motivation." IEEE Design & Test of Computers 3, no. 2 (1986): 12–16. http://dx.doi.org/10.1109/mdt.1986.294898.

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Nash, J. D., and L. F. Saunders. "VHDL Critique." IEEE Design & Test of Computers 3, no. 2 (1986): 54–65. http://dx.doi.org/10.1109/mdt.1986.294917.

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Ashenden, P. J. "VHDL standards." IEEE Design & Test of Computers 18, no. 5 (2001): 122–23. http://dx.doi.org/10.1109/54.953280.

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Helbig, J., R. Schlör, W. Damm, G. Döhmen, and P. Kelb. "VHDL/S — integrating statecharts, timing diagrams, and VHDL." Microprocessing and Microprogramming 38, no. 1-5 (September 1993): 571–80. http://dx.doi.org/10.1016/0165-6074(93)90197-s.

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Varga, László, Gábor Hosszú, and Ferenc Kovács. "Design Procedure Based on VHDL Language Transformations." VLSI Design 14, no. 4 (January 1, 2002): 349–54. http://dx.doi.org/10.1080/10655140290011159.

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One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstract VHDL model and produces an RTL VHDL description through successive language transformations while preserving the VHDL standard simulation semantics. The steps of the synthesis do not use graph representation or other meta-language, but apply the standard VHDL only. This VHDL representation is simulatable and accessible, functional verification can be performed by simulation at any time, and the simulation results can be used to guide the synthesis process. The output VHDL format is suitable to continue the design flow with RTL based synthesis tools.
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Lipsett, Roger, Erich Marschner, and Moe Shahdad. "VHDL - The Language." IEEE Design & Test of Computers 3, no. 2 (April 1986): 28–41. http://dx.doi.org/10.1109/mdt.1986.294900.

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Hands, J. P. "What is VHDL?" Computer-Aided Design 22, no. 4 (May 1990): 246–49. http://dx.doi.org/10.1016/0010-4485(90)90054-g.

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Nagler, James J., and David R. Idler. "Ovarian uptake of vitellogenin and another very high density lipoprotein in winter flounder (Pseudopleuronectes americanus) and their relationship with yolk proteins." Biochemistry and Cell Biology 68, no. 1 (January 1, 1990): 330–35. http://dx.doi.org/10.1139/o90-045.

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Ultracentrifugation analysis of female winter flounder plasma confirmed that in addition to vitellogenin another different lipoprotein is found as very high density lipoprotein (VHDL). Accordingly this protein (formerly known as peak A protein) has been named VHDL II, with respect to vitellogenin which we designate VHDL I. Both these proteins were shown to be taken up in vivo by the ovary of vitellogenic females. Based on total mass, vitellogenin and VHDL II could potentially contribute in similar amounts to yolk protein accumulated by developing oocytes. Sodium dodecyl sulfate – polyacrylamide gel electrophoresis of vitellogenic oocyte yolk proteins revealed five major protein subunits of 101.4, 94.4, 68.7, 25.5, and 22.5 kilodaltons (kDa). Western blots of these yolk protein subunits established three of them (104.4, 94.4, and 22.5 kDa) as originating from vitellogenin. Similar Western blots utilizing a VHDL II antisera identified the 68.7-kDa yolk protein subunit as arising from incorporated serum VHDL II.Key words: VHDL II, vitellogenin, oocyte yolk proteins, in vivo uptake, Western blot.
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Dickinson, Brian. "VHDL '92: The new features of the VHDL hardware description language." Microprocessors and Microsystems 19, no. 2 (January 1995): 106–7. http://dx.doi.org/10.1016/0141-9331(95)90002-0.

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Dissertations / Theses on the topic "VHDL"

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Shu, Shin-Ming. "EPLD modeling with VHDL." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/25899.

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Hicks, William T., and Robert E. Yantorno. "CVSD MODULATOR USING VHDL." International Foundation for Telemetering, 2004. http://hdl.handle.net/10150/605317.

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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California
IRIG-106 Chapter 5 describes a method for encoding voice using a simple circuit to reduce the overall bit rate and still achieve good quality voice. This well described Continuously Variable Slope Delta Modulation (CVSD) circuit can be obtained using analog parts. A more stable implementation of CVSD can be obtained by designing an anti-aliasing input filter, an A/D converter, and logic. This paper describes one implementation of the CVSD using a standard A/D converter and logic.
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BAPAT, SACHIN VASUDEO. "THE PERFORMANCE EVALUATION OF VHDL-AMS SIMULATORS BY CREATING LARGE, SCALABLE VHDL-AMS MODELS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1032179532.

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Tong, Yanhui. "VHDL implementation of turbo codec." Thesis, University of Ottawa (Canada), 2003. http://hdl.handle.net/10393/26405.

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Turbo coding is one of the most significant achievements in coding theory during the last decade. It has been shown in the literature that transmission systems employing turbo codes could achieve a performance close to the Shannon limit. Turbo decoding is the major contributor to the overall complexity of turbo coding. Therefore, the challenge is to implement turbo coding in various communications systems at affordable decoding complexity using current VLSI technology. Four different turbo decoding algorithms were investigated in this thesis. Comparisons on both their performances and implementation complexities were performed. Log-MAP based turbo decoding offers the best compromise among the different turbo decoding algorithms. A Register-Transfer-Level (RTL) fixed-point turbo decoder model based on Log-MAP algorithm was designed and simulated using VHDL as the hardware description language. The RTL model was verified by comparing its simulation results with those obtained from a behavioral model of the same turbo decoder written in C language.
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Ardeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.

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Sprunger, Steven J. "UML modeling for VHDL designs." Virtual Press, 2008. http://liblink.bsu.edu/uhtbin/catkey/1399192.

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Unified Modeling Language (UML) allows software engineers to use a standard way of expressing a design approach at a high level. The benefits of system modeling are well accepted in the software development community. Modeling of Very High Speed Integrated Circuit Hardware Description Language (VHDL) designs, for synthesizing into hardware, is a common practice also. The research herein looks at system modeling of a design using UML, in which there are both software and hardware components. The idea is to explore modeling of the system with the ability to abstract whether the implementation of a particular function is realized in software or hardware. The designer can then model/evaluate a given system design approach and later allocate functions to software and hardware, as appropriate to meet constraints such as performance, cost, schedule. Since using UML for software is a standard approach, this research investigates the UML to hardware path via VHDL.
Department of Computer Science
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Mecera, Martin. "Transformace jazyka C do VHDL." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-237149.

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The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.
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Novotný, Jaroslav. "Návrh vícejádrového procesoru ve VHDL." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-235548.

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The objective of the thesis is to design and implement in the VHDL language a simple multiprocessor supporting parallel computing. Furthemore, the author has designed and realized universal transparent generic interconnection layer with the objective to connect any given number of processor cores to shared address space using arbitrated bus. Parametrized cache has been allocated to each core in the layer. MSI protocol was used to deal with the issue of memory coherence of the implemented system. Direct and indirect synchornisation support is available to the user. In order to verify the functionality of the system, simple processor core has been designed and implemented, and its copies were connected to the interconnection layer. Various testing programmes have been used to verify the functionality of the system, which also confirmed that the acceleration of computing has been achieved successfully. Virtex6 chip has been used to test the whole system.
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CHACKO, BABU. "A VHDL-AMS BSIM4.1 MODEL." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1206121503.

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Ailes, John W. Lee Chin-Hwa. "Automated digital hardware synthesis using VHDL." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School; Available from the National Technical Information Service, 1991. http://handle.dtic.mil/100.2/ADA246976.

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Books on the topic "VHDL"

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Perry, Douglas L. VHDL. New York: McGraw-Hill, 1991.

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Perry, Douglas L. VHDL. 2nd ed. New York: McGraw-Hill, 1995.

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VHDL. 3rd ed. New York: McGraw-Hill, 1998.

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Perry, Douglas L. VHDL. New York: McGraw-Hill, 2007.

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Perry, Douglas L. VHDL. New York: McGraw-Hill, 1991.

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Alain, Vachoux, ed. Analog VHDL. Boston, MA: Springer US, 1998.

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Rosinski, Andrzej T., and Alain Vachoux, eds. Analog VHDL. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5753-1.

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Bergé, Jean-Michel, Alain Fonkoua, Serge Maginot, and Jacques Rouillard. VHDL ’92. Boston, MA: Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3246-0.

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T, Rosinski Andrzej, and Vachoux Alain, eds. Analog VHDL. Boston: Kluwer Academic Publishers, 1998.

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Jean-Michel, Bergé, ed. VHDL '92. Boston: Kluwer Academic Publishers, 1993.

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Book chapters on the topic "VHDL"

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Fricke, Klaus. "VHDL." In Digitaltechnik, 219–32. Wiesbaden: Vieweg+Teubner Verlag, 2005. http://dx.doi.org/10.1007/978-3-322-94253-1_15.

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Fricke, Klaus. "VHDL." In Digitaltechnik, 219–32. Wiesbaden: Vieweg+Teubner, 2009. http://dx.doi.org/10.1007/978-3-8348-9370-3_15.

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Schildt, Gerhard H., Alexander Redlein, and Daniela Kahn. "VHDL." In Springers Lehrbücher der Informatik, 67–77. Vienna: Springer Vienna, 2003. http://dx.doi.org/10.1007/978-3-7091-3750-5_3.

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Eles, Petru, Krzysztof Kuchcinski, and Zebo Peng. "VHDL." In System Synthesis with VHDL, 21–62. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2789-0_2.

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Fricke, Klaus. "VHDL." In Digitaltechnik, 217–30. Wiesbaden: Springer Fachmedien Wiesbaden, 2018. http://dx.doi.org/10.1007/978-3-658-21066-3_15.

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Tlelo-Cuautle, Esteban, José de Jesús Rangel-Magdaleno, and Luis Gerardo De la Fraga. "VHDL." In Engineering Applications of FPGAs, 33–60. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-34115-6_2.

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Fricke, Klaus. "VHDL." In Digitaltechnik, 219–32. Wiesbaden: Springer Fachmedien Wiesbaden, 2014. http://dx.doi.org/10.1007/978-3-8348-2213-0_15.

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Edwards, Stephen A. "VHDL." In Languages for Digital Embedded Systems, 55–77. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4325-1_4.

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Fricke, Klaus. "VHDL." In Digitaltechnik, 218–31. Wiesbaden: Springer Fachmedien Wiesbaden, 2021. http://dx.doi.org/10.1007/978-3-658-32537-4_15.

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Fricke, Klaus. "VHDL." In Digitaltechnik, 215–28. Wiesbaden: Springer Fachmedien Wiesbaden, 2023. http://dx.doi.org/10.1007/978-3-658-40210-5_15.

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Conference papers on the topic "VHDL"

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Kiamilev, F., Dau-Tsuong Lu, J. Fan, S. Esener, and S. H. Lee. "VHDL for simulation of optoelectronic computers." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.fj7.

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VHSIC Hardware Description Language (VHDL) is a standard language for modelling electronic hardware. To evaluate the application of VHDL to optoelectronic computers, we simulate the programmable optoelectronic multiprocessor (POEM) architecture in VHDL. POEM is an architecture in which processing elements are interconnected with reconfigurable free-space optical interconnections. We use VHDL to simulate the POEM prototype, develop the next-generation POEM system, and design and test new parallel algorithms that exploit unique features of optoelectronic technology. We discuss our experience in the application of VHDL to the modeling of optoelectronic systems.
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Breuer, P. T., N. Martinez Madrid, J. P. Bowen, R. France, M. Lorrondo Petrie, and C. Delgado Kloos. "Reasoning about VHDL and VHDL-AMS using denotational semantics." In the conference. New York, New York, USA: ACM Press, 1999. http://dx.doi.org/10.1145/307418.307519.

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Sezer, S. "VHDL package GUI." In IEE Seminar on Intellectual Property. IEE, 2000. http://dx.doi.org/10.1049/ic:20000410.

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Badimon, J., L. Bodimon, and V. Fuster. "HIGH AND VERY HIGH DENSITY LIPOPROTEINS ADMINISTRATION INHIBITS PROGRESSION OF EXPERIMENTAL ATHEROSCLEROSIS IN THE RABBIT." In XIth International Congress on Thrombosis and Haemostasis. Schattauer GmbH, 1987. http://dx.doi.org/10.1055/s-0038-1643748.

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Epidemiologic studies have shown an inverse relationship between HDL and coronary artery disease. We have previously demonstrated that in vivo administration of HDL-VHDL inhibits thedevelopment of atherosclerosis in cholesterol (cho)-fed rabbits. In the present study we have analyzed whether high levels of the physiological cholesterol acceptor, homologous HDL-VHDL,could inhibit the progression of established atherosclerotic lesions. Atherosclerosis was induced by feeding rabbits a 0.5% cho-rich diet for 2 months (140g/day). At that moment, a subgroup of animal (N=4) was sacrificed and their aortas showed 30 ± 8% of aortic atherosclerotic involvement. The remaining animals, kept on the same atherogenic diet, were randomly divided in two identical groups (N=7): a control and a treated group administered with 50 mg of HDL-VHDL a week for 4 weeks. HDL-VHDL fraction wasisolated from normal rabbit plasma byultracentrifugation at a density range of 1.063-1.25g/ml. The amount of HDL-VHDL administered was determined byits protein content according to Lowry"s technique. The 50mg of HDL-VHDL, measured as protein, contained1.4mg of total cholesterol, 1.43mg oftriglycerides and 0.6mg of phospholipids. At sacrifice, the treated group showed a marked decrease on the extent of aortic by fatty streaks (20 ± 6%X ± 1SE) as compared to(36% + 6) inthe control group (p < 0.05). Similar results were obtained in aortic wall lipid accumulation (See table, results expressed as X±1SEM; rag/gr dry aorta.)In conclusion, administration of HDL-VHDL induced a marked inhibition on the progression of atherosclerosis in cholesterol-fed rabbits.
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Bailey, Julian A., Peter R. Wilson, Andrew D. Brown, and John Chad. "Behavioral simulation of biological neuron systems using VHDL and VHDL-AMS." In 2007 IEEE International Behavioral Modeling and Simulation Workshop. IEEE, 2007. http://dx.doi.org/10.1109/bmas.2007.4437543.

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Macko, D., and K. Jelemenska. "VHDL structural model visualization." In IEEE EUROCON 2011 - International Conference on Computer as a Tool. IEEE, 2011. http://dx.doi.org/10.1109/eurocon.2011.5929348.

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Giumale, Cristian A., and Hilary J. Kahn. "Information models of VHDL." In the 32nd ACM/IEEE conference. New York, New York, USA: ACM Press, 1995. http://dx.doi.org/10.1145/217474.217610.

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Berdychowski, Piotr P., and Wojciech M. Zabolotny. "C to VHDL compiler." In Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010, edited by Ryszard S. Romaniuk. SPIE, 2010. http://dx.doi.org/10.1117/12.872194.

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Cristian A Giumale. "Information Models of VHDL." In 32nd Design Automation Conference. ACM, 1995. http://dx.doi.org/10.1109/dac.1995.250051.

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Armstrong, James, Chang Cho, Sandeep Shah, and Chakravarthy Kosaraju. "The VHDL validation suite." In Conference proceedings. New York, New York, USA: ACM Press, 1990. http://dx.doi.org/10.1145/123186.123190.

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Reports on the topic "VHDL"

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Cooper, Keith D., John Bennett, and Linda Torczon. Optimizing VHDL Intermediate Forms. Fort Belvoir, VA: Defense Technical Information Center, March 2001. http://dx.doi.org/10.21236/ada387386.

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Nassif, Michael P., and Mark T. Pronobis. VHDL Model Verification and Acceptance Procedure,. Fort Belvoir, VA: Defense Technical Information Center, December 1995. http://dx.doi.org/10.21236/ada304607.

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Drager, Steven, Christopher Flynn, Frederick Hall, James Hanna, and Robert Hillman. Waves-VHDL Integration for Common Applications. Fort Belvoir, VA: Defense Technical Information Center, February 1996. http://dx.doi.org/10.21236/ada309491.

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Aylor, James, Robert Klenke, Ron Waxman, Paul Menchini, Jack Stinson, and Bill Anderson. VHSIC Hardware Description Language (VHDL) 200X Requirements Report/Survey. Fort Belvoir, VA: Defense Technical Information Center, November 1999. http://dx.doi.org/10.21236/ada406178.

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Palanisamy, Karthikeyan. High Level Preprocessor of a VHDL-based Design System. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6660.

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Serafino, Karen M., and Michael A. Dukes. VHDL and Waves Descriptions for a Pseudo-Random Pattern Generator. Fort Belvoir, VA: Defense Technical Information Center, January 1992. http://dx.doi.org/10.21236/ada247891.

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Chawla, Praveen, Herbert L. Hirsch, Philip A. Wilsey, and Jeffrey Carter. Standard Analyzer of VHDL Applications for Next Generation Technology (SAVANT). Fort Belvoir, VA: Defense Technical Information Center, April 1995. http://dx.doi.org/10.21236/ada295547.

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Johnson, Barry W., D. T. Smith, and Todd A. DeLong. VHDL Fault Simulation and Automatic Test Pattern Generation Requirements Document. Fort Belvoir, VA: Defense Technical Information Center, January 1996. http://dx.doi.org/10.21236/ada304358.

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Paragi, Robert J., Michael P. Nassif, and Edward P. Stabler. Evaluation of the Larch/VHDL Interactive Prover in Hardware Verification. Fort Belvoir, VA: Defense Technical Information Center, October 1997. http://dx.doi.org/10.21236/ada337948.

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SCHROEPPEL, RICHARD C., CHERYL L. BEAVER, TIMOTHY J. DRAELOS, RITA A. GONZALES, and RUSSELL D. MILLER. A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip. Office of Scientific and Technical Information (OSTI), September 2002. http://dx.doi.org/10.2172/802030.

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