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Journal articles on the topic 'Verification'

To see the other types of publications on this topic, follow the link: Verification.

Author: Grafiati

Published: 4 June 2021

Last updated: 14 September 2024

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1

Benoit, Anne, Saurabh K. Raina, and Yves Robert. "Efficient checkpoint/verification patterns." International Journal of High Performance Computing Applications 31, no. 1 (July 28, 2016): 52–65. http://dx.doi.org/10.1177/1094342015594531.

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Errors have become a critical problem for high-performance computing. Checkpointing protocols are often used for error recovery after fail-stop failures. However, silent errors cannot be ignored, and their peculiarity is that such errors are identified only when the corrupted data is activated. To cope with silent errors, we need a verification mechanism to check whether the application state is correct. Checkpoints should be supplemented with verifications to detect silent errors. When a verification is successful, only the last checkpoint needs to be kept in memory because it is known to be correct. In this paper, we analytically determine the best balance of verifications and checkpoints so as to optimize platform throughput. We introduce a balanced algorithm using a pattern with p checkpoints and q verifications, which regularly interleaves both checkpoints and verifications across same-size computational chunks. We show how to compute the waste of an arbitrary pattern, and we prove that the balanced algorithm is optimal when the platform MTBF (mean time between failures) is large in front of the other parameters (checkpointing, verification and recovery costs). We conduct several simulations to show the gain achieved by this balanced algorithm for well-chosen values of p and q, compared with the base algorithm that always perform a verification just before taking a checkpoint ( p = q = 1), and we exhibit gains of up to 19%.

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2

Shaik, Bushra, Jyothi Manohar Katikireddy, Vamsidhar Kambham, and K. Sravani. "Offline Signature Verification Using Image Processing." E3S Web of Conferences 391 (2023): 01074. http://dx.doi.org/10.1051/e3sconf/202339101074.

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A person’s signature is merely a handwritten sign that closely resembles his/her name, frequently stylized and distinctive, and that expresses the person’s identity, intent, and consent. Two types of verifications are present. They are online signature verification and offline signature verification. Generally, Offline Signature verification is less efficient and slower process compare to online verification when come to the situation having larger number of documents and files to verify with in less time. Over the years, many researchers have developed so many methods for signature verifications to help the people or organizations to find whether the signature of a particular person is forged or genuine. To overcome this problems; In this paper we introduced a simple method to improve the verification of the signature in Image Processing using Convolution Neural Networks(CNN). Signature Verification it is used to authenticate various kinds of documents, including cheques, draughts, certificates, approvals, letters, and other legal ones, such verification is crucial for preventing document forgery and falsification. Previously, to verify a signature, it was manually checked against copies of real signatures. This straightforward approach might not be sufficient given that forgery and signature fraud techniques are becoming more sophisticated as a result of improving technology.

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3

Deboo, Cyrus, Shubham Kshatriya, and Rajat Bhat. "Video Liveness Verification." International Journal of Trend in Scientific Research and Development Volume-2, Issue-3 (April 30, 2018): 2449–52. http://dx.doi.org/10.31142/ijtsrd12772.

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4

Pucella, Riccardo. "Logical verification and equational verification." ACM SIGACT News 36, no. 2 (June 2005): 77–88. http://dx.doi.org/10.1145/1067309.1067326.

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5

Regehr, John, and Nathan Cooprider. "Interrupt Verification via Thread Verification." Electronic Notes in Theoretical Computer Science 174, no. 9 (June 2007): 139–50. http://dx.doi.org/10.1016/j.entcs.2007.04.002.

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6

Simonova, Natalia S. "An International Veriﬁ cation Institute as an Element of the Mechanism of Ensuring for Meeting Commitments under International Treaties." Moscow Journal of International Law, no. 1 (March 30, 2014): 82–102. http://dx.doi.org/10.24833/0869-0049-2014-1-82-102.

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The article deals with the explanation of an international verification’s nature as a specific type of international legal relationship. An author critically analyses domestic and foreign doctrines as well as the international treaties’ practice concerning the issues of international verification. An international verification institute is quite well-searched in the international law science. But the article author considers that traditional approaches to analysis of the international verification essence (investigation of subjects, matters and aims) are not sufficient. Practical value of this article flows from the new vision of the international verification as a specific international legal relationship. The legal matter, subjects and substance of the international verification are suggested to be searched in the article.

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7

Jiang, Long Long, and Dai Ping Li. "Using Contour Marking Bytecode Verification Algorithm on the Java Card." Applied Mechanics and Materials 556-562 (May 2014): 4120–23. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.4120.

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Java bytecode verification could not be well performed in the smart card due to the resource usage especially in the resource-constrained devices. Currently, on the card there are several bytecode verifications which exist kinds of problems, in order to be better and be better adapt to the environment, such as a smart card platform, raised using the contour subroutine labeled bytecode verification algorithm on a card. First, through the analysis of existing card byte code verification algorithm to determine the imperfections and difficulties in the judgment and the verification of subroutine, and then propose a method for marking the subroutine in the place of the jump to it. Thus not only get the program structure and enhance the effectiveness and efficiency of the validation. The feasibility of the method is demonstrated by simulating typical examples verification.

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8

Phelps, Doug. "Verification." Cataloging & Classification Quarterly 9, no. 1 (December 19, 1988): 5–9. http://dx.doi.org/10.1300/j104v09n01_02.

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9

Robb, Jonathan Peter. "Verification." AJN, American Journal of Nursing 117, no. 6 (June 2017): 72. http://dx.doi.org/10.1097/01.naj.0000520263.18448.55.

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10

Classen, Julie. "Verification." Nursing Management (Springhouse) 40, no. 8 (August 2009): 8. http://dx.doi.org/10.1097/01.numa.0000359199.37081.f7.

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11

Kassirer, Jerome P., and Richard I. Kopelman. "Verification." Hospital Practice 24, no. 1 (January 15, 1989): 21–30. http://dx.doi.org/10.1080/21548331.1989.11703639.

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12

Kwiatkowska, Marta. "From software verification to ‘everyware’ verification." Computer Science - Research and Development 28, no. 4 (September 7, 2013): 295–310. http://dx.doi.org/10.1007/s00450-013-0249-1.

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13

Das, Rajat Suvra, and Arjun Pal Chowdhury. "Enhancing Semiconductor Functional Verification with Deep Learning with Innovation and Challenges." International Journal of Computing and Engineering 5, no. 3 (April 19, 2024): 22–32. http://dx.doi.org/10.47941/ijce.1814.

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Purpose: Universally, the semiconductor is the foundation of electronic technology used in an extensive range of applications such as computers, televisions, smartphones, etc. It is utilized to create ICs (Integrated Circuits), one of the vital electronic device components. The Functional verification of semiconductors is significant to analyze the correctness of an IC for appropriate applications. Besides, Functional verification supports the manufacturers in various factors such as quality assurance, performance optimization, etc. Traditionally, semiconductor Functional verification is carried out manually with the support of expertise. However, it is prone to human error, inaccurate, expensive and time-consuming. To resolve the problem, DL (Deep Learning) based technologies have revolutionized the functional verification of semiconductor device. The utilization of various DL algorithms automates the semiconductor Functional verification to improve the semiconductor quality and performance. Therefore, the focus of this study is to explore the advancements in the functional verification process within the semiconductor industry. Methodology: It begins by examining research techniques used to analyse existing studies on semiconductors. Additionally, it highlights the manual limitations of semiconductor functional verification and the need for DL-based solutions. Findings: The study also identifies and discusses the challenges of integrating DL into semiconductor functional verification. Furthermore, it outlines future directions to improve the effectiveness of semiconductor functional verification and support research efforts in this area. The analysis reveals that there is a limited amount of research on deep learning-based functional verification, which necessitates further enhancement to improve the efficiency of functional verification. Unique contribution to theory, policy and practice: The presented review is intended to support the research in enhancing the efficiency of the semiconductor functional verification. Furthermore, it is envisioned to assist the semiconductor manufacturers in the field of functional verification regarding efficient verifications, yield enhancement, improved accuracy, etc.

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14

Roache, Patrick J. "Code Verification by the Method of Manufactured Solutions." Journal of Fluids Engineering 124, no. 1 (November 12, 2001): 4–10. http://dx.doi.org/10.1115/1.1436090.

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Verification of Calculations involves error estimation, whereas Verification of Codes involves error evaluation, from known benchmark solutions. The best benchmarks are exact analytical solutions with sufficiently complex solution structure; they need not be realistic since Verification is a purely mathematical exercise. The Method of Manufactured Solutions (MMS) provides a straightforward and quite general procedure for generating such solutions. For complex codes, the method utilizes Symbolic Manipulation, but here it is illustrated with simple examples. When used with systematic grid refinement studies, which are remarkably sensitive, MMS produces strong Code Verifications with a theorem-like quality and a clearly defined completion point.

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15

Fuller, David L., B. Ravikumar, and Yuzhe Zhang. "Unemployment Insurance Fraud and Optimal Monitoring." American Economic Journal: Macroeconomics 7, no. 2 (April 1, 2015): 249–90. http://dx.doi.org/10.1257/mac.20130255.

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An important incentive problem for the design of unemployment insurance is the fraudulent collection of unemployment benefits by workers who are gainfully employed. We show how to efficiently use a combination of tax/subsidy and monitoring to prevent such fraud. The optimal policy monitors the unemployed at fixed intervals. Employment tax is nonmonotonic: it increases between verifications but decreases after a verification. Unemployment benefits are relatively flat between verifications but decrease sharply after a verification. Our quantitative analysis suggests that the optimal monitoring cost is 60 percent of the cost in the current US system. (JEL D82, H24, J64, J65)

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16

Sangargir, Maryam, and Joël Brose. "Safety Verification Procedure in the Implementation of Alternative Equipment Maintenance at The Ottawa Hospital." Journal of Clinical Engineering 49, no. 3 (July 2024): 108–13. http://dx.doi.org/10.1097/jce.0000000000000657.

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This article explores safety verifications in The Ottawa Hospital’s alternative Equipment Management (AEM) project, focusing on optimizing resource use and maintaining patient safety. This methodology includes integrating World Health Organization guidelines, establishing a dedicated AEM Committee, and a safety verification process using failure codes. The article consists of a case study on The Ottawa Hospital Civic Campus Floor Scales to further illustrate the AEM safety verification process.

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17

Jadhav, Angarika, and Prof N. M. Shahane. "Privacy Preserving Biometric Verification." International Journal of Engineering Research 3, no. 1 (January 1, 2014): 6–8. http://dx.doi.org/10.17950/ijer/v3s1/102.

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18

Chary, V. Vishnu Vardhan, and Ch Sandeep Ch.Sandeep. "Robust Offline Signature Verification." International Journal of Scientific Research 2, no. 12 (June 1, 2012): 93–95. http://dx.doi.org/10.15373/22778179/dec2013/30.

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19

Yamada, Chikatoshi, Yasunori Nagata, and Zensho Nakao. "An Efficient Specification for System Verification." Journal of Advanced Computational Intelligence and Intelligent Informatics 10, no. 6 (November 20, 2006): 931–38. http://dx.doi.org/10.20965/jaciii.2006.p0931.

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In design of complex and large scale systems, system verification has played an important role. In this article, we focus on specification process of model checking in system verifications. Modeled systems are in general specified by temporal formulas of computation tree logic, and users must know well about temporal specification because the specification might be complex. We propose a method by which specifications with temporal formulas are obtained inductively. We will show verification results using the proposed temporal formula specification method, and show that amount of memory, OBDD nodes, and execution time are reduced.

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20

Yim, Joon-Seo, Chang-Jae Park, In-Cheol Park, and Chong-Min Kyung. "Design Verification of Complex Microprocessors." Journal of Circuits, Systems and Computers 07, no. 04 (August 1997): 301–18. http://dx.doi.org/10.1142/s021812669700022x.

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As the complexity of microprocessors increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for compatible microprocessor designs. To guarantee perfect compatibility with previous microprocessors, we developed three C models in different abstraction levels, i.e. Polaris, MCV and StreC. An instruction behavioral level C model (Polaris) is verified using the slowed-down PC. In the implemetation of micro-architecture, a micro-operational level model (MCV) and RTL model (StreC) are co-simulated with consistency checking between these two models. The simulation speed of C models makes it possible to test the "real-world" application programs on the RTL design with a software board model (VPC). To increase the confidence level of verifications, Profiler reports the verification coverage of the test program, which is fed-back to the automatic test program generator (Pandora). The Restartability feature also helps to significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified the HK486, an Intel 80486 pin-compatible microprocessor successfully.

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21

Dong, Zhijiang, Yujian Fu, and Yue Fu. "Runtime Verification on Robotics Systems." International Journal of Robotics Applications and Technologies 3, no. 1 (January 2015): 23–40. http://dx.doi.org/10.4018/ijrat.2015010102.

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Runtime verification is a technique for generating monitors from formal specification of expected behaviors for the underlying system. It can be applied to automatically evaluate system execution, either on-line or off-line, analyzing extracted execution traces; or it can be used online during operation, potentially steering the application back to a safety region if a property is violated. As a so-called light-weighted formal method, runtime verification bridges the gap between system design and implementation and shorten the distance of software quality assurance between the software testing and model checking and theorem proving. Runtime verification is considered as a highly scalable and automatic technique. Most of current runtime verification research are endeavored on the program context, in other words, on the program side and falls in the implementation level. These applications limited the benefits of runtime verification that bridges the gap among types of applications. With the proliferation of embedded systems and mobile device, dynamically verifying the firmware and mobile apps becomes a new emerging area. Due to the characteristics of runtime verification technique and limitations of the robotics systems, so far, very few research and project are located in the runtime verification on the firmware of embedded systems, which appear in most of robotics systems. Robotics systems are programmed on the firmware and only observed on device. In this paper, the authors first discussed the current runtime verifications on the embedded systems with limitations. After that, a layered runtime verification framework will be presented for the firmware verification. The case study is applied on the commonly recognized educational toolkit – LEGO Mindstorm robotics systems.

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22

Rangi, Anshuka, Long Tran-Thanh, Haifeng Xu, and Massimo Franceschetti. "Saving Stochastic Bandits from Poisoning Attacks via Limited Data Verification." Proceedings of the AAAI Conference on Artificial Intelligence 36, no. 7 (June 28, 2022): 8054–61. http://dx.doi.org/10.1609/aaai.v36i7.20777.

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This paper studies bandit algorithms under data poisoning attacks in a bounded reward setting. We consider a strong attacker model in which the attacker can observe both the selected actions and their corresponding rewards, and can contaminate the rewards with additive noise. We show that any bandit algorithm with regret O(log T) can be forced to suffer a regret O(T) with an expected amount of contamination O(log T). This amount of contamination is also necessary, as we prove that there exists an O(log T) regret bandit algorithm, specifically the classical UCB, that requires Omega(log T) amount of contamination to suffer regret Omega(T). To combat such poisoning attacks, our second main contribution is to propose verification based mechanisms, which use limited verification to access a limited number of uncontaminated rewards. In particular, for the case of unlimited verifications, we show that with O(log T) expected number of verifications, a simple modified version of the Explore-then-Commit type bandit algorithm can restore the order optimal O(log T) regret irrespective of the amount of contamination used by the attacker. We also provide a UCB-like verification scheme, called Secure-UCB, that also enjoys full recovery from any attacks, also with O(log T) expected number of verifications. To derive a matching lower bound on the number of verifications, we also prove that for any order-optimal bandit algorithm, this number of verifications O(log T) is necessary to recover the order-optimal regret. On the other hand, when the number of verifications is bounded above by a budget B, we propose a novel algorithm, Secure-BARBAR, which provably achieves O(min(C,T/sqrt(B))) regret with high probability against weak attackers (i.e., attackers who have to place the contamination before seeing the actual pulls of the bandit algorithm), where C is the total amount of contamination by the attacker, which breaks the known Omega(C) lower bound of the non-verified setting if C is large.

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23

Najeeb, Shaima Miqdad Mohamed, Raid Rafi Omar Al-Nima, and Mohand Lokman Ahmad Al-Dabag. "Reinforced Deep Learning for Verifying Finger Veins." International Journal of Online and Biomedical Engineering (iJOE) 17, no. 07 (July 2, 2021): 19. http://dx.doi.org/10.3991/ijoe.v17i07.24655.

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Recently, personal verifications become crucial demands for providing securities in personal accounts and financial activities. This paper suggests a new Deep Learning (DL) model called the Re-enforced Deep Learning (RDL). This approach provides another way of personal verification by using the Finger Veins (FVs). The RDL consists of multiple layers with a feedback. Two FV fingers are employed for each person, FV of the index finger for first personal verification and FV of the middle finger for re-enforced verification. The used database is from the Hong Kong Polytechnic University Finger Image (PolyUFI) database (Version 1.0). The result shows that the proposed RDL achieved a promising performance of 91.19%. Also, other DL approaches are exploited for comparisons in this study including state-of-the-art models.

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24

Golodnova, N. N., and M. A. Pivovarova. "Verification of classification modernization solutions (the case study of Library Bibliographic Classification)." Scientific and Technical Libraries, no. 8 (August 14, 2023): 122–40. http://dx.doi.org/10.33186/1027-3689-2023-8-122-140.

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Efficiency of library classifications depends on their capacity to embrace current knowledge and social practices. Therefore, the verification (late Latin verificatio – evidence, confirmation, from the Latin verus – true and facio – to make) of upgrade solutions is an essential part of classification system operation and development. The problem of library classification verification is often out of researchers view. The verification mechanism (tools) for upgrade solutions has not been described yet. Therefore, the reliability and relevance of classification upgrade solutions is of scientific and practical value.The purpose of the paper is to summarize the related experience of Research LBC Center of the Russian State Library. Based on s tructured system analysis and the long practice of LBC development and application, the authors examine the mechanism for monitoring publications and identifying innovations, including new terms, concepts, social phenomena, etc., and for assessing and processing data for continuing update of the classification system. Using the example of LBC modernization solutions, the authors discuss advantages and disadvantages of individual methods. They conclude that the classification upgrade verification – essential to the nature of the library classification systems – has to become the key element of the classifying culture. The researchers review and suggest the ways to improve the verification mechanism adopted at the RSL LBC Research Center. The integrated approach to LBC verification is of applied relevance both for the theory of classifications and librarianship.

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25

Lazić, Ranko. "Verification column." ACM SIGLOG News 8, no. 2 (April 2021): 3. http://dx.doi.org/10.1145/3467001.3467002.

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This quarter's article expertly leads us from foundations to state-of-the-art in multiplayer turn-based infinite-duration games for synthesis of reactive systems. Providing examples throughout and an extensive coverage of related work, I expect it will quickly become a standard reference in the field.

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26

Lazić, Ranko. "Verification column." ACM SIGLOG News 7, no. 4 (October 2020): 3. http://dx.doi.org/10.1145/3458593.3458594.

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This quarter, we have an authoritative treatment of several basic verification problems for parallel programs running with shared memory under the topical total store ordering model. The article is also a testimony to the enduring relevance of the theory and practice of well-structured transition systems, which was recognised by the 2017 CAV Award.

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27

Krishna, Chandana. "Speaker Verification." IOSR Journal of VLSI and Signal Processing 2, no. 5 (2013): 01–08. http://dx.doi.org/10.9790/4200-0250108.

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28

McGregor, John D. "Variation Verification." Journal of Object Technology 8, no. 2 (2009): 7. http://dx.doi.org/10.5381/jot.2009.8.2.c1.

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29

Yehia, Ahmed. "Scalable Verification." International Conference on Electrical Engineering 9, no. 9th (May 1, 2014): 1. http://dx.doi.org/10.21608/iceeng.2014.30507.

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30

Lazić, Ranko. "Verification column." ACM SIGLOG News 8, no. 3 (July 2021): 5. http://dx.doi.org/10.1145/3477986.3477987.

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Given the extensive applications of logics with concrete domains in verification and related areas, the shortage of an accessible survey on the topic is quite surprising. This article does much more than fill the gap, providing also useful and inspiring pointers for future work.

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31

Vardi, Moshe Y. "Program verification." Communications of the ACM 64, no. 7 (July 2021): 5. http://dx.doi.org/10.1145/3469113.

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32

Lazić, Ranko. "Verification column." ACM SIGLOG News 8, no. 4 (October 2021): 3. http://dx.doi.org/10.1145/3527372.3527373.

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Notwithstanding the rapid recent progress in settling the very high computational complexity of the reachability problem, VASS (also known as Petri nets) remain an intriguing model of concurrency with extensive significance for verification and synthesis. In this engaging article, Tony introduces us to asymptotic analysis of VASS, showing that many relevant problems have attractive complexities, and concluding with several inviting directions for further investigations.

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Lazić, Ranko. "Verification column." ACM SIGLOG News 9, no. 1 (January 2022): 5. http://dx.doi.org/10.1145/3527540.3527541.

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In this highly readable article, Aiswarya takes a novel approach and reminds us of deep links between verification and the study of classes of graphs based on notions such as treewidth. Starting gently and providing ample examples, we are led to the state of the art and interesting open questions.

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34

Rungta, Neha. "Verification column." ACM SIGLOG News 3, no. 3 (August 8, 2016): 66. http://dx.doi.org/10.1145/2984450.2984458.

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Rungta, Neha. "Verification column." ACM SIGLOG News 2, no. 2 (April 22, 2015): 28. http://dx.doi.org/10.1145/2766189.2766194.

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Lazić, Ranko. "Verification column." ACM SIGLOG News 7, no. 3 (November 16, 2020): 28. http://dx.doi.org/10.1145/3436980.3436983.

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37

Drell, Sidney D. "Verification Triumphs." Bulletin of the Atomic Scientists 47, no. 9 (November 1991): 28–29. http://dx.doi.org/10.1080/00963402.1991.11460036.

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38

Maruyama. "Hardware Verification." Computer 18, no. 2 (February 1985): 22–32. http://dx.doi.org/10.1109/mc.1985.1662796.

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39

Lazić, Ranko. "Verification column." ACM SIGLOG News 5, no. 4 (November 12, 2018): 25. http://dx.doi.org/10.1145/3292048.3292051.

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Rungta, Neha. "Verification column." ACM SIGLOG News 4, no. 2 (May 3, 2017): 54. http://dx.doi.org/10.1145/3090064.3090069.

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41

O’Sullivan, Jack W., Amitava Banerjee, Carl Heneghan, and Annette Pluddemann. "Verification bias." BMJ Evidence-Based Medicine 23, no. 2 (February 27, 2018): 54–55. http://dx.doi.org/10.1136/bmjebm-2018-110919.

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This article is part of the Catalogue of Bias series. We present a description of verification bias, and outline its potential impact on research studies and the preventive steps to minimise its risk. We also present teaching slides in the online supplementary file. Verification bias (sometimes referred to as ‘work-up bias’) concerns the test(s) used to confirm a diagnosis within a diagnostic accuracy study. Verification bias occurs when only a proportion of the study participants receive confirmation of the diagnosis by the reference standard test, or if some participants receive a different reference standard test.

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42

Lazić, Ranko. "Verification column." ACM SIGLOG News 5, no. 3 (July 26, 2018): 66. http://dx.doi.org/10.1145/3242953.3242963.

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43

Ricanek, Karl. "Kinship Verification." Computer 53, no. 1 (January 2020): 7–8. http://dx.doi.org/10.1109/mc.2019.2952537.

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Atkins, Wendy. "Speaker verification." Biometric Technology Today 8, no. 3 (March 2000): 8–11. http://dx.doi.org/10.1016/s0969-4765(00)03012-5.

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45

Meenakshi, B. "Formal verification." Resonance 10, no. 5 (May 2005): 26–38. http://dx.doi.org/10.1007/bf02871329.

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46

Aguilera, Juan Pablo, and David Fernández-Duque. "Verification logic." Journal of Logic and Computation 27, no. 8 (August 14, 2017): 2451–69. http://dx.doi.org/10.1093/logcom/exx027.

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47

Sivilotti, Paolo A. G. "Verification Benchmarks." ACM SIGSOFT Software Engineering Notes 43, no. 3 (December 7, 2018): 19. http://dx.doi.org/10.1145/3229783.3299107.

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48

Lazić, Ranko. "Verification column." ACM SIGLOG News 6, no. 2 (April 22, 2019): 42. http://dx.doi.org/10.1145/3326938.3326941.

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Rungta, Neha. "Verification column." ACM SIGLOG News 3, no. 2 (May 31, 2016): 68. http://dx.doi.org/10.1145/2948896.2948904.

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Lazić, Ranko. "Verification column." ACM SIGLOG News 7, no. 2 (April 29, 2020): 3. http://dx.doi.org/10.1145/3397619.3397620.

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