Relevant bibliographies by topics / Verification and testing

Academic literature on the topic 'Verification and testing'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Verification and testing"

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Evernden, Jack F. "Verification of Nuclear Testing." Science 228, no. 4701 (May 17, 1985): 792–94. http://dx.doi.org/10.1126/science.228.4701.792.b.

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Evernden, Jack F. "Verification of Nuclear Testing." Science 228, no. 4701 (May 17, 1985): 792–94. http://dx.doi.org/10.1126/science.228.4701.792-b.

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Fodor, B., and I. Kollar. "ADC Testing With Verification." IEEE Transactions on Instrumentation and Measurement 57, no. 12 (December 2008): 2762–68. http://dx.doi.org/10.1109/tim.2008.928404.

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EVERNDEN, J. F. "Verification of Nuclear Testing." Science 228, no. 4701 (May 17, 1985): 792–94. http://dx.doi.org/10.1126/science.228.4701.792-a.

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Ferris, E. A. E. "Gender verification testing in sport." British Medical Bulletin 48, no. 3 (1992): 683–97. http://dx.doi.org/10.1093/oxfordjournals.bmb.a072571.

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Hailpern, B., and P. Santhanam. "Software debugging, testing, and verification." IBM Systems Journal 41, no. 1 (2002): 4–12. http://dx.doi.org/10.1147/sj.411.0004.

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Margaria, Tiziana, Zongyan Qiu, and Hongli Yang. "Program verification and testing technologies." International Journal on Software Tools for Technology Transfer 16, no. 4 (June 25, 2014): 335–37. http://dx.doi.org/10.1007/s10009-014-0327-0.

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Tracey, Nigel, John Penix, and Willem Visser. "Automated analysis, verification and testing." Software Focus 2, no. 2 (2001): 82. http://dx.doi.org/10.1002/swf.34.

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Schmitt, Robert L., Awad S. Hanna, Jeffrey S. Russell, and Erik V. Nordheim. "Statistically Based Methods for Verification Testing." Transportation Research Record: Journal of the Transportation Research Board 1761, no. 1 (January 2001): 86–92. http://dx.doi.org/10.3141/1761-11.

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Findlay, Trevor, and Oliver Meier. "Nuclear Testing: In verification we trust." Bulletin of the Atomic Scientists 57, no. 1 (January 1, 2001): 13–15. http://dx.doi.org/10.2968/057001005.

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Dissertations / Theses on the topic "Verification and testing"

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Rotting, Tjädermo Viktor, and Alex Tanskanen. "System Upgrade Verification : An automated test case study." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-165125.

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We live in a society where automatization is becoming more common, whether it be cars or artificial intelligence. Software needs to be updated using patches, however, these patches have the possibility of breaking components. This study takes such a patch in the context of Ericsson, identifies what needs to be tested, investigates whether the tests can be automated and assesses how maintainable they are. Interviews were used for the identification of system and software parts in need of testing. Then tests were implemented in an automated test suite to test functionality of either a system or software. The goal was to reduce time of troubleshooting for employees without interrupting sessions for users as well as set up a working test suite. When the automated testing is completed and implemented in the test suite, the study is concluded by measuring the maintainability of the scripts using both metrics and human assessment through interviews. The result showed the testing suite proved maintainable, both from the metric point of view and from human assessment.
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Wu, Weixin. "Mining constraints for Testing and Verification." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/31056.

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With the advances in VLSI and System-On-Chip (SOC) technologies, the complexity of hardware systems has increased manifold. The increasing complexity poses serious challenges to the digital hardware design. Functional verification has become one of the most expensive and time-consuming components of the current product development cycle. Today, design verification alone often surpasses 70% of the total development cost and the situation has been projected to continue to worsen. The two most widely used formal methods for design verification are Equivalence Checking and Model Checking. During the design phase, hardware goes through several stages of optimizations for area, speed, power, etc. Determining the functional correctness of the design after each optimization step by means of exhaustive simulation can be prohibitively expensive. An alternative to prove functional correctness of the optimized design is to determine the design's functional equivalence with respect to some golden model which is known to be functionally correct. Efficient techniques to perform this process is known as Equivalence Checking. Equivalence Checking requires that the implementation circuit should be functionally equivalent to the specification circuit. Complexities in Equivalence Checking can be exponential to the circuit size in the worst case. Since Equivalence Checking of sequential circuits still remains a challenging problem, in this thesis, we first address this problem using efficient learning techniques. In contrast to the traditional learning methods, our method employs a mining algorithm to discover global constraints among several nodes efficiently in a sequential circuit. In a Boolean satisfiability (SAT) based framework for the bounded sequential equivalence checking, by taking advantage of the repeated search space, our mining algorithm is only performed on a small window size of unrolled circuit, and the mined relations could be reused subsequently. These powerful relations, when added as new constraint clauses to the original formula, help to significantly increase the deductive power for the SAT engine, thereby pruning a larger portion of the search space. Likewise, the memory required and time taken to solve these problems are alleviated. We also propose a pseudo-functional test generation method based on effective functional constraints extraction. We use mining techniques to extract a set of multi-node functional constraints which consists of illegal states and internal signal correlation. Then the functional constraints are imposed to a ATPG tool to generate pseudo functional delay tests.
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Jayabharathi, Rathish. "Hierarchical timing verification and delay fault testing /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Nilsson, Daniel. "System for firmware verification." Thesis, University of Kalmar, School of Communication and Design, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hik:diva-2372.

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Software verification is an important part of software development and themost practical way to do this today is through dynamic testing. This reportexplains concepts connected to verification and testing and also presents thetesting-framework Trassel developed during the writing of this report.Constructing domain specific languages and tools by using an existinglanguage as a starting ground can be a good strategy for solving certainproblems, this was tried with Trassel where the description-language forwriting test-cases was written as a DSL using Python as the host-language.

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Argote, Garcia Gonzalo. "Formal verification and testing of software architectural models." FIU Digital Commons, 2009. http://digitalcommons.fiu.edu/etd/1308.

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Ensuring the correctness of software has been the major motivation in software research, constituting a Grand Challenge. Due to its impact in the final implementation, one critical aspect of software is its architectural design. By guaranteeing a correct architectural design, major and costly flaws can be caught early on in the development cycle. Software architecture design has received a lot of attention in the past years, with several methods, techniques and tools developed. However, there is still more to be done, such as providing adequate formal analysis of software architectures. On these regards, a framework to ensure system dependability from design to implementation has been developed at FIU (Florida International University). This framework is based on SAM (Software Architecture Model), an ADL (Architecture Description Language), that allows hierarchical compositions of components and connectors, defines an architectural modeling language for the behavior of components and connectors, and provides a specification language for the behavioral properties. The behavioral model of a SAM model is expressed in the form of Petri nets and the properties in first order linear temporal logic. This dissertation presents a formal verification and testing approach to guarantee the correctness of Software Architectures. The Software Architectures studied are expressed in SAM. For the formal verification approach, the technique applied was model checking and the model checker of choice was Spin. As part of the approach, a SAM model is formally translated to a model in the input language of Spin and verified for its correctness with respect to temporal properties. In terms of testing, a testing approach for SAM architectures was defined which includes the evaluation of test cases based on Petri net testing theory to be used in the testing process at the design level. Additionally, the information at the design level is used to derive test cases for the implementation level. Finally, a modeling and analysis tool (SAM tool) was implemented to help support the design and analysis of SAM models. The results show the applicability of the approach to testing and verification of SAM models with the aid of the SAM tool.
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Zhou, Zhiquan, and 周智泉. "Verification of program properties: from testing to semi-proving." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2003. http://hub.hku.hk/bib/B31245134.

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Sudol, Alicia. "A methodology for modeling the verification, validation, and testing process for launch vehicles." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54429.

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Completing the development process and getting to first flight has become a difficult hurdle for launch vehicles. Program cancellations in the last 30 years were largely due to cost overruns and schedule slips during the design, development, testing and evaluation (DDT&E) process. Unplanned rework cycles that occur during verification, validation, and testing (VVT) phases of development contribute significantly to these overruns, accounting for up to 75% of development cost. Current industry standard VVT planning is largely subjective with no method for evaluating the impact of rework. The goal of this research is to formulate and implement a method that will quantitatively capture the impact of unplanned rework by assessing the reliability, cost, schedule, and risk of VVT activities. First, the fidelity level of each test is defined and the probability of rework between activities is modeled using a dependency structure matrix. Then, a discrete event simulation projects the occurrence of rework cycles and evaluates the impact on reliability, cost, and schedule for a set of VVT activities. Finally, a quadratic risk impact function is used to calculate the risk level of the VVT strategy based on the resulting output distributions. This method is applied to alternative VVT strategies for the Space Shuttle Main Engine to demonstrate how the impact of rework can be mitigated, using the actual test history as a baseline. Results indicate rework cost to be the primary driver in overall project risk, and yield interesting observations regarding the trade-off between the upfront cost of testing and the associated cost of rework. Ultimately, this final application problem demonstrates the merits of this methodology in evaluating VVT strategies and providing a risk-informed decision making framework for the verification, validation, and testing process of launch vehicle systems.
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Belsick, Charlotte Ann. "Space Vehicle Testing." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/888.

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Requirement verification and validation is a critical component of building and delivering space vehicles with testing as the preferred method. This Master’s Project presents the space vehicle test process from planning through test design and execution. It starts with an overview of the requirements, validation, and verification. The four different verification methods are explained including examples as to what can go wrong if the verification is done incorrectly. Since the focus of this project is on test, test verification is emphasized. The philosophy behind testing, including the “why” and the methods, is presented. The different levels of testing, the test objectives, and the typical tests are discussed in detail. Descriptions of the different types of tests are provided including configurations and test challenges. While most individuals focus on hardware only, software is an integral part of any space product. As such, software testing, including mistakes and examples, is also presented. Since testing is often not performed flawlessly the first time, sections on anomalies, including determining root cause, corrective action, and retest is included. A brief discussion of defect detection in test is presented. The project is actually presented in total in the Appendix as a Power Point document.
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Ipate, Florentin Eugen. "Theory of X-machines with applications in specification and testing." Thesis, University of Sheffield, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.319486.

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Woo, Yan, and 胡昕. "A dynamic integrity verification scheme for tamper-resistancesoftware." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2005. http://hub.hku.hk/bib/B34740478.

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Books on the topic "Verification and testing"

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Srinivas, Devadas, and Newton A. Richard 1951-, eds. Sequential logic testing and verification. Boston: Kluwer Academic, 1992.

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Ghosh, Abhijit, Srinivas Devadas, and A. Richard Newton. Sequential Logic Testing and Verification. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3646-8.

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Ghosh, Abhijit. Sequential Logic Testing and Verification. Boston, MA: Springer US, 1992.

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Zeljko, Zilic, ed. Verification by error modeling: Using testing techniques in hardware verification. Boston: Kluwer Academic Publishers, 2003.

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IFIP WG 6.1 International Symposium on Protocol Specification, Testing and Verification (14th 1994 Vancouver, B.C). Protocol specification, testing and verification XIV. London: Chapman & Hall, 1995.

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Eder, Kerstin, João Lourenço, and Onn Shehory, eds. Hardware and Software: Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-34188-5.

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Bloem, Roderick, and Eli Arbel, eds. Hardware and Software: Verification and Testing. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-49052-6.

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Bertacco, Valeria, and Axel Legay, eds. Hardware and Software: Verification and Testing. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03077-7.

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Yahav, Eran, ed. Hardware and Software: Verification and Testing. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-13338-6.

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Barner, Sharon, Ian Harris, Daniel Kroening, and Orna Raz, eds. Hardware and Software: Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19583-9.

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Book chapters on the topic "Verification and testing"

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Rajamani, Sriram K. "Verification, Testing and Statistics." In Runtime Verification, 25. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-04694-0_2.

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Tay, Francis E. H. "Verification and Testing." In Microsystems, 101–13. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-3534-5_5.

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Velure, Arild. "Verification and Testing." In Springer Theses, 93–124. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-71559-5_4.

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Drury, Michael. "Initial Verification." In Electrical Inspection, Testing and Certification, 97–109. Second edition. | Boca Raton: Taylor & Francis, Routledge, 2018.: Routledge, 2018. http://dx.doi.org/10.1201/9781351232838-5.

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Sheu, Phillip C. Y. "Program Verification and Testing." In Software Engineering and Environment, 231–60. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-5907-8_9.

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Nori, Aditya, and Sriram K. Rajamani. "Verification, Testing and Statistics." In Tests and Proofs, 6–9. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-02949-3_2.

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Schneier, Bruce. "Product Testing and Verification." In Secrets and Lies, 334–52. Indianapolis, Indiana: Wiley Publishing, Inc., 2015. http://dx.doi.org/10.1002/9781119183631.ch22.

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Dghaym, Dana, Tomas Fischer, Thai Son Hoang, Klaus Reichl, Colin Snook, Rupert Schlick, and Peter Tummeltshammer. "Systematic Verification and Testing." In Validation and Verification of Automated Systems, 89–104. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-14628-3_9.

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Guerin, Frank, and Jeremy Pitt. "Verification and Compliance Testing." In Communication in Multiagent Systems, 98–112. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-44972-0_4.

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Rajamani, Sriram K. "Verification, Testing and Statistics." In Theoretical Aspects of Computing - ICTAC 2009, 79. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03466-4_4.

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Conference papers on the topic "Verification and testing"

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Fodor, Balazs, and Istvan Kollar. "ADC Testing with Verification." In 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007. IEEE, 2007. http://dx.doi.org/10.1109/imtc.2007.378993.

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Pastore, Fabrizio, Leonardo Mariani, Antti E. J. Hyvärinen, Grigory Fedyukovich, Natasha Sharygina, Stephan Sehestedt, and Ali Muhammad. "Verification-aided regression testing." In the 2014 International Symposium. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2610384.2610387.

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Plummer, F. B., Bjørn Haslerud, and Svein Carlsen. "Snorre Verification And Testing." In Offshore Technology Conference. Offshore Technology Conference, 1993. http://dx.doi.org/10.4043/7219-ms.

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Pinero, Luis, and James Sovey. "NEXT Thruster Component Verification Testing." In 43rd AIAA/ASME/SAE/ASEE Joint Propulsion Conference & Exhibit. Reston, Virigina: American Institute of Aeronautics and Astronautics, 2007. http://dx.doi.org/10.2514/6.2007-5276.

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Stuhlinger, Tilman W. "Subaperture Optical Testing: Experimental Verification." In 1986 International Symposium/Innsbruck, edited by Robert E. Fischer and Philip J. Rogers. SPIE, 1986. http://dx.doi.org/10.1117/12.938444.

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Stuhlinger, Tilman W. "Subaperture Optical Testing: Experimental Verification." In 1986 International Symposium/Innsbruck, edited by Leo H. J. F. Beckmann, J. D. Briers, and Paul R. Yoder, Jr. SPIE, 1986. http://dx.doi.org/10.1117/12.938467.

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Ait Ettajer, Alexandre. "Verification Testing for Multiphysics Codes." In Proposed for presentation at the Virtual NM Intern Symposium in ,. US DOE, 2021. http://dx.doi.org/10.2172/1878722.

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Katz, Shmuel. "Session details: Testing and verification." In AOSD '09: Eighth International Conference on Aspect-Oriented Software Development. New York, NY, USA: ACM, 2009. http://dx.doi.org/10.1145/3247283.

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Bertolino, Antonia. "Session details: Verification and testing." In Comparch '11: Federated Events on Component-Based Software Engineering and Software Architecture. New York, NY, USA: ACM, 2011. http://dx.doi.org/10.1145/3244772.

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Sugai, Kenta, Hiroshi Hosobe, and Shaoying Liu. "SMT-Based Theorem Verification for Testing-Based Formal Verification." In ICSCA 2021: 2021 10th International Conference on Software and Computer Applications. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3457784.3457823.

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Reports on the topic "Verification and testing"

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Aleman, S. PORFLOW TESTING AND VERIFICATION DOCUMENT. Office of Scientific and Technical Information (OSTI), June 2007. http://dx.doi.org/10.2172/909355.

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Whiteside, Tad S. HDTS 2017.0 Testing and verification document. Office of Scientific and Technical Information (OSTI), August 2017. http://dx.doi.org/10.2172/1374368.

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Whiteside, T. HDTS 2017.1 Testing and Verification Document. Office of Scientific and Technical Information (OSTI), December 2017. http://dx.doi.org/10.2172/1414385.

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Whiteside, Tad S. PORFLOW 6.42.9 Testing and Verification Document. Office of Scientific and Technical Information (OSTI), June 2018. http://dx.doi.org/10.2172/1459419.

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Mesina, George L. RELAP5-3D Restart and Backup Verification Testing. Office of Scientific and Technical Information (OSTI), September 2013. http://dx.doi.org/10.2172/1120815.

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Sen, Koushik, Costin Iancu, and James W. Demmel. Program Correctness, Verification and Testing for Exascale (Corvette). Office of Scientific and Technical Information (OSTI), January 2018. http://dx.doi.org/10.2172/1418165.

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Rizvi, Syed A., P. Jonathon Phillips, and Hyeonjoon Moon. The FERET verification testing protocol for face recognition algorithms. Gaithersburg, MD: National Institute of Standards and Technology, 1998. http://dx.doi.org/10.6028/nist.ir.6281.

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Porter, Nathan, Robert Salko, and Martin Pilch. FY20 Improvements to CTF Code Verification and Unit Testing. Office of Scientific and Technical Information (OSTI), February 2020. http://dx.doi.org/10.2172/1763289.

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Josey, Colin, Alexander Clark, Joel Kulesza, Eric Pearson, and Michael Rising. MCNP® Code Version 6.3.0 Verification & Validation Testing. Office of Scientific and Technical Information (OSTI), December 2022. http://dx.doi.org/10.2172/1907750.

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McCord, J. T., and M. T. Goodrich. Benchmark testing and independent verification of the VS2DT computer code. Office of Scientific and Technical Information (OSTI), November 1994. http://dx.doi.org/10.2172/10105566.

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