Relevant bibliographies by topics / VEDIC MULTIPLIERS

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'VEDIC MULTIPLIERS'

Author: Grafiati
Published: 11 September 2023

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Journal articles on the topic "VEDIC MULTIPLIERS"

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Eshack, Ansiya, and S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (June 1, 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.

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Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is noticed that as complexity of adders in the multipliers reduce, the systems show improved speed and least hardware utilization. The architecture designed using 2 x 2 – bit pipelined Vedic multiplier is, then, compared with existing Vedic multipliers and conventional multipliers and shows least delay.
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Khubnani, Rashi, Tarunika Sharma, and Chitirala Subramanyam. "Applications of Vedic multiplier - A Review." Journal of Physics: Conference Series 2225, no. 1 (March 1, 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.

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Abstract Vedic Multiplier is a key tool in rapidly growing technology especially in the immense domain of Image processing, Digital Signal Processing, real-time signal. Multipliers are important block in digital systems and play a critical role in digital designs. Along with accuracy demand for minimizing time area, power, and delay of the processor by enhancing speed is the focus point. Vedic mathematics rules and Algorithms generate partial products concurrently and save time. This paper is a review of the application and modification of Vedic multiplier in different fields and a comparison of Vedic multiplier with other multipliers for enhancing performance parameters.
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Rashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.

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In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.
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Bhairannawar, Satish s., Raja K B, Venugopal K R, and L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 5 (January 30, 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.

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Most of the algorithms which are used in DSP, image and video processing, computer graphics, vision and high performance supercomputing applications require multiplication and matrix operation as the kernel operation.In this paper, we propose Efficient FPGA based matrix multiplication using MUX and Vedic multiplier. The 2x2, 3x2 and 3x3 MUX based multipliers are designed. The basic lower order MUX based multipliers are used to design higher order MxN multipliers with a concept of UrdhvaTiryakbyham Vedic approach. The proposed multiplier is used for image processing applications. It is observed that the device utilization and combinational delay are less in the proposed architecture compared to existing architectures.
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Nandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (December 15, 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.

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Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.
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CVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad, and V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics." International Journal of Engineering & Technology 7, no. 2.4 (March 10, 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.
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Kuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (June 22, 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.

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Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.
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CVS, Chaitanya, Sundaresan C, and P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.
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Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.

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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.
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Prof. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device." International Journal of New Practices in Management and Engineering 6, no. 01 (March 31, 2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.

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Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.
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Dissertations / Theses on the topic "VEDIC MULTIPLIERS"

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ANTONY, SAJI M. "DESIGN OF ENERGY EFFICIENT TRANSCEIVER BLOCKS FOR WIRELESS SENSOR NODES." Thesis, DELHI TECHNOLOGICAL UNIVERSITY, 2020. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18771.

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Sensor networks have been recognised as one of the most advanced technologies of the 21st century with vast practical applications. The life of a sensor network is mainly determined by its energy consumption. Commercially available sensor nodes are battery driven devices. As most sensor nodes are deployed widely scattered and in isolated areas, replacing battery is not an option. This dissertation focuses on extending the lifespan of sensor networks by reducing energy consumption in design and operation of sensor nodes. The study goes in depth to analyse the state of art technology to achieve energy efficiency in sensor nodes and identify scope for further research in this field. In the architecture of sensor nodes, multipliers are the main blocks for designing an energy efficient processor. Vedic Mathematics provides principles of high speed multiplication. The main reason for power dissipation in multiplier circuit is due to power dissipation of full adder circuit. Low power multipliers have been designed by using low power adders. Motivated by this, a high speed Vedic multiplier has been designed using multiplexer based adder. When compared with existing Vedic multipliers, proposed designs showed significant improvement in reduction of delay and energy consumption. Sensor nodes consume maximum power during data communication. So processing data locally at each node in a sensor network is important for minimizing power consumption. High processing speed and low area designs are in ever growing demand. In order to predict outcomes, based on previous inputs, ALU can be designed with neurons. Processing speed of ALU can be improved by replacing conventional multipliers with Vedic multipliers. This research work suggests implementation of high speed ALU using Vedic neurons. The analysis of the results shows that the proposed design leads to x reduction in the delay and reduction in LUT count (an indicator of area) of the ALU. Use of energy efficient power amplifiers is an essential requirement for sensor nodes, as power amplifiers are responsible for the main power consumption in the transceivers of sensor nodes. Again, wider band width is another important requirement for power amplifiers used in sensor transceivers especially in wireless visual sensor networks and wireless multimedia sensor networks. Reliability of a power amplifier can be increased by designing it at smaller supply voltage. This thesis suggests improvements in design of power amplifier in class E configuration, for transceivers in wireless sensor nodes. In order to achieve wider band width, cascade of common drain followed by common source in class E configuration has been designed; and for more reliable operation with higher efficiency, class E in double cascoded has been implemented. The proposed designs, when simulated in SPICE, higher efficiencies and band widths have been achieved. This research also explored to design a robust solar energy harvesting system to enhance life time of sensor nodes. Proposed solar energy supply system mainly consists of a solar panel, rechargeable battery and a control circuit. To obtain sufficient voltage to charge battery, electrical energy generated through panel is boosted by boost converter. Different sensor nodes are supplied with energy from this system. An inverter is also designed for AC applications. Experimental results show that this compact, self-sufficient system enables outdoor based wireless sensor network nodes to operate successfully for longer periods.
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Jiang, CunHao, and 蔣存皓. "An Efficient Vedic Multiplier Design." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/65n6nm.

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碩士
國立臺北科技大學
電子工程系研究所
105
Multiplier is one of core operations of the digital signal processing and microprocessor. the multiplier in the digital circuit needs to increase the speed, decrease the area and consume less memory. So an efficient multiplier is very important in nowadays. This paper is about designing traditional Vedic multiplier through the Urdhva-Tiryagbhyam sutra. Changing the adder from the traditional Vedic multiplier which designed with the sutra, it can become two kinds of efficient Vedic multipliers. After designing 4-bit, 8-bit, 16-bit, 32-bit traditional Vedic multiplier and two kinds of efficient Vedic multipliers, their time delay and areas are analyzed through the Quartus II. According to the results of the experiment, time delay of the original efficient Vedic multiplier decreases 5.88％ but the area increases 37.298%. Besides, time delay of the resolved efficient Vedic multiplier decreases 7.4% but the area increases 21.6%. If the multiplier needs to be faster on work afterwards, 4-bit and 16-bit original efficient Vedic multiplier and 8-bit, 32-bit and 64-bit resolved efficient Vedic multiplier are suggested. If the multiplier needs to be smaller, traditional Vedic multiplier is suggested. If both delay time and chip area cost are considered comprehensively, 8-bit or 64-bit resolved efficient Vedic multiplier are suggested.
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RUHELA, DIKSHA. "DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE MULTIPLIER USING VEDIC MATHEMATICS TOOL." Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14759.

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Multiplier is one of the important block in almost all the arithmetic logic units. These multipliers are mostly used in the fields of the Digital Signal Processing (DSP), Fast Fourier Transform, convolution, filtering and microprocessor applications. A system's performance is generally determined by the performance of the multiplier, because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. Since multiplier is the main component and hence a high speed and area efficient multiplier can be achieve by using Vedic mathematics. In this work we have implemented the Vedic multiplier using Chinese Abacus Adder with and without using Reversible logic gates. Reversible logic is one of the promising fields for future low power design technologies. Since one of the requirements of all DSP processors and other embedded devices is to minimize power dissipation multipliers with high speed and lower dissipations are critical. This work is devoted to the design of a high speed Vedic multiplier using reversible logic gates. For arithmetic multiplication, various Vedic multiplication techniques like Urdhva Tiryakbhyam, Nikhilam and Anurupye have been thoroughly discussed. It has been found that Urdhva Tiryakbhyam Sutra is the most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva Tiryakbhyam Sutra for 32x32 bits and 64x64 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done. The synthesis results show that the computation time for calculating the product of 4x4 multiplication is less as compared with other conventional multipliers.
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KUMAR, SHIVAM. "DESIGN AND IMPLEMENTATION OF EFFICIENT MATRIX MULTIPLICATION USING VARIOUS ARCHITECTURE." Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19896.

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The semiconductor industry plays a crucial role in the design and manufacture of integrated circuits (ICs) used in a wide range of electronic devices. VLSI technology allows for the integration of millions of transistors onto a single chip, enabling the creation of highly complex and powerful devices such as computers, smart phones, and other electronic devices. The VLSI industry is a key driver of innovation in the electronics industry and has played a major role in the development of new technologies and the proliferation of electronic devices in our daily lives. Consequently, area, speed, and power play a critical role in any circuit design .A circuit must be created to meet the present trend's requirements with minimal space and minimal time limitations. Matrix multiplication is of significant importance in various fields and applications. Matrix multiplication plays a fundamental role in linear algebra, solving system of linear equations, data analysis and machine learning, computer graphics and computer vision, network theory and graph algorithm, etc. This thesis gives a thorough investigation into how the Wallace tree multiplier, Vedic multiplier, and parallel prefix adders might be combined to enhance matrix multiplication performance. These techniques contribute to achieving significant speed improvements, reduced and optimized resource utilization. The findings of this study add to understanding of digital circuit design by offering suggestions for choosing and incorporating effective multiplication methods for matrix operations. The thesis provides helpful advice to researchers and designers of digital circuits by explaining the trade-offs, benefits, and drawbacks of the integrated architecture. Firstly, Ripple Carry adders, Kogge Stone adders, and Han Carlson adders have been designed and analyzed. After that, the Wallace tree multiplier and Vedic multiplier are designed using these adders. By combining both multiplier and adder, matrix multiplication designs, analyses the performance data, and interprets the results obtained from the experiments. Using the ISE Design Suite tools in Verilog, all circuits are created and simulations are run. The XC6SLX150T are the devices used for synthesis.
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Books on the topic "VEDIC MULTIPLIERS"

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Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach) . Innovative Research Publications, 2013.

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Book chapters on the topic "VEDIC MULTIPLIERS"

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Sai Ramya, A., B. S. S. V. Ramesh Babu, E. Srikala, M. Pavan, P. Unita, and A. V. S. Swathi. "Performance of Optimized Reversible Vedic Multipliers." In Lecture Notes in Networks and Systems, 587–93. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3226-4_60.

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Eshack, Ansiya, and S. Krishnakumar. "Design of Low-Power Vedic Multipliers Using Pipelining Technology." In Proceedings of the Third International Conference on Computational Intelligence and Informatics, 281–87. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1480-7_24.

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Pasuluri, Bindu Swetha, and V. J. K. Kishor Sonti. "Performance Analysis of 8-Bit Vedic Multipliers Using HDL Programming." In Lecture Notes in Electrical Engineering, 1036–46. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1420-3_114.

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Loganathan, Haripriya, Patnaikuni Rohit, Polamarasetty Sai Suneel, and Karthi Balasubramanian. "Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics." In Lecture Notes in Electrical Engineering, 475–86. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-8942-9_39.

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Sudhamsu Preetham, J. V. R., Perli Nethra, D. Chandrasekhar, Mathangi Akhila, N. Arun Vignesh, and Asisa Kumar Panigrahy. "Vedic Multiplier for High-Speed Applications." In Communication, Software and Networks, 349–56. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4990-6_31.

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Pavan Kumar, N., and K. Shashi Raj. "Delay Analysis of Hybrid Vedic Multiplier." In Advances in Intelligent Systems and Computing, 91–103. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7330-6_8.

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Lachireddy, Dhanunjay, and S. R. Ramesh. "Power and Delay Efficient ALU Using Vedic Multiplier." In Lecture Notes in Electrical Engineering, 703–11. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5558-9_61.

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Kumari, Sabita, and Kanchan Sharma. "Implementation of Nobel Vedic Multiplier Using Arithmetic Adder." In Data Intelligence and Cognitive Informatics, 209–16. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6460-1_15.

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Awade, Anirudh, Prachi Jain, S. Hemavathy, and V. S. Kanchana Bhaaskaran. "Design of Vedic Multiplier Using Reversible Logic Gates." In Lecture Notes in Electrical Engineering, 435–48. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-9019-1_38.

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Srimani, Supriyo, Diptendu Kumar Kundu, Saradindu Panda, and B. Maji. "Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra." In Computational Advancement in Communication Circuits and Systems, 443–49. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_49.

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Conference papers on the topic "VEDIC MULTIPLIERS"

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Jain, Ankita, and Atush Jain. "Design, implementation & comparison of vedic multipliers with conventional multiplier." In 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS). IEEE, 2017. http://dx.doi.org/10.1109/icecds.2017.8389596.

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Kumar, Akash, Tarun Chaudhary, and Vijay Kumar Ram. "Comparative Analysis of Multiplications Technique Conventional, Booth, Array Multiplier and Vedic Arithmetic Using VHDL." In International Conference on Women Researchers in Electronics and Computing. AIJR Publisher, 2021. http://dx.doi.org/10.21467/proceedings.114.63.

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The multiplication operation is one of the often used operation in many computer and electronic devices. Low power utilization is one of the most essential attributes for meeting several challenges in many applications. In this paper different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processing, so designing a high speed multiplier is the need the hour. Structures of 4X4 bits Urdhva Tiryagbhya, Nikhilam Sutra have been executed on Spartan 3 XC3S50-5-PQ-208.The determined calculation delay for 4X4 Urdhva Tiryagbhyam was 14.14 ns and force is 20.60 mw. For Nikhilam Sutra the determined computational postponement is 16.16 ns and all out force utilization is 24.60 mw.
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Gujamagadi, Pavan, Pramod R. Sankolli, Praveen Kumar V, Raghavendra Nayak B, Namita Palecha, and Suma MS. "Design of Vedic multiplier for high fault coverage and comparative analysis with conventional multipliers." In 2015 IEEE International Advance Computing Conference (IACC). IEEE, 2015. http://dx.doi.org/10.1109/iadcc.2015.7154805.

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Saligram, Rakshith, and T. R. Rakshith. "Optimized reversible vedic multipliers for high speed low power operations." In 2013 IEEE Conference on Information & Communication Technologies (ICT). IEEE, 2013. http://dx.doi.org/10.1109/cict.2013.6558205.

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Mulkalapally, Mounika, Jacob Manning, Paul Gatewood, and Tooraj Nikoubin. "High Speed, Area and Power Efficient 32-bit Vedic Multipliers." In ICCCNT '16: 7th International Conference on Computing Communication and Networking Technologies. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2967878.2967890.

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Kumari, Raj, and Rajesh Mehra. "Power and delay analysis of CMOS multipliers using Vedic algorithm." In 2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES). IEEE, 2016. http://dx.doi.org/10.1109/icpeices.2016.7853344.

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Vijayan, Aravind E., Arlene John, and Deepak Sen. "Efficient implementation of 8-bit vedic multipliers for image processing application." In 2014 International Conference on Contemporary Computing and Informatics (IC3I). IEEE, 2014. http://dx.doi.org/10.1109/ic3i.2014.7019675.

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Raj, Rishi, Darsana S, and Ramesh P. "Performance Analysis of 32-Bit Vedic Multipliers for Different Adder Configurations." In 2022 IEEE 19th India Council International Conference (INDICON). IEEE, 2022. http://dx.doi.org/10.1109/indicon56171.2022.10040134.

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Rao, K. Deergha, P. V. Muralikrishna, and Ch Gangadhar. "FPGA Implementation of 32 Bit Complex Floating Point Multiplier Using Vedic Real Multipliers with Minimum Path Delay." In 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON). IEEE, 2018. http://dx.doi.org/10.1109/upcon.2018.8597031.

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Patil, Abhijeet, Shreyas Kapare, Ganesh Shinde, Arti Tekade, Maithili Andhare, and Vijayalaxmi Kumbar. "Create a 32-bit Vedic Multiplier and Compare it Against Other Multipliers Using A Carry Look-Ahead Adder." In 2023 4th International Conference for Emerging Technology (INCET). IEEE, 2023. http://dx.doi.org/10.1109/incet57972.2023.10170076.

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