Journal articles: 'VEDIC MULTIPLIER'

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Eshack, Ansiya, and S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (June 1, 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.

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Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is noticed that as complexity of adders in the multipliers reduce, the systems show improved speed and least hardware utilization. The architecture designed using 2 x 2 – bit pipelined Vedic multiplier is, then, compared with existing Vedic multipliers and conventional multipliers and shows least delay.

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Khubnani, Rashi, Tarunika Sharma, and Chitirala Subramanyam. "Applications of Vedic multiplier - A Review." Journal of Physics: Conference Series 2225, no. 1 (March 1, 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.

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Abstract Vedic Multiplier is a key tool in rapidly growing technology especially in the immense domain of Image processing, Digital Signal Processing, real-time signal. Multipliers are important block in digital systems and play a critical role in digital designs. Along with accuracy demand for minimizing time area, power, and delay of the processor by enhancing speed is the focus point. Vedic mathematics rules and Algorithms generate partial products concurrently and save time. This paper is a review of the application and modification of Vedic multiplier in different fields and a comparison of Vedic multiplier with other multipliers for enhancing performance parameters.

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Rashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.

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In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

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Kuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (June 22, 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.

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Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

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Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.

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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.

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Safoev, Nuriddin, and Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata." Electronics 9, no. 6 (June 23, 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.

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A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.

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CVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad, and V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics." International Journal of Engineering & Technology 7, no. 2.4 (March 10, 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

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C, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M, and Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.

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Abstract: This paper proposes low-power multiplier architectures based on Vedic mathematics, which is a set of ancient Indian techniques for performing arithmetic operations. The proposed architectures use the Urdhva-Tiryagbhyam sutra from Vedic mathematics, which enables the efficient multiplication of numbers with fewer partial products. The proposed architectures have been implemented and simulated using the 45-nm CMOS technology. The simulation results demonstrate that the proposed architectures achieve significant power savings compared to conventional multipliers while maintaining reasonable area and delay. Therefore, the proposed architectures are suitable for use in low-power and high-performance applications. The Vedic multiplier consists of several sub-modules, each of which performs a specific function in the multiplication process. These submodules include the partial product generator, the multiplier, and the adder. The partial product generator generates partial products based on the input numbers and the Vedic sutras. The multiplier module then combines these partial products to create the final product. Finally, the adder module adds the product to the previous state of the circuit to generate the final result.

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Bhairannawar, Satish s., Raja K B, Venugopal K R, and L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 5 (January 30, 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.

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Most of the algorithms which are used in DSP, image and video processing, computer graphics, vision and high performance supercomputing applications require multiplication and matrix operation as the kernel operation.In this paper, we propose Efficient FPGA based matrix multiplication using MUX and Vedic multiplier. The 2x2, 3x2 and 3x3 MUX based multipliers are designed. The basic lower order MUX based multipliers are used to design higher order MxN multipliers with a concept of UrdhvaTiryakbyham Vedic approach. The proposed multiplier is used for image processing applications. It is observed that the device utilization and combinational delay are less in the proposed architecture compared to existing architectures.

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Nandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (December 15, 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.

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Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.

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Saraswathi, N., Lokesh Modi, and Aatish Nair. "Complex Number Vedic Multiplier and its Implementation in a Filter." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 336. http://dx.doi.org/10.14419/ijet.v7i2.24.12078.

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Complex numbers multiplication is a fundamental mathematical process in systems like digital signal processors (DSP). The main objective of complex number multiplication is to perform operations at lightning fast speed with less intake of power. In this paper, the best possible architecture is designed for a Real vedic multiplier based on the ancient Indian mathematical procedure known as URDHVA TIRYAKBHYAM SUTRA i.e. the structure of a MxM Vedic real multiplier architecture is developed. Then, a Vedic real multiplier solution of a complex multiplier is presented and its simulation results are obtained. The MxM Vedic real multiplier architecture, architecture of the Real Vedic multiplier solution for 32 x 32 bit complex numbers multiplication of complex multiplier and the architecture of a FIR filter has been code in Verilog and implementation is done through Modelsim 5.6 and Xilinx ISE 7.1 navigator.

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Prof. Sharayu Waghmare. "Vedic Multiplier Implementation for High Speed Factorial Computation." International Journal of New Practices in Management and Engineering 1, no. 04 (December 31, 2012): 01–06. http://dx.doi.org/10.17762/ijnpme.v1i04.8.

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Vedic Mathematics arise from the prehistoric classification of Indian mathematics that was recreated by Tirthaji. Ancient mathematical operations are depending on sixteen methods. In this article, a new VLSI architecture to compute factorial of the given number with Vedic based multiplier is proposed. Simulations are performed using Xilinx ISE 14.2. Effective comparative analysis is made with existing multipliers to prove the momentous development in competence and high speed operation. This efficient multiplier is implemented in the proposed factorial architecture which significantly reduces the path delay and provides better optimization.

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SM, Vijaya, and Suresh K. "An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (August 1, 2019): 2433. http://dx.doi.org/10.11591/ijece.v9i4.pp2433-2442.

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In digital image processing, the compression mechanism is utilized to enhance the visual perception and storage cost. By using hardware architectures, reconstruction of medical images especially Region of interest (ROI) part using Lossy image compression is a challenging task. In this paper, the ROI Based Discrete wavelet transformation (DWT) using separate Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM) methods are designed. The Lifting based DWT method is used for the ROI compression and reconstruction. The 9/7 filter coefficients are multiplied in DWT using Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM). The designed Wallace tree multiplier works with the parallel mechanism using pipeline architecture results with optimized hardware resources, and 8x8 Vedic multiplier designs improves the ROI reconstruction image quality and fast computation. To evaluate the performance metrics between ROI Based DWT-WM and DWT-VM on FPGA platform, The PSNR and MSE are calculated for different Brain MRI images, and also hardware constraints include Area, Delay, maximum operating frequency and power results are tabulated. The proposed model is designed using Xilinx platform using Verilog-HDL and simulated using ModelSim and Implemented on Artix-7 FPGA device.

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Prof. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device." International Journal of New Practices in Management and Engineering 6, no. 01 (March 31, 2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.

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Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.

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Jhamb, Mansi, and Manoj Kumar. "Optimized vedic multiplier using low power 13T hybrid full adder." Journal of Information and Optimization Sciences 44, no. 4 (2023): 675–87. http://dx.doi.org/10.47974/jios-1222.

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The research paper detects a modified version of the Vedic multiplier by using the sutras of Vedic mathematics by implementing a 13T hybrid full adder. A conventional multiplier is considered for comparative analysis of existing Vedic versions and a modified Vedic multiplier that better reflects the timing and usage of the device. This technology was developed and implemented by EDA. The proposed 13T hybrid full adder is achieved to reduce the static power consumption by 12.12 % and dynamic power consumption by 15.7%. The modified Vedic multiplier is implemented by using a 13T hybrid full adder which is achieved to reduce the power consumption by 10.08% and delay by 2.068%. The circuit and simulation are executed for 4-bit multiplication and can be performed in Eight-bit, Sixteen-bit or Thirty-two-bit. Results of simulation are shown only in the Vedic 4-bit multiplication technique. The results of this multiplication method are compared with existing techniques of Vedic multiplicative circuits.

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CVS, Chaitanya, Sundaresan C, and P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

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Gowreesrinivas, K. V., Sabbavarapu Srinivas, and Punniakodi Samundiswary. "FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders." Engineering, Technology & Applied Science Research 13, no. 3 (June 2, 2023): 10698–702. http://dx.doi.org/10.48084/etasr.5797.

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Nowadays, the requirement for very high-speed operations in processors constantly increases. Multiplication is a crucial operation in high power-consuming processes such as image and signal processing. The main characteristics of a multiplier are good accuracy, speed, reduction in area, and little power consumption. Speed plays a major role in multiplication operations, and an increase in speed can be obtained by reducing the number of steps involved in the computation process. Since a multiplier has the largest delay among the basic blocks in a digital system, the critical path is determined by it. Furthermore, the multiplier consumes more area and dissipates more power. Hence, designing multipliers that offer high speed, lower power consumption, less area, or a combination of them is of prime concern. Hence, an attempt is made in this paper to achieve the above design metrics using a Spurious Power Suppression Technique (SPST) adder. A resource-efficient SPST-based Vedic multiplier is developed and implemented using Artix 7 FPGA and is finally compared with the ripple carry adder-based Vedic multiplier.

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Paradhasaradhi, Damarla, Bharinala Haridhar, A. V. Sreekanth Reddy, Dudipalli Sri Charan, and Atyam Lekhaz. "Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 626. http://dx.doi.org/10.14419/ijet.v7i2.7.10895.

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Convolution is an algorithm which is mainly used in video, audio and image processing. Convolution calculation is simple in steps however it consumes a lot of memory as well as power in the computational process. It is a mathematical algorithm which is also used in the applications like filtering, edge detection, de-noising, compression etc., as it can be exploit computational power. In this paper, we implemented the speed of discrete linear convolution using robust Vedic multiplier which is one of the fastest multipliers with two finite-length sequences. By implementing convolution with Vedic multiplier power, area and delay are reduced. This implementation process can be realized by simplifying the convolution building block.

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Sharma, Vaishali. "Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths." International Journal for Research in Applied Science and Engineering Technology 10, no. 1 (January 31, 2022): 24–30. http://dx.doi.org/10.22214/ijraset.2022.39759.

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Abstract: This paper proposed the layout of Vedic Multiplier based totally on Urdhva Trigbhyam approach of multiplication. It is most effective Vedic sutras for multiplication. Urdhva triyagbhyam is a vertical and crosswise approach to discover product of two numbers. Multiplication is an essential quintessential feature in arithmetic logic operation. Computational overall performance of a DSP device is limited via its multiplication overall performance and since, multiplication dominates the execution time of most DSP algorithms. Multiplication is one of the simple arithmetic operations and it requires extensively extra hardware assets and processing time than addition and subtraction. Our work is to compare different bit Vedic multiplier structure using carry look ahead adder technique. Keywords: Carry Look Ahead Adder, Urdhva Trigbhyam, DSP algorithms, Vedic Multiplier

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Kunchigik, Vaijyanath, Linganagouda Kulkarni, and Subhash Kulkarni. "Pipelined Vedic-Array Multiplier Architecture." International Journal of Image, Graphics and Signal Processing 6, no. 6 (May 8, 2014): 58–64. http://dx.doi.org/10.5815/ijigsp.2014.06.08.

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Kivi Sona, M., and V. Somasundaram. "Vedic Multiplier Implementation in VLSI." Materials Today: Proceedings 24 (2020): 2219–30. http://dx.doi.org/10.1016/j.matpr.2020.03.748.

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Prabhu, E., H. Mangalam, and P. R. Gokul. "A Delay Efficient Vedic Multiplier." Proceedings of the National Academy of Sciences, India Section A: Physical Sciences 89, no. 2 (February 9, 2018): 257–68. http://dx.doi.org/10.1007/s40010-017-0464-4.

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Kumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi, and K. Hari Kishore. "Bit wise and delay of vedic multiplier." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.

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The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

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Manikrao, Kaustubh, and Mahesh Shrikant. "Analysis of Array Multiplier and Vedic Multiplier using Xilinx." Communications on Applied Electronics 5, no. 1 (May 24, 2016): 13–16. http://dx.doi.org/10.5120/cae2016652140.

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Eshack, Ansiya, and S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier." Indonesian Journal of Electrical Engineering and Computer Science 16, no. 3 (December 1, 2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.

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With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.

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Yadav, Jatin, Anupam Kumar, Shaik Shareef, Sandeep Bansal, and Navjot Rathour. "Comparative Analysis of Vedic Multiplier using Various Adder Architectures." Journal of Physics: Conference Series 2327, no. 1 (August 1, 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2327/1/012022.

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Abstract The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, different adder topologies like Carry Look ahead Adder, Kogge Stone Adder, Carry Skip Adder are used to compare area, delay and power. The reviewed methods are implemented on 45nanometer(nm), 90nm and 180 nm CMOS technology. The results of all the prior approaches are reviewed and an efficient method out of them has been proposed.

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Bhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.

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In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite.

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Bhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.

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In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite.

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Prasad, M. V. Tejendra. "Development and Realization of a 4x4 Vedic Multiplier Utilizing Cadence Platform." Journal of VLSI Design and Signal Processing 9, no. 2 (August 4, 2023): 39–51. http://dx.doi.org/10.46610/jovdsp.2023.v09i02.004.

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This study presents a pioneering approach to designing a Vedic multiplier using full adders and conducts a comprehensive power analysis to assess its energy efficiency. Vedic mathematics, rooted in ancient Indian principles, offers innovative techniques for rapid and precise computations. Leveraging these principles, we propose a Vedic multiplier architecture that exploits full adders as fundamental building blocks, enabling efficient multiplication operations through the Gate Diffusion Input (GDI) method. The thorough power analysis ensures a comprehensive evaluation of its energy-saving potential. This research aims to explore how Vedic mathematics can offer alternative and energy-efficient solutions for modern computational systems, particularly in performing multiplication operations. By embracing this novel methodology, we aspire to unlock new possibilities for efficient and sustainable computing paradigms.

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., Uttara Bhatt. "HIGH SPEED MULTIPLIER USING VEDIC MATHEMATICS." International Journal of Research in Engineering and Technology 03, no. 01 (January 25, 2014): 548–52. http://dx.doi.org/10.15623/ijret.2014.0301092.

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Hari Kishore, K., Fazal Noorbasha, Katta Sandeep, D. N. V. Bhupesh, SK Khadar Imran, and K. Sowmya. "Linear convolution using UT Vedic multiplier." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.8.10471.

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Linear Convolution is one of the elemental operations of Signal processing systems and is used by some Multiplication Algorithms. In our project we perform Linear Convolution using ancient Multiplication Algorithm called UrdhvaTriyagbhyam (UT) which is one among the 16 sutras in Vedic mathematics. This provides best results in speed when compared to other multipliers. UrdhvaTriyagbhyam technique is used to increase the timing performance of the design. Our aim is to design 8 bit convolution using UT. The synthesis and simulation is done by using XILINX ISE Design.

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Ramalakshmanna, Y., V. Yaswanth Varma, Phani Sai Kumar, and T. Nalini Prasad. "Modified Vedic Multiplier Using CSLA Adders." Journal of Computational and Theoretical Nanoscience 16, no. 4 (April 1, 2019): 1255–69. http://dx.doi.org/10.1166/jctn.2019.8028.

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Sharma, Nitesh Kumar, Deepesh Kumar Gautam, and M. R. Khan. "Vedic Mathematics Implementation in Multiplier Units." Journal of Computer and Mathematical Sciences 10, no. 5 (May 30, 2019): 997–1003. http://dx.doi.org/10.29055/jcms/1083.

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NivasA, Sree, and Kayalvizhi N. "Implementation of Power Efficient Vedic Multiplier." International Journal of Computer Applications 43, no. 16 (April 30, 2012): 21–24. http://dx.doi.org/10.5120/6188-8673.

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Vikas, Om, Deepak Gupta, Aneesh Bhasin, and Sonu Arora. "Vedic Multiplier with Fast Carry Optimization." IETE Journal of Research 51, no. 4 (July 2005): 327–31. http://dx.doi.org/10.1080/03772063.2005.11416411.

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Ariafar, Zahra, and Mohammad Mosleh. "Effective Designs of Reversible Vedic Multiplier." International Journal of Theoretical Physics 58, no. 8 (May 24, 2019): 2556–74. http://dx.doi.org/10.1007/s10773-019-04145-0.

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Et. al., Srilakshmi Kaza,. "Performance Analysis of Adiabatic Vedic Multipliers." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 1429–35. http://dx.doi.org/10.17762/turcomat.v12i5.2039.

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Energy dissipation and reliability are the two important design constraints in the high performance processor design. With the advancements in the IC manufacturing and reduced feature sizes the energy dissipation increases in exponential manner at the lower technology nodes. So, there is a need to design energy-efficient and reliable circuits and systems. The reliability with temperature is also one of the major challenges in today’s smart systems as they are operated in harsh environments. Most of the works till date analyzed the reliability with respect to DC constraints. The basic operation in the high performance Digital Signal Processing (DSP) is the multiplication is used to simplify various operations like convolution, filtering and correlation. In this work, a Vedic multiplier with 4x4 size is implemented with FinFET based energy recovery Modified PFAL (MPFAL) logic at 45 nm technology node. The designed multiplier performance is analyzed and compared with our earlier work in terms of energy dissipation and delay. The results indicate a reduction of 55% in energy dissipation over ECRL based Vedic multiplier. Linear variation of power dissipation with temperature in the order of pW shows that design MPFAL Vedic muliplier is more reliable compared to CMOS multiplier.

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Sharma, Sandesh, and Vangmayee Sharda. "Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 759. http://dx.doi.org/10.14419/ijet.v7i3.12.16496.

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Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less complex than circuits designed by other techniques.

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Kanda, Guard, and Kwangki Ryoo. "Vedic Multiplier-based International Data Encryption Algorithm Crypto-Core for Efficient Hardware Multiphase Encryption Design." Webology 19, no. 1 (January 20, 2022): 4581–96. http://dx.doi.org/10.14704/web/v19i1/web19304.

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At present, there are several pieces of research on designing and implementing new cryptographic algorithms that are lightweight and resistant to several, if not major forms of security attacks. However, some algorithms such as the International Data Encryption Algorithm (IDEA), which has been around for some time is yet to record any real threat against its functionality. To ensure its continued usage, current implementations rely on multiphase encryption where it is combined with other algorithms such as ROTation (ROT) and Data Encryption Standard (DES) for maximum security strength. Multiphase encryption implies that there is a tendency for an increase in hardware area and a reduction in overall speed. In such cases, having fast and reduced area algorithms are much desired. This paper, therefore, proposes an efficient hardware implementation of the IDEA cipher that is based on arithmetic modulo multiplication—one of the main computations of the IDEA—on a novel Vedic multiplier architecture. The increase in efficiency of the IDEA crypto architecture and the reduction in resources utilization is achieved through an enhancement of its structural architecture to utilize a fixed set of resources for all eight identical rounds of computation and the use of a proposed fast and lightweight Vedic hardware multiplier. The proposed hardware modification and resulting architecture are designed using the Xilinx ISE and Vivado tools. The architecture is synthesized using Precision Synthesis Tool (PS) and simulated using Modelsim SE 10.6d and ISIM simulation tools. The proposed IDEA cipher is 100% more efficient when designed based on the Vedic multiplier compared to existing designs. The hardware architecture is implemented on Spartan-6-FGG484 Field Programmable Gate Array (FPGA) using Verilog HDL. Verified results show that the proposed Vedic-based IDEA occupied 212 Slices with the Vedic multiplier only occupying 28 Slices out of the total 212. The proposed architecture operates at a maximum frequency of 253.3 MHz.

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Deokate, Rajesh. "A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 20, 2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.

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The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

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Kunchigi, Vaijyanath, Linganagouda Kulkarni, and Subhash Kulkarni. "Simulation of Vedic Multiplier in DCT Applications." International Journal of Computer Applications 63, no. 16 (February 15, 2013): 27–32. http://dx.doi.org/10.5120/10552-5744.

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M C, Pradeep, and Dr Ramesh S. "Optimized high performance multiplier using Vedic mathematics." IOSR journal of VLSI and Signal Processing 4, no. 5 (2014): 06–11. http://dx.doi.org/10.9790/4200-04510611.

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Nittala, Vijay Bhaskar, Anisha Bomma, and M. Ramana Reddy. "Energy Efficient Approximate 8-bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 10, no. 9 (September 30, 2022): 1453–65. http://dx.doi.org/10.22214/ijraset.2022.46861.

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Abstract: The digital signal processing and its classification applications on the energy constrained devices should be supported based on efficiency. Because such applications must perform highly complex computations especially complex multiplication processes while exhibiting tolerance for a large amount of noise and for computational errors too. So, comparing all the arithmetic computations, improving the energy efficiency of multiplication is critical. In this project, an energy efficient approximate 8-bit Vedic multiplier is proposed which gives a tradeoff between computational accuracy and energy consumption. The proposed architecture has reduced area compared to other multiplier architectures which process same number of bits. The reduced architecture area reduces the power consumption. Also, the Vedic technology adopted for the multiplication reducesthe delay further. But the approximate architecture output possesses a small amount of computational accuracy which is negligible for DSP applications.

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Rashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "Designing of Parity Preserving Reversible Vedic Multiplier." International Journal of Theoretical Physics 60, no. 8 (July 13, 2021): 3024–40. http://dx.doi.org/10.1007/s10773-021-04903-z.

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Suryavanshi, Ravindra, and Sweta Khare. "An Efficient High-Performance Vedic Multiplier: Review." INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING AND MANAGEMENT 2, no. 3 (March 1, 2017): 60. http://dx.doi.org/10.24999/ijoaem/02030017.

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Narendra, K., and Sagara Pandu. "Low Power Area-Efficient Adiabatic Vedic Multiplier." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, no. 08 (August 20, 2014): 11027–32. http://dx.doi.org/10.15662/ijareeie.2014.0308018.

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Sahu, Satya Ranjan, Bandan Kumar Bhoi, and Manoranjan Pradhan. "Fast signed multiplier using Vedic Nikhilam algorithm." IET Circuits, Devices & Systems 14, no. 8 (November 1, 2020): 1160–66. http://dx.doi.org/10.1049/iet-cds.2019.0537.

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Vadiraj, G., K. Shivanand, B. Sampat, and G. Subramanya Nayak. "Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 1 (May 28, 2018): 36. http://dx.doi.org/10.11591/ijres.v6.i1.pp36-40.

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Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.

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Kumar V G, Kiran, and Shantharama Rai C,. "Low Power High Speed Arithmetic Circuits." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (July 30, 2019): 807–13. http://dx.doi.org/10.35940/ijrte.a1064.078219.

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In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (September 1, 2021): 505–11. http://dx.doi.org/10.6036/10214.

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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

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Journal articles on the topic 'VEDIC MULTIPLIER'

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