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Journal articles on the topic 'Variable gain power amplifier'

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Published: 7 July 2024

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1

Choi, Ye-Ji, and Jee-Youl Ryu. "Design of Low-Power Variable Gain Amplifier." Journal of Institute of Control, Robotics and Systems 28, no. 1 (January 31, 2022): 1–5. http://dx.doi.org/10.5302/j.icros.2022.21.0138.

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2

Zhang, Jing Zhi. "A 520MHz Wideband Variable Gain Amplifier." Applied Mechanics and Materials 556-562 (May 2014): 1564–67. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1564.

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The design and realization of a wideband variable gain amplifier for RF system is presented. The cascade of LNA and controllable attenuation makes the design have a 0-90dB gain adjustment range. Special care is devoted to the solution of typical problems encountered in the design of the amplifier, such as signal shielding and power supply decoupling. The amplifier uses passive amplitude-frequency equalization, 0.1-460MHz band variation is less than 1dB, the 3dB bandwidth is up to 520MHz. The noise characteristic is low, the total input referred noise is less than 15.5nV⁄√¯Hz.

3

Fujimoto, Y., H. Tani, M. Maruyama, H. Akada, H. Ogawa, and M. Miyamoto. "A low-power switched-capacitor variable gain amplifier." IEEE Journal of Solid-State Circuits 39, no. 7 (July 2004): 1213–16. http://dx.doi.org/10.1109/jssc.2004.829919.

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4

Vintola, V. T. S., M. J. Matilainen, S. J. K. Kalajo, and E. A. Jarvinen. "Variable-gain power amplifier for mobile WCDMA applications." IEEE Transactions on Microwave Theory and Techniques 49, no. 12 (2001): 2464–71. http://dx.doi.org/10.1109/22.971637.

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5

Huang, Yan-Yu, Wangmyong Woo, Hamhee Jeon, Chang-Ho Lee, and J. Stevenson Kenney. "Compact Wideband Linear CMOS Variable Gain Amplifier for Analog-Predistortion Power Amplifiers." IEEE Transactions on Microwave Theory and Techniques 60, no. 1 (January 2012): 68–76. http://dx.doi.org/10.1109/tmtt.2011.2175234.

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6

Quoc-Hoang Duong, Quan Le, Chang-Wan Kim, and Sang-Gug Lee. "A 95-dB linear low-power variable gain amplifier." IEEE Transactions on Circuits and Systems I: Regular Papers 53, no. 8 (August 2006): 1648–57. http://dx.doi.org/10.1109/tcsi.2006.879058.

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7

Xie, Hongyun, Shuo Liu, Lianghao Zhang, Zhiyun Jiang, Yanxiao Zhao, Liang Chen, and Wanrong Zhang. "Low power dissipation SiGe HBT dual-band variable gain amplifier." Microelectronics Journal 46, no. 7 (July 2015): 626–31. http://dx.doi.org/10.1016/j.mejo.2015.03.007.

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8

Kang, So Young, Jooyoung Jang, Inn-Yeal Oh, and Chul Soon Park. "A 2.16 mW Low Power Digitally-Controlled Variable Gain Amplifier." IEEE Microwave and Wireless Components Letters 20, no. 3 (March 2010): 172–74. http://dx.doi.org/10.1109/lmwc.2010.2040222.

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9

Tang, Fang, Amine Bermak, Amira Abbes, and Mohieddine Amor Benammar. "Continuous-TimeΣΔADC with Implicit Variable Gain Amplifier for CMOS Image Sensor." Scientific World Journal 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/208540.

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This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

10

Kledrowetz, Vilem, Roman Prokop, Lukas Fujcik, Michal Pavlik, and Jiří Háze. "Low-power ASIC suitable for miniaturized wireless EMG systems." Journal of Electrical Engineering 70, no. 5 (September 1, 2019): 393–99. http://dx.doi.org/10.2478/jee-2019-0071.

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Abstract Nowadays, the technology advancements of signal processing, low-voltage low-power circuits and miniaturized circuits have enabled the design of compact, battery-powered, high performance solutions for a wide range of, particularly, biomedical applications. Novel sensors for human biomedical signals are creating new opportunities for low weight wearable devices which allow continuous monitoring together with freedom of movement of the users. This paper presents the design and implementation of a novel miniaturized low-power sensor in integrated circuit (IC) form suitable for wireless electromyogram (EMG) systems. Signal inputs (electrodes) are connected to this application-specific integrated circuit (ASIC). The ASIC consists of several consecutive parts. Signals from electrodes are fed to an instrumentation amplifier (INA) with fixed gain of 50 and filtered by two filters (a low-pass and high-pass filter), which remove useless signals and noise with frequencies below 20 Hz and above 500 Hz. Then signal is amplified by a variable gain amplifier. The INA together with the reconfigurable amplifier provide overall gain of 50, 200, 500 or 1250. The amplified signal is then converted to pulse density modulated (PDM) signal using a 12-bit delta-sigma modulator. The ASIC is fabricated in TSMC0.18 mixed-signal CMOS technology.

11

Motamed, A., Changku Hwang, and M. Ismail. "A low-voltage low-power wide-range CMOS variable gain amplifier." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 7 (July 1998): 800–811. http://dx.doi.org/10.1109/82.700927.

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12

Liao, Hsien-Yuan, Kuan-Yu Chen, Joseph D. S. Deng, and Hwann-Kaeo Chiou. "0.35-μm SiGe BiCMOS variable-gain power amplifier for WiMAX transmitters." Microwave and Optical Technology Letters 49, no. 11 (2007): 2750–53. http://dx.doi.org/10.1002/mop.22851.

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13

Iji, Ayobami, Xi Zhu, and Michael Heimlich. "High gain/power quotient variable-gain wideband low-noise amplifier for capsule endoscopy application." Microwave and Optical Technology Letters 54, no. 11 (August 24, 2012): 2563–65. http://dx.doi.org/10.1002/mop.27111.

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14

Lahiani, Sawssen, Samir Ben Salem, Houda Daoud, and Mourad Loulou. "A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850135. http://dx.doi.org/10.1142/s0218126618501359.

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This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and designed for a cognitive radio receiver. The variable-gain amplifier (VGA) proposed consists of a digital control block, an auxiliary pair to retain a constant current density, and offers a gain-independent bandwidth (BW). A novel cell structure is designed for high gain, high BW, low power consumption and low Noise Figure (NF). The Heuristic Method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18[Formula: see text][Formula: see text]m CMOS process. Simulation results show that the DVGA can provide a gain variation range of 54[Formula: see text]dB (from 54[Formula: see text]dB to 0[Formula: see text]dB) with a 3[Formula: see text]dB BW over more than 110[Formula: see text]MHz. The circuit consumes the maximum power of 0.65[Formula: see text]mW from a 1.8[Formula: see text]V supply.

15

Arbet, Daniel, Viera Stopjaková, Martin Kováč, Lukáš Nagy, Matej Rakús, and Michal Šovčík. "130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications." Journal of Circuits, Systems and Computers 26, no. 08 (April 11, 2017): 1740003. http://dx.doi.org/10.1142/s0218126617400035.

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In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility to operate with low supply voltage. Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no risk of latch-up event that usually represents the main drawback of the BD circuit systems. BD transistors are employed in the input differential stage, which makes it possible to operate in rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide scale, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications. An additional circuit responsible for maintaining the linear-in-decibel gain dependency of the VGA is also addressed. The proposed circuit block avails arbitrary shaping of the curve characterizing the gain versus the controlling voltage dependency.

16

Alam, M. J., Mohammad Arif Sobhan Bhuiyan, Md Torikul Islam Badal, Mamun Bin Ibne Reaz, and Noorfazila Kamal. "Design of a low-power compact CMOS variable gain amplifier for modern RF receivers." Bulletin of Electrical Engineering and Informatics 9, no. 1 (February 1, 2020): 87–93. http://dx.doi.org/10.11591/eei.v9i1.1468.

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The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design achieves the widest bandwidth of 200 MHz and high gain range from -33 to 32 dB. The VGA dissipates only 2mW from a single 1.2 V DC supply. The core chip area of the VGA is also only 0.026 mm2 which is also the lowest compared to recent researches. Such a VGA will be a very useful module for all modern communication devices.

17

Semsar Parapari, Ehsan, Elmira Semsar Parapari, Ziaddin Daie Koozehkanani, and Siroos Toofan. "A low power 102 dB Reconfigurable Variable Gain Amplifier for Multistandard Receivers." AEU - International Journal of Electronics and Communications 132 (April 2021): 153631. http://dx.doi.org/10.1016/j.aeue.2021.153631.

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18

Nguyen, H. H., Q. H. Duong, H. B. Le, J. S. Lee, and S. G. Lee. "Low-power 42 dB-linear single-stage digitally-controlled variable gain amplifier." Electronics Letters 44, no. 13 (2008): 780. http://dx.doi.org/10.1049/el:20081269.

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19

Chen, Zhiming, Yuanjin Zheng, Foo Chung Choong, and Minkyu Je. "A Low-Power Variable-Gain Amplifier With Improved Linearity: Analysis and Design." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 10 (October 2012): 2176–85. http://dx.doi.org/10.1109/tcsi.2012.2185331.

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20

Sánchez‐Rodríguez, Trinidad, Juan Antonio Galán, Manuel Pedro, Antonio J. López‐Martín, Ramon G. Carvajal, and Jaime Ramírez‐Angulo. "Low‐power CMOS variable gain amplifier based on a novel tunable transconductor." IET Circuits, Devices & Systems 9, no. 2 (March 2015): 105–10. http://dx.doi.org/10.1049/iet-cds.2014.0130.

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21

Ma, Dongsheng, Chen Zheng, Hio Leong Chao, and Mike Koen. "Integrated low-power CMFB-free variable-gain amplifier for ultrasound diagnostic applications." Analog Integrated Circuits and Signal Processing 61, no. 2 (March 13, 2009): 171–79. http://dx.doi.org/10.1007/s10470-009-9296-8.

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22

Han, Jingyu, Yu Jiang, Guiliang Guo, and Xu Cheng. "A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process." Electronics 9, no. 5 (May 18, 2020): 831. http://dx.doi.org/10.3390/electronics9050831.

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A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

23

Xuelian, Zhang, Yan Jun, Shi Yin, and Dai Fa Foster. "5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end." Journal of Semiconductors 30, no. 1 (January 2009): 015008. http://dx.doi.org/10.1088/1674-4926/30/1/015008.

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24

ZIABAKHSH, SOHEYL, HOSEIN ALAVI-RAD, MORTEZA ALINIA AHANDANI, and MUSTAPHA C. E. YAGOUB. "DESIGN AND OPTIMIZATION OF A FULLY DIFFERENTIAL CMOS VARIABLE-GAIN LNA WITH DIFFERENTIAL EVOLUTION ALGORITHM FOR WLAN APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 09 (August 25, 2014): 1450124. http://dx.doi.org/10.1142/s0218126614501242.

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In this paper, we optimized the performance of a 2.4 GHz variable gain low-noise amplifier for WLAN applications which provides high dynamic range with relatively low power consumption. First, the differential evolution algorithm was used to optimize the width of input transistors, then the tunable on-chip switching stage method was applied to control the amplifier gain when the input signal increases. The optimization was performed in terms of gain, noise figure (NF), IIP3 and power dissipation. The LNA has achieved a variable gain from 16.55 to 20.45 dB with excellent NF between 1.63 and 1.74 dB. Furthermore, the proposed circuit achieves a third order input intercept point of 6.6 dBm. It consumes only 10 mW from a 1.5 V supply.

25

Lee, Samuel B. S., Hang Liu, Kiat Seng Yeo, Jer-Ming Chen, and Xiaopeng Yu. "Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS." Electronics 9, no. 7 (June 27, 2020): 1058. http://dx.doi.org/10.3390/electronics9071058.

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This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

26

DUONG, Q. H., C. W. KIM, and S. G. LEE. "All CMOS Low-Power Wide-Gain Range Variable Gain Amplifiers." IEICE Transactions on Electronics E91-C, no. 5 (May 1, 2008): 788–97. http://dx.doi.org/10.1093/ietele/e91-c.5.788.

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27

Duan, Ji Hai, and Chun Lei Kang. "A Fully Integrated 5.2-GHz CMOS Variable Gain LNA for 802.11a WLAN." Advanced Materials Research 433-440 (January 2012): 5579–83. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5579.

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A fully integrated 5.2GHz variable gain low noise amplifier (VGLNA) in a 0.18μm CMOS process is proposed in this paper. The VGLAN can achieve a maximum small signal gain of 17.85 dB within the noise figure (NF) of 2.04 dB and a minimum gain of 2.04 dB with good input return loss. The LNA’s P1dB in the high gain mode is -17.5 dBm. The LAN consumes only 14.58 mW from a 1.8V power supply.

28

Rahmatian, Behnoosh, and Shahriar Mirabbasi. "A low-power 75 dB digitally programmable variable-gain amplifier in 0.18μm CMOS." Canadian Journal of Electrical and Computer Engineering 32, no. 4 (2007): 181–86. http://dx.doi.org/10.1109/cjece.2007.4407663.

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29

van Lieshout, P. J. G., and R. J. van de Plassche. "A power-efficient, low-distortion variable gain amplifier consisting of coupled differential pairs." IEEE Journal of Solid-State Circuits 32, no. 12 (1997): 2105–10. http://dx.doi.org/10.1109/4.643668.

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30

Shin, Gibeom, Kyunghwan Kim, Kangseop Lee, Hyun-Hak Jeong, and Ho-Jin Song. "An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS." Electronics 10, no. 7 (March 29, 2021): 804. http://dx.doi.org/10.3390/electronics10070804.

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This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

31

Nam, Hyosung, Taejoo Sim, and Junghyun Kim. "A 2.4 GHz 20 W 8-channel RF Source Module with Solid-State Power Amplifiers for Plasma Generators." Electronics 9, no. 9 (August 26, 2020): 1378. http://dx.doi.org/10.3390/electronics9091378.

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This paper presents a novel multi-channel type RF source module with solid-state power amplifiers for plasma generators. The proposed module is consisted of a DC control part, RF source generation part, and power amplification part. A 2-stage power amplifier (PA) is combined with a gallium arsenide hetero bipolar transistor (GaAs HBT) as a drive PA and a gallium nitride high electron mobility transistor (GaN HEMT) as a main PA, respectively. By employing 8 channels, the proposed module secures better area coverage on the wafer during semiconductor processes such as chemical vapor deposition (CVD), etching and so on. Additionally, each channel can be maintained at a constant output power because they have a gain factor tunable by a variable gain amplifier (VGA). For that reason, it is possible to have uniform plasma density on the wafer. The operating sequence is controllable by an external DC control port. Moreover, copper–tungsten (CuW) heat spreaders were applied to prevent RF performance degradation from heat generated by the high power amplifier (HPA), and a water jacket was implemented at the bottom of the power amplification part for liquid cooling. Drawing upon the measurement results, the output power at each channel was over 43 dBm (20 W) and the drain efficiency was more than 50% at 2.4 GHz.

32

Bao, Jiazhen, Yifeng Cao, and Qian Huang. "Maximum gain optimization of thulium-doped fiber amplifier based on genetic algorithm for peak gain spectrum at 1800- 2000nm." Applied and Computational Engineering 10, no. 1 (September 25, 2023): 72–78. http://dx.doi.org/10.54254/2755-2721/10/20230143.

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The optical fiber amplifier doped with rare earth elements has the characteristics of high gain, high doping concentration and short length. Compared with other fiber optic systems, the fiber used is shorter, also known as lumped fiber amplifier. At present, Er, Pr, Tm, Nd and Yb doped fiber amplifiers and lasers are mainly studied more. To further extend the transmission distance, improve the transmission quality and increase the transmission capacity, it is very important for the research of fiber amplifier. In this research, using a two-level structure, we investigate the maximum of the peak gain of the gain spectrum of a thulium-doped broadband fiber amplifier in the 1800-2000 nm wavelength range. Signal gain is inversely proportional to fiber length, doping concentration, and pump power in both the absorption spectrum and the emission spectrum, as shown by the relationship diagram of signal gain with these variables. And through the genetic algorithm data optimization, we get that when the fiber length is 2.2 m, the maximum gain is 42.7 dB.

33

Wu, Junjie, and Jianhui Wu. "A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain." Electronics 9, no. 3 (March 19, 2020): 507. http://dx.doi.org/10.3390/electronics9030507.

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A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions.

34

Zhang, Wei Jia, and Bo Wang. "A SiGe HBT Variable Gain Amplifier for Wireless Receiver System with On-Chip Filter." Applied Mechanics and Materials 155-156 (February 2012): 167–70. http://dx.doi.org/10.4028/www.scientific.net/amm.155-156.167.

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A using SiGe HBT variable gain amplifier (VGA) with filtering for wireless receiver system is presented in this paper. The VGA consists of three stages. The first stage is the gain control stage, and the second stage is the fixed gain stage. The third is the GM-C filter. The VGA is driven by a 3.3-V power supply, and linear gain control range varying is from 26 dB to 62dB. When control voltage varies from 0 to 1.8V. The input 1-dB compression point is -4dBm at minimum gain. The VGA is fabricated in a 0.5 μm = 80GHz and =90GHz silicon germanium heterojunction transistor technology.

35

Kumar, Vijay, and Sujatha Ravichandran. "A Low Noise Variable Gain Amplifier with 97.2 dB Linear Gain Range for CW Radar." Defence Science Journal 74, no. 01 (October 26, 2023): 85–90. http://dx.doi.org/10.14429/dsj.74.19149.

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This manuscript reports the design of a low noise variable gain amplifier (VGA) having wide dB linear gain characteristics for a continuous wave (CW) radar. A pseudo-exponential gain control function has been adopted in this VGA for the wide dB-linear behavior. Also, a BJT-based gain stage has been proposed to improve the gain dynamic range and low noise performance due to its higher transconductance/gain and lower flicker noise contribution. This proposed 2-gain stage VGA has been implemented in 130 nm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) technology. This design performance has been benchmarked by post-layout simulation results. It has demonstrated a voltage-controlled gain from -33.6 dB to 74.4 dB (total 108 dB), with a 97.2 dB linear gain range, input referred noise of 2.4 nV /√Hz, and power consumption of 4.25 mW. This VGA has a 3-dB bandwidth of 10 MHz at a maximum gain of 74.4 dB and 251 MHz at a minimum gain of -33.6 dB with a chip layout area of 0.0682 mm2 . Compared to the latest available CMOS/BiCMOS VGAs in the literature, this proposed VGA has the highest gain dynamic range and dB-linear gain range with minimum input referred noise simultaneously across the operation bandwidth.

36

Jazayeri, Farzan, Behjat Forouzandeh, and Farshid Raissi. "Low-power variable gain amplifier with wide UGBW based on nanoscale Field Effect Diode." IEICE Electronics Express 6, no. 1 (2009): 51–57. http://dx.doi.org/10.1587/elex.6.51.

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37

Ma, Rui, Maliang Liu, Hao Zheng, and Zhangming Zhu. "A 77-dB Dynamic Range Low-Power Variable-Gain Transimpedance Amplifier for Linear LADAR." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 2 (February 2018): 171–75. http://dx.doi.org/10.1109/tcsii.2017.2684822.

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38

Rivetti, A. "A low-power variable-gain front-end amplifier in a 0.25 μm CMOS technology." IEEE Transactions on Nuclear Science 50, no. 4 (August 2003): 948–54. http://dx.doi.org/10.1109/tns.2003.815131.

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39

Lahiani, Sawssen, Houda Daoud, Samir Ben Salem, and Mourad Loulou. "Low power CMOS variable gain amplifier design for a multistandard receiver WLAN/WIMAX/LTE." Analog Integrated Circuits and Signal Processing 101, no. 2 (July 26, 2019): 255–65. http://dx.doi.org/10.1007/s10470-019-01509-8.

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Lee, Lini, Roslina Mohd Sidek, Sudhanshu Shekhar Jamuar, and Sabira Khatun. "Cascode Current Mirror for a Variable Gain Stage in a 1.8 GHz Low Noise Amplifier (LNA)." ECTI Transactions on Electrical Engineering, Electronics, and Communications 6, no. 1 (January 25, 2007): 47–52. http://dx.doi.org/10.37936/ecti-eec.200861.171760.

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A high frequency CMOS variable gain low noise amplifier (VGLNA) constructed based on an inductive source degenerated LNA and a cascode current mirror is proposed. The 'variable' concept is to prevent the unwanted saturation phenomenon due to large input signal. A cascode current mirror cell which consumes minimal voltage headroom without sacrificing the accuracy of the circuit is proposed in the circuit. With a 0.18 m CMOS technology, this technique is applied on a VGLNA operating at 1.8 GHz for GSM band application. The simulation results reveal that the maximum gain is 17.29 dB with gain tuning range of 9.56 dB. The noise ¯gure (NF) is less than 0.92 dB with the power consumption of 9.34 mW at power supply of 1.8 V. Comparison with several same operating frequency LNA circuits published show that this work demonstrated among the lowest NF and highest IIP3 with compromise on the gain.

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Zhao, Yinan, Jinwu Zhuang, Zhihao Ye, Zhiliang Qian, and Fang Peng. "Simulation of Steady-State Temperature Rise of Electric Heating Field of Wireless Sensor Circuit Fault Current Trigger." Journal of Sensors 2021 (September 30, 2021): 1–11. http://dx.doi.org/10.1155/2021/8359504.

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This article analyzes the structure of the wireless sensor circuit, considering the balance of power consumption, integration, area, noise, etc., and adopts a radio frequency wireless sensor circuit with a low-IF structure. Through the analysis and comparison of traditional analog current trigger and digital current trigger structure, the feed-forward current trigger structure is selected, which is composed of received signal strength indicator (RSSI) and variable gain amplifier (VGA), which achieves low power consumption, fast stabilization time, and wide dynamic range design. The received signal strength indicator adopts the form of approximate logarithmic amplifier, five-stage double feedback loop structure, and realizes lower power consumption. In order to prevent the load current trigger from entering the speed saturation zone, a gain unit structure in which the superimposed current trigger is connected to the NMOS tube as the load is proposed. The test results show that the circuit has a good power consumption performance (1 mW) and at the same time 56.8 dB/m sensitivity. In this paper, through the analysis of the current trigger system and the analysis and comparison of the existing variable gain amplifiers, the variable gain amplifier structure composed of the folded wireless sensing unit and the index control unit is adopted. In order to reduce the power consumption of the circuit and increase the output swing, a structure in which the two-stage folding wireless sensor unit shares the controlled voltage-to-current part of the circuit is proposed. Aiming at the design requirements of the system, this article discussed in detail the architecture of the entire temperature measurement node and the design parameters of the chip and completed the overall architecture design of the chip. The simulation results of the steady-state temperature rise of the electric heating field show that the circuit has achieved an input dynamic adjustment range of more than 60 dB, the maximum power consumption is 1 mW, and the linearity error is less than 0.5 dB. The designed automatic gain control circuit is implemented in SMIC 0.18 cape CMOS process. The simulation results of the steady-state temperature rise of the electric heating field show that the circuit has a 56 dB input dynamic adjustment range within a linear error of 1.25 dB, and the time constant is 7.55 ms, and power consumption is 2.84 mW. Through the steady-state temperature rise simulation and test results of the electric heating field, the correctness of the design is verified and it meets the system requirements.

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del Pino, J., Sunil L. Khemchandani, D. Galante-Sempere, and C. Luján-Martínez. "A Compact Size Wideband RF-VGA Based on Second Generation Controlled Current Conveyors." Electronics 9, no. 10 (September 30, 2020): 1600. http://dx.doi.org/10.3390/electronics9101600.

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This paper presents a methodology to design a wideband radio frequency variable gain amplifier (RF-VGA) in a low-cost SiGe BiCMOS 0.35 μm process. The circuit uses two Class A amplifiers based on second-generation controlled current conveyors (CCCII). The main feature of this circuit is the wideband input match along with a reduced NF (5.5–9.6 dB) and, to the authors’ knowledge, the lowest die footprint reported (62 × 44 μm2 area). The implementation of the RF-VGA based on CCCII allows a wideband input match without the need of passive elements. Due to the nature of the circuit, when the gain is increased, the power consumption is reduced. The architecture is suitable for designing wideband, low-power, and low-noise amplifiers. The proposed design achieves a tunable gain of 6.7–18 dB and a power consumption of 1.7 mA with a ±1.5 V DC supply. At maximum gain, the proposed RF-VGA covers from DC up to 1 GHz and can find application in software design radios (SDRs), the low frequency medical implant communication system (MICS) or industrial, scientific, and medical (ISM) bands.

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Zhang, Da Hui, Ze Dong Nie, Feng Guan, and Lei Wang. "An Energy-Efficient Receiver for Human Body Communication." Applied Mechanics and Materials 195-196 (August 2012): 84–89. http://dx.doi.org/10.4028/www.scientific.net/amm.195-196.84.

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A low-power, wideband signaling receiver for data transmission through a human body was presented in this paper. The receiver utilized a novel implementation of energy-efficient wideband impulse communication that uses the human body as the transmission medium, provides low power consumption, high reception sensitivity. The receiver consists of a low-noise amplifier, active balun, variable gain amplifier (VGA) Gm-C filter, comparator, and FSK demodulator. It was designed with 0.18um CMOS process in an active area of 1.54mm0.414mm. Post-simulation showed that the receiver has a gain range of-2dB~40dB. The receiver consumes 4mW at 1.8V supply and achieves transmission bit energy of 0.8nJ/bit.

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Togawa, Kazuaki, Hirokazu Maesaka, Reichiro Kobana, and Hitoshi Tanaka. "Frequency-segmented power amplification using multi-band radio frequency amplifiers to produce a high-voltage pulse." Review of Scientific Instruments 93, no. 7 (July 1, 2022): 073304. http://dx.doi.org/10.1063/5.0093915.

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A method of frequency-segmented power amplification using multiband radio frequency (RF) amplifiers was proposed to generate stable and arbitrary high-voltage pulses. The concept behind this method is that an arbitrary pulse with a specified duration and sharp edges can be reconstructed using only several frequencies, and most of the power is concentrated on the fundamental frequency. The high-voltage pulse can, therefore, be obtained by amplifying each segmented frequency and then combining it with the RF power combiners. To correct the frequency-dependent group delays and gain of the amplifier circuit and to perform fine-tuning of the pulse structure, a seed pulse is divided into several lines that have bandpass filters, variable delay lines, variable power attenuators, and main RF amplifiers. A prototype pulse amplifier was designed and fabricated based on this method to generate rectangular pulses for the electron beam chopper of an x-ray free-electron laser injector. Flat and stable pulses with a 2 ns width of 0.2 kV height, peak-to-peak flat top of 0.8%, and route-mean-squared peak jitter of less than 0.2% were successively generated in both single- and multi-bunch structures. In the future, this type of pulse generator will play an important role in accelerators that require complicated and precise beam handling at high repetition rates of kHz or MHz.

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Nam, Hyungseok, Dang-An Nguyen, Yanghyun Kim, and Chulhun Seo. "Design of 6 GHz Variable-Gain Low-Noise Amplifier Using Adaptive Bias Circuit for Radar Receiver Front End." Electronics 12, no. 9 (April 27, 2023): 2036. http://dx.doi.org/10.3390/electronics12092036.

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This paper presents a variable-gain low-noise amplifier (VGLNA) based on an adaptive bias (ADB) circuit for the radar receiver front end. The ADB circuit processes the signal separated by a coupler at the LNA output port. First, the ADB circuit rectifies the coupled signal into positive DC voltage through a rectifier, which is then inverted to control a junction-gate field-effect transistor (JFET). The voltage-controlled current of JFET flows through a voltage-divider network and finally produces the DC biasing voltage for the BJT base termination, which decreases with the increase in the input RF power. The proposed VGLNA operates automatically in high gain at low input power and low gain at high input power, providing a wider dynamic range as compared to the constant-bias counterpart. For validation, a prototype is fabricated and measured at 6 GHz. As observed, the base biasing voltage generated by the ADB circuit is changed from 858 mV to 798 mV as the input power increases from −50 dBm to 0 dBm. As a result, the dynamic range represented by the input P1dB point (IP1dB) has an increase of 6.5 dB, while LNA still maintains a high gain of 15.15 dB at low input power.

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Chilukuri, Manu, Sungyong Jung, and Hoon-Ju Chung. "A Charge Amplifier Based Complementary Metal–Oxide–Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 315–22. http://dx.doi.org/10.1166/jolpe.2019.1615.

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In this paper, a low noise and low power analog front end for piezoelectric microphones used in hearing aid devices is presented. It consists of a Charge Amplifier, followed by a Variable Gain Amplifier and an Analog-to-Digital Converter. At the core of charge amplifier a two stage opamp with modified cascode current mirror is designed which achieves a gain of 93 dB and phase margin of 62°. Designed analog front end achieves an input referred noise of 0.12 μVrms and SNR of 74 dB. It consumes power of 430 μW from 1.8 V supply and occupies an area of 1.2 mm × 0.22 mm. Proposed circuit is designed and fabricated in 0.18 μm CMOS process. Designed circuit is interfaced with a sensor model of piezoelectric microphone, which mimics Ormia ochracea's auditory system, and its performance is successfully verified against simulation results.

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Wang, Yanjie, Bagher Afshar, Lu Ye, Vincent C. Gaudet, and Ali M. Niknejad. "Design of a Low Power, Inductorless Wideband Variable-Gain Amplifier for High-Speed Receiver Systems." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 4 (April 2012): 696–707. http://dx.doi.org/10.1109/tcsi.2011.2169852.

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48

Hau, G., T. B. Nishimura, and N. Iwata. "High efficiency, wide dynamic range variable gain and power amplifier MMICs for wideband CDMA handsets." IEEE Microwave and Wireless Components Letters 11, no. 1 (January 2001): 13–15. http://dx.doi.org/10.1109/7260.905953.

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49

Öncü, Ahmet. "Design and prototype of a 60 GHz variable gain RF amplifier with 90 nm CMOS for multi-gigabit-rate close proximity point-to-point communications." Journal of Electrical Engineering 75, no. 3 (June 1, 2024): 173–80. http://dx.doi.org/10.2478/jee-2024-0021.

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Abstract This paper presents the implementation of a low-power and variable-gain 60 GHz millimeter-wave CMOS Amplifier designed for short-range multi-gigabit close proximity point-to-point communications. The design uses coplanar wave transmission lines to achieve 50 Ω input and output matching. Realized in a 90 nm CMOS process, the variable-gain VGA exhibits power consumption ranging from 4.7 mW to 39.1 mW, with gains spanning from 5.5 dB to 12.4 dB at 60 GHz and a 3 dB bandwidth exceeding 14.4 GHz. Input and output return losses remain below –10 dB across the gain spectrum. Successful demonstration of gain controllability further validates the circuit’s performance. The compact VGA die, inclusive of pads, has dimensions of 740 μm by 920 μm, thereby occupying a core area of 0.2 mm2. This design demonstrates the potential of low-power, high-performance VGAs in enhancing millimeter-wave communication systems.

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Altet, Josep, Xavier Aragones, Enrique Barajas, Xavier Gisbert, Sergio Martínez, and Diego Mateo. "Aging Compensation in a Class-A High-Frequency Amplifier with DC Temperature Measurements." Sensors 23, no. 16 (August 10, 2023): 7069. http://dx.doi.org/10.3390/s23167069.

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One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation due to transistor aging. To extend circuit operating life, the bias of the main devices within the circuit must be adjusted while the aging degradation process affects them by using a monitor circuit that tracks the evolution of the circuit performance. In this paper, we propose the use of DC temperature measurements in the proximity of the circuit to perform the monitoring of circuit performance degradation and as an observable variable to adjust the bias of the main devices to restore the degraded performance to the original values. To this end, we present experimental results obtained from nine samples of a standard CMOS integrated circuit containing a high-frequency class-A power amplifier and a differential temperature sensor. After accelerated aging, the gain of the amplifier is degraded up to 50%. We propose two different procedures to perform DC temperature measurements that allow tracking of the amplifier gain degradation due to aging and, by uniquely observing temperature readings, automatically set a new bias for the amplifier devices that restores the original amplifier gain. Whereas one of the procedures is able to restore the gain up to a certain limit, the second allows full gain restoration.