Dissertations / Theses on the topic 'Variable gain power amplifier'
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1
PATEL, PRERNA D. "DESIGN OF A PIXEL SCALE OPTICAL POWER METER SUITABLE FOR INCORPORATION IN A MULTI-TECHNOLOGY FPGA." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1066421274.
2
Chen, Lin. "A low power, high dynamic-range, broadband variable gain amplifier for an ultra wideband receiver." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5843.
Abstract:
A fully differential Complementary Metal-Oxide Semiconductor (CMOS) Variable
Gain Amplifier (VGA) consisting of complementary differential pairs with source
degeneration, a current gain stage with programmable current mirror, and resistor loads is
designed for high frequency and low power communication applications, such as an Ultra
Wideband (UWB) receiver system. The gain can be programmed from 0dB to 42dB in 2dB
increments with -3dB bandwidth greater than 425MHz for the entire range of gain. The 3rd-order
intercept point (IIP3) is above -13.6dBm for 1Vpp differential input and output
voltages. These low distortion broadband features benefit from the large linear range of the
differential pair with source degeneration and the low impedance internal nodes in the
current gain stages. In addition, common-mode feedback is not required because of these
low impedance nodes. Due to the power efficient complementary differential pairs in the
input stage, power consumption is minimized (9.5mW) for all gain steps. The gain control
scheme includes fine tuning (2dB/step) by changing the bias voltage of the proposed
programmable current mirror, and coarse tuning (14dB/step) by switching on/off the source degeneration resistors in the differential pairs. A capacitive frequency compensation
scheme is used to further extend the VGA bandwidth.
3
Oder, Stephen, Paula Arinello, Peter Caron, Scott Crawford, Stephen McGoldrick, and Douglas Bajgot. "Development of a Variable Output Power, High Efficiency Programmable Telemetry Transmitter Using GaN Amplifier Technology." International Foundation for Telemetering, 2012. http://hdl.handle.net/10150/581842.
Abstract:
Cobham Electronic Systems, Inc. has developed a field-programmable telemetry transmitter module for higher-power (0.1W to 25W) airborne telemetry applications. A key feature of the transmitter is high DC to RF conversion efficiency over the entire variable output power range of 25dB through the use of GaN amplifiers. This high efficiency is realized by using a variable voltage DC-DC converter and dynamic bias control of the GaN amplifier elements. This feature is useful in that output power can be tailored to mission requirements and timelines, thereby extending battery life and increasing operation time. The transmitter receives configuration commands and can be programmed through an external data port. The transmitter can be configured for RF power and frequency over the telemetry S-Band frequency range, and has multiple data rates. The unit consists of RF, digital and power supply circuits. The RF transmitter is a PCM-FM type with a phase-locked loop, driver amplifiers, a power amplifier and a digital processor for RF control. The unit contains a digital processor, FPGA's, and flash memory. The power supplies contains all the regulator circuits to supply power to the rest of the unit, variable output drain voltage to the GaN devices, EMI filtering, under/overvoltage protection, a temperature sensor and a digital processor for power control. The electronics are housed in a compact aluminum housing.
4
Huang, Yan-Yu. "CMOS-based amplitude and phase control circuits designed for multi-standard wireless communication systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/44908.
Abstract:
Designing CMOS linear transmitter front-end, specially the power amplifiers (PAs), in multi-band wireless transceivers is a major challenge for the single-chip integration of a CMOS radio. In some of the linear PA systems, for example, polar- or predistortion-PA system, amplitude and phase control circuits are used to suppress the distortion produces by the PA core. The requirements of these controlling circuits are much different from their conventional role in a receiver or a phase array system. In this dissertation, the special design issues will be addressed, and the circuit topologies of the amplitude and phase controllers will be proposed.
In attempt to control the high-power input signal of a PA system, a highly linear variable attenuator with adaptive body biasing is first introduced. The voltage swing on the signal path is intentionally coupled to the body terminal of the triple-well NMOS devices to reduce their impedance variation. The fabricated variable attenuator shows a significant improvement on linearity as compared to previous CMOS works. The results of this research are then used to build a variable gain amplifier for linear PA systems that requires gain of its amplitude tuning circuits. Different from the conventional attenuator-based VGAs, the high linearity of the suggested attenuator allows it to be put after the gain stage in the presented VGA topology. This arrangement along with the current boosting technique gives the VGA a better noise performance while having a linear-in-dB tuning curve and better worst-case linearity.
The following part of the dissertation is about a compact, linear-in-degree tuned variable phase shifter as the phase controller in the PA system. This design uses a modified RC poly-phase filter to produce a set of an orthogonal phase vectors with smaller loss. A specially designed control circuit combines these vectors and generates an output signal with different phases, while having very small gain mismatches at different phase setting. The proposed amplitude and phase control circuits are then verified with a system level analysis. The results show that the proposed designs successfully reduce the non-linear effect of a wireless transmitter.
5
Fechine, Sette Elmo Luiz. "Circuits intégrés millimétriques en bande Ka pour une antenne à pointage électronique pour les télécommunications avec des satellites géostationnaires ou des constellations de satellites." Electronic Thesis or Diss., Limoges, 2024. http://www.theses.fr/2024LIMO0002.
Abstract:
Ce travail présente la conception de circuits actifs intégrés en vue d'une intégration dans une antenne à dépointage électronique pour les télécommunications par satellite en bande Ka. Tout d'abord, le manuscrit présente le contexte dans lequel se déroule l'étude, abordant les principaux concepts et caractéristiques de ce type d'antenne. Par la suite, deux blocs clés de la chaîne d’émission sont étudiés en détail et conçus : un amplificateur de puissance à gain variable et trois déphaseurs pilotables. Les circuits sont réalisés en utilisant deux technologies SiGe BiCMOS: BiCMOS9MW et SG13G2. Enfin, les résultats de simulation post-layout sont exposés et comparés aux spécifications du projet ainsi qu'à l'état de l'artThis work presents the design of active integrated circuits intended for integration into an electronically steered antenna for Ka-band satellite communications. Firstly, the manuscript introduces the context of the study, discussing the main concepts and characteristics of this type of antenna. Subsequently, two key blocks of the transmission chain are studied in detail and designed: a variable gain power amplifier and three controllable phase shifters. The circuits are implemented using two SiGe BiCMOS technologies: BiCMOS9MW and SG13G2. Finally, the post-layout simulation results are presented and compared to the project specifications as well as the state of the art
6
Rahmatian, Behnoosh. "A 75-dB digitally programmable CMOS variable gain amplifier." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/32248.
Abstract:
A 75-dB DIGITALLY PROGRAMMABLE CMOS VARIABLE GAIN AMPLIFIER
Variable-gain amplifiers (VGAs) are essential building blocks of many communication systems.
In this thesis, a monolithic low-power digitally programmable VGA with 75dB of gain range is
presented. The VGA is targeted for power line communication systems in particular for
automotive application; however, it is a generic block that can be use in other applications. The
core of the design is based on the low-distortion source-degenerated differential amplifier
structure. A gm-boosting circuit is also used to provide higher gain and improve gain accuracy.
In this work, to control the gain a new technique is used which is based on digitally controlling:
1) the source-degeneration resistance, and 2) an additional resistance between the differential
output nodes of each gain stage. The changes in the source-degeneration resistance handle the
coarse tuning, and the changes in the latter resistance are used for fine gain tuning.
The overall VGA consists of three such gain stages. As a proof of concept, a single gain stage
with a gain range of 24dB and programmable in 2dB gain steps has been fabricated in a 0.18μm
CMOS technology. The chip is tested and measurement results are obtained. Based on these
measurement results, the design of the gain stage is optimized and a three-stage 75dB VGA is
designed. Each stage has a digitally tunable gain range of 25dB, and fine gain tuning of 2.5dB
per step. The bandwidth of the VGA is higher than 140MHz, and the gain error is less than
0.3dB. The overall VGA draws 6.5mA from a 1.8V supply. The noise figure of the system at
maximum gain is 12.5dB, and the IIP3 is 14.4dBm at minimum gain. These performance
parameters are either better or compare favorably with the reported state-of-the-art VGAs.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
7
Jha, Nand Kishore. "Design of a complementary silicon-germanium variable gain amplifier." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24614.
8
Krishnanji, Sivasankari. "Design of a variable gain amplifier for an ultrawideband receiver." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2576.
Abstract:
A fully differential CMOS variable gain amplifier (VGA) has been designed for
an ultra-wideband receiver. The VGA comprises of two variable gain stages followed by
a post amplifier stage. The interface between the digital control block and the analog
VGA is formed by a digital-to-analog converter and an exponential voltage generator.
The gain of the VGA varies dB-linearly from 0 to 52 dB with respect to the control
voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz
throughout the gain range to cater to the requirements of the ultra-wideband system. The
noise-to-power ratio of the VGA is -23.9 dB for 1Vp-p differential input signal in the low
gain setting, and the equivalent input referred noise is 1.01 V2 for the high gain setting.
All three stages use common mode feedback to fix and stabilize the output DC levels at
a particular voltage depending on the input common-mode requirement of the following
stage. DC offset cancellation has also been incorporated to minimize the input referred
DC offset caused by systematic and random mismatches in the circuit. Compensation
schemes to minimize the effects of temperature, supply and process variations have been
included in the design. The circuit has been designed in 0.18??m CMOS technology, and
the post layout simulations are in good agreement with the schematic simulations.
9
Lo, Keng Wai. "Wideband active-balun variable-gain low-noise amplifier for mobile-TV applications." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2148237.
10
Li, Lisha. "High Gain Low Power Operational Amplifier Design and Compensation Techniques." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1701.pdf.
11
Ehteshamuddin, Mohammed. "Design of a High Temperature GaN-Based Variable Gain Amplifier for Downhole Communications." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/74958.
Abstract:
The decline of easily accessible reserves pushes the oil and gas industry to explore deeper wells, where the ambient temperature often exceeds 210 °C. The need for high temperature operation, combined with the need for real-time data logging has created a growing demand for robust, high temperature RF electronics. This thesis presents the design of an intermediate frequency (IF) variable gain amplifier (VGA) for downhole communications, which can operate up to an ambient temperature of 230 °C. The proposed VGA is designed using 0.25 μm GaN on SiC high electron mobility transistor (HEMT) technology. Measured results at 230 °C show that the VGA has a peak gain of 27dB at center frequency of 97.5 MHz, and a gain control range of 29.4 dB. At maximum gain, the input P1dB is -11.57 dBm at 230 °C (-3.63 dBm at 25 °C). Input return loss is below 19 dB, and output return loss is below 12 dB across the entire gain control range from 25 °C to 230 °C. The variation with temperature (25 °C to 230 °C) is 1 dB for maximum gain, and 4.7 dB for gain control range. The total power dissipation is 176 mW for maximum gain at 230 °C.Master of Science
12
Ayad, Mohammed. "Etude et Conception d’amplificateurs DOHERTY GaN en technologie Quasi - MMIC en bande C." Thesis, Limoges, 2017. http://www.theses.fr/2017LIMO0027.
Abstract:
Ce travail répond à un besoin industriel accru en termes d’amplification des signaux sur porteuses à enveloppes variables utilisés par les systèmes de télécommunications actuels. Ces signaux disposent d’un fort PAPR et d’une distribution statistique d’enveloppe centrée en-deçà de la valeur crête d’enveloppe. La raison pour laquelle les industriels télécoms requièrent alors des amplificateurs de très fortes puissances de sortie, robustes, fiables et ayant une dépense énergétique optimale le long de la dynamique d’enveloppe associée à un niveau de linéarité acceptable. Ce document expose les résultats d’étude et de réalisation de deux Amplificateurs de Puissance Doherty (APD) à haut rendement encapsulés en boîtiers plastiques QFN. Le premier est un amplificateur Doherty symétrique classique (APD-SE) et le second est un amplificateur à deux entrées RF (APD-DE). Ces démonstrateurs fonctionnant en bande C sont fondés sur l’utilisation de la technologie Quasi-MMIC associant des barrettes de puissance à base des transistors HEMTs AlGaN/GaN sur SiC à des circuits d’adaptation en technologie ULRC. L’approche Quasi-MMIC associée à la solution d’encapsulation plastique QFN permettant une meilleure gestion des comportements thermiques offre des performances électriques similaires à celles de la technologie MMIC avec des coûts et des cycles de fabrication très attractifs. Durant ces travaux, une nouvelle méthode d’évaluation des transistors dédiés à la conception d’amplificateurs Doherty a été développée et mise en oeuvre. L’utilisation intensive des simulations électromagnétiques 2.5D et 3D a permis de bien prendre en compte les effets de couplages entre les différents circuits dans l’environnement du boîtier QFN. Les résultats des tests des amplificateurs réalisés fonctionnant sur une bande de 1GHz ont permis de valider la méthode de conception et ont montré que les concepts avancés associés à l’approche Quasi-MMIC ainsi qu’à des technologies d’encapsulation plastique, peuvent générer des fonctions micro-ondes innovantes. Les caractérisations de l’APD-DE ont relevé l’intérêt inhérent à la préformation des signaux d’excitation et des points de polarisation de chaque étage de l’amplificateurThis work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier
13
Azmat, Rehan. "Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449.
Abstract:
The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.
14
Zhang, Xiaolang. "A programmable-gain amplifier and an active inductor for in-vehicle power line communications." Thesis, University of British Columbia, 2011. http://hdl.handle.net/2429/37014.
Abstract:
In-vehicle power-line communication (VPLC) is a communication technique that uses
the power lines of the vehicle for data transmission. Based on the measurements of the power
line communication channel, the channel response is characterized as frequency selective,
time and location dependent with high signal attenuation. Also, the access impedance
changes a lot in different frequency ranges. These properties impose design challenges at
both system level and circuit levels of a VPLC system. This thesis presents the design of two
critical building blocks of a VPLC system, namely, a variable gain amplifier (VGA) and an
active inductor.
VGAs are used to amplify the signal to a predefined level without introducing too much
distortion. The presented VGA design targets a 0.13μm CMOS technology. The VGA design
is discussed in detail. Gm-boosting technique is used to both increases the linearity and
provide a programmable 0 dB to 60 dB gain over a broadband. Furthermore, the gain is
stable over a wide range of temperatures. The circuit is fabricated and tested, and the
measured results are in good agreement with the simulation results.
Inductors are commonly used in impedance matching networks. In this work, an active
inductor circuit is designed which provides a wide tuning range for VPLC LC matching
networks. Active inductor is a good candidate to replace the passive inductor in the LC
matching network since it has a smaller area, wider tuning range, and a higher quality-factor.
The designed active inductor is a fully differential grounded Gyrator-C active inductor.
Simulation results confirm that the inductor has wide tuning range with linear tuning ability;
however, its bandwidth is limited.
The circuit design for this VPLC system is challenging, the preliminary results of the
proposed circuits show some promise; however, further work is still needed to improve the
performance.
15
Singh, Rishi Pratap. "A High-Gain, Low-Power CMOS Operational Amplifier Using Composite Cascode Stage in the Subthreshold Region." BYU ScholarsArchive, 2011. https://scholarsarchive.byu.edu/etd/2510.
Abstract:
This thesis demonstrates that the composite cascode differential stage, operating in the subthreshold region, can form the basis of a high gain (113 dB) and low-power op amp (28.1 µW). The circuit can be fabricated without adding a compensation capacitance. The advantages of this architecture include high voltage gain, low bandwidth, low harmonic distortion, low quiescent current and power, and small chip area. These advantages suggest that this design might be well-suited for biomedical applications where low power, low noise bio-signal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range is required.
16
Hasan, Md Naimul. "A Compact Low Power Bio-Signal Amplifier with Extended Linear Operation Range." University of Akron / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=akron1358074945.
17
Paro, Filho Pedro Emiliano. "A variable-gain transimpedance amplifier for MEMS-based oscillators = Um amplificador de transimpedância de ganho variável para aplicação em osciladores baseados em MEMS." [s.n.], 2012. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259292.
Abstract:
Orientador: José Alexandre DinizDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-20T16:11:38Z (GMT). No. of bitstreams: 1 ParoFilho_PedroEmiliano_M.pdf: 39204453 bytes, checksum: 8ea6c789b126029d1ff5b579bdd25102 (MD5) Previous issue date: 2012
Resumo: Um amplificador de transimpedância (TIA) de ganho variável é apresentado. Implementado em tecnologia 0,18 'mi'm, o projeto relatado possui a finalidade de prover um amplificador de sustentação para osciladores baseados em ressonadores do tipo MEMS (Micro-Electro-Mechanical System). Entre outros, as peculiaridades de projeto envolvem um desafiante compromisso entre Ganho, Largura de Banda, Ruído e Consumo de potência. Sendo assim, o amplificador foi implementado através do cascateamento de quatro estágios de ganho similares, lançando-se mão de realimentação do tipo shunt-shunt para diminuir as impedâncias de entrada e saída. Através do emprego de um estágio de ganho variável, uma alta faixa dinâmica de ganho é alcançada (53 dB), com um ganho máximo de transimpedância de 118 dB'ômega'...Observação: O resumo, na íntegra, poderá ser visualizado no texto completo da tese digital
Abstract: A variable gain Transimpedance Amplifier (TIA) is presented. Realized in 0.18 'mi'm technology, this amplifier was conceived with the purpose of providing oscillation sustaining for Micro-Electro-Mechanical System (MEMS) based oscillators. Facing a quite challenging trade-off between Gain, Bandwidth, Noise and Power consumption, the TIA was implemented through the cascade of four similar gain stages, with the application of shunt-shunt feedback to lower both input and output resistances. With the employment of a variable-gain stage, this TIA presents a large gain tunability of 53 dB, with a also large maximum transimpedance gain of 118 dB'omega'...Note: The complete abstract is available with the full electronic document
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
18
Khan, Abbas. "Optimization through Co-Simulation of Antenna, Bandpass Filter and Low-Noise Amplifier at 6-9 GHz." Thesis, Linköpings universitet, Fysik och elektroteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110575.
Abstract:
Ultra-wide band (UWB) 6-9 GHz antenna, band pass filter and low-noise amplifier (LNA) optimization using co-simulation of the RF front-end. At higher frequencies, carefully conducted design methodologies are required for RF front-end parameter optimization, such as power gain and low noise figure with low power consumption.
19
Altuntas, Mehmet. "Mmic Vector Modulator Design." Master's thesis, METU, 2004. http://etd.lib.metu.edu.tr/upload/12605684/index.pdf.
Abstract:
In this thesis the design of a MMIC vector modulator operating in 9GHz-10GHz band is investigated and performed. Sub-sections of the vector modulator are 4-port (4.8dB) 1200 phase shift relative to the dedicated port power splitter, digitally controlled variable gain amplifier and the in phase power combiner.
Alternative methods are searched in order to implement the structure properly in the given frequency band. The final design is appropriate for MMIC structure.
4-port (4.8dB) 1200 phase shift relative to the dedicated port power splitter is studied. The performance is simulated and optimized first on Microwave Office, then on Advanced Design System (ADS) tools.
Various methods to design a digitally controlled variable gain amplifier are studied. The final topology is simulated and optimized on ADS tool.
An in phase power combiner is designed. The performance of the combiner is simulated and optimized on ADS tool.
Lumped element models are replaced with CASWELL H-40 models to achieve a MMIC structure and a layout is drawn. The finalized vector modulator is simulated and optimized on ADS tool.
Key words: MMIC, Vector Modulator, Digitally Controlled Variable Gain Amplifier, Layout
20
Padovan, Fabio. "Analysis and design of high performance building blocks for phased array system in BiCMOS technology." Doctoral thesis, Università degli studi di Padova, 2016. http://hdl.handle.net/11577/3424338.
Abstract:
Phased array systems are spreading a lot in these years due to their higher performances respect to a single antenna. These systems have been progressively more and more employedin many fields such as satellite communications, high data rate links (emerging 5G technology), military and automotive radars. Initially they where only used for military applicationsdue to their higher costs and complexity. Thanks to the technology development and the researchers efforts, these days it is possible to integrate on the same chip an entire phased array system, leading to a drastic cost reduction. The explosive growth of the applications that use the phased array approach is the motivation behind this thesis, which deals with the analysis and design of high performance building blocks for phased array systems. The first part of this work gives a brief introduction on the phased array systems illustrating the working principle, the main tasks and issues of the design related to the need for high resolution and directivity of the antennas array. The second part of the thesis is dedicated to the analysis and design of building blocks for phased array systems. More in detail, the design of VGA (variable gain amplifier) and VCO (voltage controlled oscillator) will be described. VGAs are very important in the whole system because they are responsible for the array directivity and precision in the beam forming. The impact of the VGA performance impact on the phased array functionality is hence treated and analyzed. The phase behavior when the gain setting is changed is analyzed and discussed in depth. The aim of the design is to keep the phase of the signal constant for all the gain range variation in the frequency band of the amplifier. Several phase error compensation techniques have been studied and implemented. Some X -Band SiGe VGA have been realized and measured. The performance in terms of phase error as the gain is varied out-performs the state-of-the-art. In addition to X -Band applications, some work on the upcoming 5G Communication Network has been done. A Wide Band (15 − 40 GHz) Variable Gain Amplifier has been prototyped in SiGe BiCMOS technology and a 28 GHz VGA has been implemented in a 40 nm CMOS Technology. The VCO is the other fundamental building block that we take into consideration in this thesis. In this case, we focus our attention on the phase noise, a crucial parameter that is directly related to the performance of the phased array system. An in-depth analysis on the minimization of the phase noise has been done and some K-band (i.e. 18-27 GHz) VCOs have been realized in a SiGe bipolar technology. The VCOs feature a phase noise as low as -137 dBc/Hz at 10 MHz offset from the carrier. This result out-performs the state of the art if compared to other Silicon K-band Silicon-based VCOs. Only VCOs implemented using compound semiconductor technologies show better performance in terms of phase noise. However the technology cost is in this case, dramatically higher.
The work shows the feasibility of realizing high performance building blocks for phase array systems in Silicon technology. The possibility to integrate an entire phased array system on the same chip leads to a drastic cost reduction, overcoming the barrier that has stopped the development of this approach for several applications for many years. This a is crucial point for the development of next generation high data rate communication links and high precision automotive and military radars.I sistemi Phased Array si stanno diffondendo molto in questi anni grazie alle loro elevate prestazioni rispetto alla singola antenna. Questi sistemi sono stati usati sempre più in molti campi, per esempio nelle comunicazioni satellitari, nei link ad alta velocità di trasmissione (emergente tecnologia 5G), nei radar militari e automotive. Inizialmente erano usati solo nelle applicazioni militari a causa dell’elevato costo e complessità del sistema. Grazie allo sviluppo di nuove tecnologie e allo sforzo dei ricercatori, al giorno d’oggi è possibile integrare nello stesso chip un intero sistema Phased Array, portando quindi ad una drastica riduzione dei costi. La motivazione di questa tesi è appunto la crescita esplosiva delle applicazioni che adottano l’approccio dei Phased Array, in particolare la tesi si occupa dell’analisi e progettazione di blocchi circuitali ad alte prestazioni per i sistemi Phased Array. La prima parte del lavoro consiste in una breve introduzione dei sistemi con array di antenne illustrando il principio di funzionamento gli oobiettivi e le problematiche della progettazione relazionate al bisogno di avere alta risoluzione e direttività dell’array di antenne. La seconda parte della tesi è dedicata all’analisi e progettazione di blocchi circuitali per i sistemi Phased Array. Più in dettaglio, verrà descritta la progettazione di VGA (amplificatori a guadagno variabile) e VCO (Oscillatori controllati in tensione). I VGA sono molto importanti nel sistema perche sono responsabili della direttività dell’array e nella precisione nella formazione del fascio. Nella tesi viene analizzato l’impatto delle prestazioni del VGA rispetto alla funzionalità del sistema. Viene analizzato più in particolare il comportamente della phase del segnale rispetto alla variazione del guadagno. L’obiettivo del progetto è quello di avere la fase del segnale costante per tutto il range di variazione di guadagno nella banda di frequenze dove opera l’amplificatore. Sono state studiate e implementate diverse tecniche di compensazione dell’errore di fase. Sono stati realizzati e misurati diversi VGA in banda X in Silicio Germanio. Le prestazioni in termini di errore di fase superano lo stato dell’arte. Oltre alle applicazioni in banda X è stato fatto del lavoro per l’imminente tecnologia di comunicazione 5G. E’ stato prototipato un amplificatore a guadagno variabile a ix larga banda (15 − 40 GHz) in tecnologia SiGe BiCMOS ed un VGA a 28 GHz in tecnologia CMOS 40 nm. Il VCO è un altro fondamentale blocco circuitale che abbiamo preso in considerazione in questa tesi. In questo caso ci siamo focalizzati sul rumore di fase, un parametro cruciale che è direttamente collegato alle prestazioni del sistema Phased Array. E’ stata fatta un’analisi dettagliata sulla minimizzazione del rumore di fase e sono stati realizzati dei VCO in SiGe operanti in banda K (18-27 GHz). I VCO mostrano un romore di fase che arriva a −137 dBc/Hz a 10 MHz di offset dalla portante. Questo risultato è superiore allo stato dell’arte se confrontiamo con gli altri VCO operanti in banda K e realizzati in Silicio. Solo i VCO relizzati con semiconduttori compositi hanno prestazioni migliori in termini di rumore di fase. Ad ogni modo, il costo di queste tecnologie è drammaticamente più alto. In conclusione, il lavoro dimostra la fattibilità di realizzare blocchi circuitali ad alte prestazioni per i sistemi Phased Array in Silicio. La possibilità di integrare l’intero sistema Phased Array sullo stesso chip porta ad una drastica riduzione dei costi, superando la barriera che ha fermato lo sviluppo di questo approccio in molte applicazioni negli anni precedenti. Questo è un punto cruciale per lo sviluppo della prossima generazione di comunicazioni ad alta velocità di dati e sistemi radar ad alta precisione sia militari che automotive.
21
Ryšavý, Jindřich. "Předzesilovač pro MEMS mikrofon." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242074.
Abstract:
Thesis discusses the possibility of using MEMS microphones in measuring systems. Describes the characteristics of MEMS components and shows possible realization of analog to digital signal convertor when a microphone with analog output is used. Design of the amplifier is made with respect to low noise and low power consumption. Also is shown the possibility of using antialliasing filter as microphone frequency response correction at the same time.
22
Deza, Julien. "Etude, Conception et Caractérisation de circuits pour la Conversion Analogique Numérique à très hautes performances en technologie TBH InP 0.7µm." Thesis, Cergy-Pontoise, 2013. http://www.theses.fr/2013CERG0680/document.
Abstract:
Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquenceThis thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation
23
Dasgupta, Abhijeet. "High efficiency S-Band vector power modulator design using GaN technology." Thesis, Limoges, 2018. http://www.theses.fr/2018LIMO0021/document.
Abstract:
L’évolution des systèmes de télécommunications, liée à une demande sans cesse croissante en termes de débit et de volume de données, se concrétise par le développement de systèmes proposant des bandes passantes très larges, des modulations à très hautes efficacités spectrales, de la flexibilité en puissance et en fréquence d’émission. Par ailleurs, la mise en œuvre de ces dispositifs doit se faire avec un souci permanent d’économie d’énergie d’où la problématique récurrente de l’amplification de puissance RF qui consiste à allier au mieux rendement, linéarité et bande passante. L’architecture conventionnelle d’une chaine d’émission RF consiste dans une première étape à réaliser l’opération de modulation-conversion de fréquence (Modulateur IQ) puis dans une deuxième étape l’opération de conversion d’énergie DC-RF (Amplificateur de Puissance), ces deux étapes étant traditionnellement traitées de manière indépendante. L’objectif de ces travaux de thèse est de proposer une approche alternative qui consiste à combiner ces deux opérations dans une seule et même fonction : le modulateur vectoriel de puissance à haute efficacité énergétique. Le cœur du dispositif, conçu en technologie GaN, repose sur un circuit à deux étages de transistors HEMT permettant d’obtenir un gain en puissance variable en régime de saturation. Il est associé à un modulateur de polarisation multi-niveaux spécifique également en technologie GaN. Le dispositif réalisé a permis de générer directement, à une fréquence de 2.5 GHz, une modulation vectorielle 16QAM (100Msymb/s) de puissance moyenne 13 W, de puissance crête 25W avec un rendement global de 40% et une linéarité mesurée par un EVM à 5%The evolution of telecommunications systems, linked to a constantly increasing demand in terms of data rate and volume, leads to the development of systems offering very wide bandwidths, modulations with very high spectral efficiencies, increased power and frequency flexibilities in transmitters. Moreover, the implementation of such systems must be done with a permanent concern for energy saving, hence the recurring goal of the RF power amplification which is to combine the best efficiency, linearity and bandwidth. Conventional architectures of RF emitter front-ends consist in a first step in performing the frequency modulation-conversion operation (IQ Modulator) and then in a second step the DC-RF energy conversion operation (Power Amplifier), these two steps being usually managed independently. The aim of this thesis is to propose an alternative approach that consists in combining these two operations in only one function: a high efficiency vector power modulator. The core of the proposed system is based on a two-stage GaN HEMT circuit to obtain a variable power gain operating at saturation. It is associated with a specific multi-level bias modulator also design using GaN technology. The fabricated device generates, at a frequency of 2.5 GHz, a 16QAM modulation (100Msymb/s) with 13W average power, 25W peak power, with an overall efficiency of 40% and 5% EVM
24
Hu, Yun-Chung, and 胡運忠. "Low Power Variable Gain Amplifier for UWB systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/13040808438308906179.
Abstract:
碩士中原大學
電子工程研究所
95
The booming development of the wireless communication technology in recent years make the relevant products, such as GSM, CDMA, Bluetooth, 802.11 (Wi-Fi), ZigBee and Ultra wide band (UWB) widely used in our daily life and became important research topics. This thesis proposes a Variable Gain Amplifier (VGA) that is suitable for UWB system. It consists of a main amplifier, gain control circuit, and a common mode feedback loop. The main amplifier is realized by a folded cascode amplifier with feedback and the gain control function is utilized by a source-coupled pair to realize controllable gain. A modified pseudo-exponential equation is proposed to improve the linearity of the proposed VGA. The circuit is designed and simulated in TSMC 0.18um CMOS process. The gain range of 18dB and the 3dB frequency of 610MHz at the maximum gain that meets the specification of UWB system is obtained. The power dissipation is less then 2mW at 1.8V supply voltage.
25
Hsiao, Chih-Jen, and 蕭智仁. "Implementation of 1.8/2.4GHz Variable Gain Power Amplifier with Power Switch Embedded." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/89967369452414425058.
Abstract:
碩士國立高雄應用科技大學
電機工程系碩士班
93
This thesis researches on 1.8/2.4GHz variable gain power amplifier with power switch embedded. The chip is fabricated in UMC standard 0.18um 1P6M CMOS process. After measuring, the chip at frequency 1.8GHz exhibits an input return loss of 11.4dB, output return loss of 12.6dB, gain of 20.8dB, output P1dB of 5.8dBm, OIP3 of 15.4dBm, maximum output power of 4.62dBm, PAE(Power Added Efficiency) of 5.7% and variable gain range of 13.2dB to 20.8dB. On the other hand, the chip at frequency 2.4GHz exhibits an input return loss of 11.7dB, output return loss of 13.4dB, gain of 10.1dB, output P1dB of 0.1dBm, OIP3 of 9.8dBm, maximum output power of 0.43dBm, PAE of 1.8% and variable gain range of 2.1dB to 10.1dB.
26
Chu-YunYang and 楊楚昀. "Design of K-band CMOS Low-Noise, Power Amplifier and 60-GHz Millimeter-Wave Variable Gain Amplifier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/11564077277691488506.
Abstract:
碩士國立成功大學
電腦與通信工程研究所
98
This thesis presents the design of 24- and 60-GHz CMOS amplifier RFICs for millimeter-wave communication applications. The designed RFICs are fabricated with TSMC CMOS 0.18 μm and 90-nm standard processes, respectively. At first for the Ka-band amplifier design, a 15 - 22 GHz wideband CMOS low noise amplifier (LNA), 24-GHz high-efficiency power amplifier (PA), and 18-25 GHz wideband CMOS power amplifier are presented. The simulation and measurement results are compared and discussed. Secondly, a 60-GHz 90-nm CMOS variable gain amplifier (VGA) is presented. For the desired low phase-variation in the variable gain control range, the measured phase-variation of the VGA is less than about 10 degree.
27
Chun-HanYu and 余俊翰. "Millimeter-Wave CMOS Wideband Variable-Gain Low-Noise Amplifier and 94-GHz CMOS Power Amplifier with Built-in Pre-distortion Linearizer." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/bed8pa.
Abstract:
碩士國立成功大學
電腦與通信工程研究所
102
This thesis presents the research on millimeter-wave (MMW) CMOS wideband variable-gain low-noise amplifiers (VG-LNAs) and a 94-GHz CMOS power amplifier (PA) with built-in pre-distortion linearizer, implemented by standard TSMC 0.18-μm or 90-nm GUTM CMOS process. To obtaine wideband frequency response, the resistive-feedback skill with additional passive components is used as the matching network. In the 60-GHz VG-LNA design, a gain boosting inductor is used in order to obtain a better gain performance. In 94-GHz CMOS PA design, a four stage CS cascade structure is adopted for output gain enhancement. Futhermore, the linearity performance of designed PA such as IP1dB is improved by the built-in pre-distortion linearizer. The measured performances of the designed MMW CMOS RFICs are all performed by using the on-wafer measurement. Simulation and measurement results are compared and discussed.
28
Hsieh, Chi-Song, and 謝其松. "Novel Low-Voltage Low-Power Exponential Circuits and Variable Gain Amplifiers (VGA)." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/59541005797916039795.
Abstract:
碩士國立中山大學
電機工程學系研究所
90
Two novel ultra-low-voltage (ULV) low-power (LP) variable gain amplifiers (VGA) are presented in this paper. These amplifiers based on complementary MOS transistors operating in weak inversion region are composed of pseudo-exponential current-to-current converters and analog multipliers. The gain of the amplifiers can be controlled by an exponential function circuit. The proposed circuits have been verified with the 0.25μm CMOS technology by HSPICE simulations. The simulation results confirm the feasibility of the proposed VGAs.
29
Lu, Yu-Cheng, and 盧昱程. "The Circuit Design of A Power Efficient Variable Gain Buffer Amplifier And Reconfigurable Dual Channel Analog Front-End for Biomedical Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/yhqfd4.
Abstract:
碩士國立臺灣科技大學
電機工程系
106
This thesis presents the design of power-efficient dual channel analog front-end (AFE) circuits for biomedical applications based on floating-gate programming technologies. The circuits in each channel of the analog front-end include a low noise amplifier (LNA), a variable gain amplifier (VGA), two reconfigurable biquadratic filter sections, and a buffer amplifier (BA). Floating-gate transistors are employed to implement programmable current sources, common-mode feedback, and programmable linear pseudo resistors, achieving low noise and high linearity with low power consumption. Since the bias current level is programmable, the bandwidth of the circuits can be easily tuned to fit into a variety of physiological signal sensing applications, such as the electrocardiogram (ECG), electroencephalogram (EEG), and electromyogram (EMG) from human bodies. The proposed AFE was fabricated in a 0.35μm CMOS process, and its area is 6.88mm2. To prevent that the filter impacts the sensitivity of the low frequency signal, the designed sensing channel includes the LNA and the VGA, achieving 116Hz of the high frequency cutoff point and 0.8Hz of the low frequency cutoff point under 205nA of current consumption. The midband gain is designed from 55.35dB to 81.58dB. The measured input referred noise voltage is 2.43Vrms integrated from 0.5Hz to 100kHz. The noise efficiency factor (NEF) is 3.94. The total harmonic distortion (THD) is -58.34dB with 1.136V of the output peak-to-peak voltage in the low gain set. Since the variable gain amplifier employs T-network to implement the small feedback capacitance, the feedback pseudo resistance should be several times larger than that in LNA to achieve a low frequency cutoff point. To improve this drawback, the variable gain amplifier is redesigned by employing the original structure of the buffer amplifier. Compared with conventional operational amplifier, the linearity is improved because of the floating-gate based class-AB input stage with enhanced slew rate. The bandwidth and the closed-loop gain are both reconfigurable through programming the floating-gate current source and switching different amount of feedback capacitors. The improved buffer amplifier was designed and fabricated in a 0.35μm CMOS process occupying a silicon area of 0.084mm2. The current consumptions under 100kHz, 500kHz, and 1MHz conditions are 5.9μA, 38μA, and 124.8μA, respectively. The measured IIP3 is above 28.7dBV, and the THD is below -82.6dB in the low gain set.
30
Ghosal, Kaushik. "Power Scaling Mechanism for Low Power Wireless Receivers." Thesis, 2015. http://etd.iisc.ac.in/handle/2005/3767.
Abstract:
LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power.
We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER).
We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI.
The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.
31
Ghosal, Kaushik. "Power Scaling Mechanism for Low Power Wireless Receivers." Thesis, 2015. http://etd.iisc.ernet.in/2005/3767.
Abstract:
LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power.
We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER).
We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI.
The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.
32
Chen, Yun-ju, and 陳韻如. "Design of CMOS Variable Gain Amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/47315197247618226962.
Abstract:
碩士逢甲大學
電子工程所
97
A CMOS variable gain amplifier （VGA） is presented, which consists of exponential control circuit, amplifier circuit and buffer circuit. The exponential control circuit adopts an approximate exponential equation. The amplifier circuit includes a common mode feedback circuit, the common mode feedback is required in order to prevent any of the transistors from entering linear mode operation and to maintain a specific dc value for the biasing of the next stage. The VGA is implemented in 0.35um CMOS technology and total power dissipation is 58mW at 3.3V supply. The chip size is 0.93mm2.
33
Lai, Bing-Jiun, and 賴炳均. "Integrated Radio Frequency Variable Gain Amplifier." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/79487323239286597680.
Abstract:
碩士國立中正大學
電機工程所
96
The first stage of a receiver is typically a low noise amplifier, whose main features are to provide enough gain and minimize the influence to subsequent stages due to the noise generated in itself. In general, variable gain amplifier is employed for automatic gain control, which is used for automatically adjusting gain of the receiver path, so that the received RF signal can be easily processed by subsequent circuits. The requirements for the tuner front-ends are low power consumption, dB-linear, dynamic range, linearity and gain performance. The first part of this thesis is devoted itself abut the variable gain amplifier which was manufactured by the TSMC 0.18 μm CMOS process. It is applied to WiMAX system. The first one is the variable gain low noise amplifier in which the differential topology being used due to its inherent feature of low interference. The second is the variable gain amplifier, which is addressed on the high tunable gain range. It can be use in the transmitter just before the power amplifier or used in receiver after the low noise amplifier. The second part of this thesis is the wideband variable gain low noise amplifier which was fabricated by a standard TSMC 0.35 μm SiGe BiCMOS technology. In order to improve the bandwidth, two types of feedback are employed, and then using the Darlington pair to double the cutoff frequency.
34
Chen, Hsin-Hao, and 陳信豪. "Variable Gain Amplifier for Ultrasound Imaging Receiver." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/26783570570803995937.
35
Liu, Hung-Hsi, and 劉洪禧. "FPGA implements variable gains control of the variable gain amplifier." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/01974566430523855947.
Abstract:
碩士中原大學
電子工程研究所
97
Field Programmable Gate Array (FPGA) can be used to implement complex logic function and provide rapid field re-programmable ability in a single chip design application. This thesis describes the use of hardware design language Verilog and the implementation of a variable gain controller in a Variable Gain Amplifier. A top-down methodology is applied in this design to make the design clearer and easier for maintenance. A look up table (LUT) mechanism is applied to realize faster computing and simplify the design complexity. The design is simulated by Modelsim and implemented by Altera FPGA EP1C6.
36
Tsou, Shan-Chih, and 鄒善智. "CMOS Variable Gain Amplifier for Multi-Standard Receiver." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/31899508987093420198.
Abstract:
碩士國立清華大學
電機工程學系
92
With the rapid growth of higher data rate, integrating the analog circuit block with wide bandwidth in the baseband will be an indispensable trend in the future. On the other hand, a single circuit block which can be used for multi-standard receiver is an economic implementation way to enhance the usability of the cell phone. A CMOS variable gain amplifier (VGA) for multi-standard receiver described in this thesis aims to meet these two demands. In general, VGA is controlled by an automatic gain control (AGC) loop. As the data rate increases, the data slot which is used for the AGC loop to settle is getting smaller. A fast gain settling of the AGC loop becomes more and more important to make sure the data transfer is correct. The performance of the AGC loop can be characterized not only by a fast gain settling, but also the precise gain settling, the stable gain settling, and a low-distortion output signal. Alinear model of the AGC loop is set up and simulated with the performance of VGA modeled as the proposed one to see the dynamics of the loop. In this thesis, a proposed VGA for the multi-standard receiver is analyzed, designed, and implemented using the standard 0.18um 1P6M CMOS technology. The output signal of the VGA can be of constant signal level and contant group delay. The bandwidth of the VGA is extended from GSM 100KHz, WCDMA 2MHz to WLAN 10MHz, and designed to be adjustable for the noise and linearity concern of the total architecture. The gain of tha VGA ranges from -10dB to 20dB, and the constant bandwidth peroperty with different gain settings helps the simplification of DSP circuitry in the baseband. The total power consumption of the VGA is 2.43mW at 1.8V supply voltage. The chip area is 0.645mm x 0.465mm.
37
Song, Guang-Fong, and 宋光峰. "The Design of A Variable Gain Instrumentation Amplifier." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/24520553586227143218.
Abstract:
碩士中原大學
電子工程學系
87
A variable gain instrumentation amplifier (IA) has been designed in this thesis. Buffered two-stage operational amplifier and poly resistors construct the core of the instrumentation amplifier. In order to obtain good amplifier performance, the circuit configuration of the IA and its output stage, the offset and noise effects have been analyzed and investigated in this thesis. We also present key layout methods such as common-centroid structure, dummy device and guard-ring option for differential input transistor pair, compensated capacitor and poly resistors. Full custom design flow has been used in the instrumentation amplifier design. The circuit has been integrated in a 0.5mm double poly double metal n-well CMOS process. In this research, several characterization methods have been developed to measure instrumentation amplifier. In order to assure the measurements, the commercial IA device has been also tested in this research. The test results show that the proposed IA has a variable gain of 0 dB to 40dB and a common-mode rejection ratio (CMRR) of more than 85dB. The minimum input offset voltage of less than 1mV has been measured. The amplifier has an acceptable die size of 810×400mm2 and its power consumption is 13mW at 5V operation.
38
Chen, Sz-Han, and 陳思涵. "A 1.5-GHz Variable-Gain Amplifier and Filter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/3kjgaf.
Abstract:
碩士國立交通大學
電子研究所
108
For the fifth generation (5G) communication system, we use variable gain amplifier (VGA) to amplifier the baseband signal at receiver and use filter to filter out noise and any other signals which are not in the signal band. After that, we use analog-to-digital converter (ADC) to convert analog signal to digital signal for digital circuits and complete the baseband front-end receiver circuit of the fifth generation communication system. This paper is about VGA and filter. ar Due to the specification of bandwidth is wider in the fifth generation communication system, we use Gm-Miller-C filter instead of switch-capacitor filter and active-RC filter to reach the specification. The Gm-Miller-C filter is more suitable for high speed system, but the main disadvantage is the worse linearity. It is the most important part for us to improve the linearity. ar The VGA structure is based on the design of Gm-Miller-C filter and we can change the value of resistors to get programmable voltage gain. We applied the VGA and Gm-Miller-C filter as a third-order baseband chain in the fifth generation communication system and get 1.5625 GHz -3dB frequency also we can change the voltage gain from 8 dB to 40 dB for each 1 dB step. Also, we use DC-offset cancellation technique with negative feedback topology. Comparing the positive and negative output voltage and feedback to the first stage after amplifier the mismatch to reduce the impact of offset. ar This design use TSMC 28 nm CMOS process and the layout area is 198.07 x 90.88 um$^{2}$. the main circuit operate at 1 V and 1.5 V for the last stage to meet the output swing of +/- 400 mV. For the input signal bandwidth is from 5 MHz to 1.5625 GHz and input swing is +/- 150 mV, we can get SFDR is more than 47 dB, SNDR is more than 36 dB and THD is more than -38 dB. The whole design consumes 48 mW.
39
陳東山. "Radio frequency heterojunctio bipolar transistor variable frequency oscillator and variable gain amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/93466629235737130612.
Abstract:
碩士國立中興大學
電機工程學系
91
Fabricated through a GaInP/GaAs HBT technology, a monolithic variable frequency oscillator (VFO) and a monolithic variable gain amplifier (VGA) were measured and reported in this thesis. A number of issues on the VFO and VGA were detailed as well. A new circuitry, called a Variable Impedance Converter (VIC), was adopted to mimic a variable capacitor, which was essentially an important element for frequency tuning in a LC-based oscillator design.A negative-impedance converter not only provides the necessary negative resistance for oscillation, but also functions as the voltage level shifters for the VIC. A classic circuit, called a translinear circuit, makes full advantage of the exponential I-V characteristic to linearize the tuning curve of the VFO. No external but two on-chip inductors were used in the VFO. Several operating principles for a VGA were explored in the VGA chapter. Based these principles we discussed, a wide gain control range VGA was achievable. The designed VGA consisted of a fixed gain preamplifier, a variable attenuator, and a tunable transconductance common-emitter (CE) amplifier, in which the input impedance is also controllable by a voltage controlled resistor. Therefore, by cleverly composing these functions of the controllable components, a low noise VGA with 50dB gain control range result.
40
OJHA, RAM MOHAN. "DESIGN OF HIGH GAIN LOW POWER AMPLIFIER." Thesis, 2012. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14145.
Abstract:
The analog electronics circuits have been developed much better from the past few decades. The design of analog amplifier has become the field of attraction due to various changes in technology. Amplifier circuits are analog circuit which can be used anywhere in houses like in electronic appliances. A variety of these devices such as Operational Amplifier, Fully Differential Amplifier, Current Feedback and Current Conveyors are spread all over in the integration of such electronic devices. In analog processing system Operational Amplifier is considered as a key element.
A CMOS single output two stage operational amplifier is presented which operates at 1.8 V power supply. It is designed to meet a set of provided specifications. The unique behavior of MOS transistor in sub-threshold region allows designer to work at both low input bias current and also at low voltage. This op-amp has very low standby power consumption with a high driving capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of 95.2 dB, -3db bandwidth of 80 Hz, phase margin of 64.60 and a unity gain bandwidth of 1.49 MHz for a load of 1 pF capacitor. This op-amp has a PSRR of 148.2 dB. It has a CMRR (dc) of 99.1 dB, and an output slew rate of 11.9 V/μs. The power consumption for the op-amp is 54.2 μW. The presented op-amp has Input Common Mode Range (ICMR) of 0.2V to 1.3V. The op-amp is designed in the 180 nm technology using the 180 nm technology library.
The described op-amp is a simple two stage single ended op-amp which employs composite cascode technique. The input stage of the op-amp is a differential amplifier with an NMOS pair. The second stage of the operational amplifier is a simple PMOS common source amplifier. The second stage is used to increase the voltage swing at the output. The schematic of the operational amplifier has been designed and simulation is done using PSPICE simulator thereafter results are compared with the previous reported design.
41
Liu, Bang-Zhi, and 劉邦志. "Implementation of 6-Bit Digital control Variable Gain Amplifier with High Linear Gain." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/40855833975865745996.
Abstract:
碩士中華大學
電機工程學系碩士班
102
The propose of this thesis is to design and implement the circuits of a Digital control Variable Gain Amplifier with High Linear Gain. We use HSPICE and MATLAB for circuit simulation and analysis. Circuit layout is used the Laker which provided by CIC. The Chip is fabricated by TSMC 0.18 um CMOS process. In this thesis, the variable gain amplifier is divided into two parts: Amplifier circuit and control circuit. The amplifier circuit is designed by exponential function which approximated by second order Taylor’s polynomial. The control circuit is designed by one set of segmentation control circuit. The amplifier circuit is designed by four sets of second order Taylor’s polynomial circuit at different input points and one set of segmentation control circuit. The simulated result is based on the input range of -10μA to 10μA, the power supply of 1.8V and the linear gain error within±0.5dB. The linear gain range is 108dB, the bandwidth is 37MHz to 268MHz, the power consumption is from 7.8mW to 10.1mW and the area of chip is 0.432*0.32(mm2).
42
Hsieh, Chia-Yu, and 謝家瑜. "Design of 60-GHz Buffer Amplifier and Low Phase Variation Variable Gain Amplifier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/76843822133276427501.
Abstract:
碩士臺灣大學
電信工程學研究所
98
According to the progress of communication techniques and process technologies, wireless communication and high data-rate transmissions become the trend of developments. Recently, 60 GHz becomes a more important developed frequency band, since it is an unlicensed band for application of WPAN, which can provide the secure and efficient short-distant transmission. On the other hand, in process technologies, because of the advantages of high integration potential, low cost and low power in CMOS, it gradually replaces other process to become a major process to realize analog circuits. In this thesis, two amplifiers, which are buffer amplifier and variable gain amplifier (VGA), are applied in 60 GHz and realized by CMOS technology The 60 GHz buffer amplifier, which can amplify signal from prior stage to input of front-end power amplifier and guarantee the maximum output power can be delivered without saturation at prior stages, is discussed in first part. This amplifier is implemented by 65-nm CMOS process, and matched by TFMS lines. With reasonable power consumption, the amplifier achieves high gain and high output power with broadband characteristics of both small-signal and large-signal due to broadband matching technique. This buffer amplifier can achieve maximum linear-gain of 23.7 dB with 3-dB bandwidth of 14 GHz with maximum saturated output power of 10.3 dBm and maximum peak PAE of 16%. Therefore, it also can be applied as a medium power amplifier. In the second part, the 60 GHz VGA, which can be applied in receiver phase array systems, is designed and fabricated. With current-steering topology to realize variable gain, this VGA is implemented by 90-nm CMOS process, and matched TFMS lines. In addition to the characteristics of high linear-gain with good flatness and large gain variation range, the technique to compensate insertion phase is implemented in this VGA. As a result, the insertion phase variation is lower than 6.6° versus gain tuning. Low phase variation VGA can be applied in phase array systems to reduce the complexity of control systems while can enhance the quality of modulated signals in vector sum modulators.
43
Hsieh, Yu Da, and 謝育達. "Design of Low Noise Amplifier and Variable Gain Amplifier for Multi-band Application." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/19093566999512238335.
Abstract:
碩士長庚大學
電子工程學系
100
This thesis investigates on the “Design of Low Noise Amplifier and Variable Gain Amplifier for Multi-band Application”. In the future, we will integrate the multi-band LNA and VGA with the front-end receiver. The completion can be used in the 1.8/1.9/2.4/3.5/5/5.8GHz RF transceiver. The ultimate goal is to integrate the transceiver circuit into a single wafer to benefit the integration of the base-band circuit and to realize the manufacture of SoC (System on a Chip). In this thesis, LNA input return losses are smaller than those of -9 to -10dB. Output return losses are smaller than those of -11dB. LNA has a gain of 12.1 to 17.2dB and noise figure is smaller than 3.1 to 5.5dB. P1dB of -12 to -17. DC bias of 1.6V. Power consumption is 29.6mW. The chip size of 1.4×1.29 mm2. VGA has a gain of 0 to 30dB. Power consumption is 19mW. The chip size of 0.43×0.55 mm2. Three major ICs viz. Dual-band LNA, balun and VGA are designed by Vanguard International Semiconductor Corporation (VIS). Dual-band 2.4/5.8 GHz LNA input return losses are smaller than those of -13dB. Output return losses are smaller than those of -14dB. LNA has a gain of 18/11dB and noise figure is smaller than 4.8 to 4.7dB. DC bias of 2V. Power consumption is 45.8mW. The chip size of 1.37 mm2. Dual-band 2.4/5.8 GHz LNA and balun input return losses are smaller than those of -9dB. Output return losses are smaller than those of -10dB. LNA and balun has a gain of 11/12dB and noise figure is smaller than 4.4 to 4.9dB. DC bias of 2.5/1.5V. Power consumption is 48.5mW. The chip size of 4.316 mm2. VGA has a gain of 0 to 67.9dB. Power consumption is 9.27mW. The chip size of 0.3 mm2. The circuits are fabricated by VANGUARD of 0.25μm and 0.18μm process, respectively.
44
Chang, Yu-Chen, and 張佑丞. "High Power Audio Amplifier with Variable Power Supply." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/u285tg.
Abstract:
博士國立臺灣科技大學
電子工程系
105
Conventional audio power amplifiers are operating with fixed power supply. It means that the power losses caused by quiescent current are also fixed and regardless to output power. When power amplifier working in low power condition, the voltage across power devices will be larger than high power condition such that the losses on power devices increase. This dissertation presents an audio power amplifier with variable power supply controlled by input audio signal. In low-power output condition, the power supply will provide low voltage to reduce the power loss on power transistors and improve circuit efficiency. The power supply voltage of power amplifier can be controlled by the audio input signal used as the reference of power converter. The amplifier system is divided into two parts: the audio power amplifier adopting an integrated amplifier driving circuit with class AB topology and the power supply implemented with a full-bridge phase-shifted converter.
45
Hung, Chia-Cheng, and 洪家正. "A Low Voltage, Variable Gain Design for Low Noise Amplifier." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/15654715837525270170.
Abstract:
碩士長庚大學
電子工程研究所
92
In the thesis, an integrated RF circuit topology that can be used to realize low voltage ( i.e. 1V ) low noise amplifier is presented. The design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated circuits. Based on a LC-folded cascode LNA topology, it is implemented with a modified LC-folded cascode LNA configuration using two common source transistors to improve linearity. The linearity is improved about 2 to 3 dB. On LC-folded cascode topology, another merit that only increases in the LNA circuit complexity is an extra gain control signal, Vtune. Gain variation is achieved by controlling the Vtune, hence adjusting the overall gain of the LNA without affecting the input noise and impedance matching. The technique is applied to the design of a proposed LNA operating at 2.4 GHz using a TSMC 0.18 μm mixed signal ( 1P6M ) CMOS technology. A low voltage, variable gain design for low noise amplifier is fully on chip between input and output. The proposed LNA chip achieves measured results of 11.14 dB for power gain, 3.981 dB for noise figure, the input and output return loss of -26.06 dB and -6.827 dB, the 1-dB compression point and IIP3 of -14 dBm and -5 dBm, respectively. The circuit has 10 dB of gain tuning, and can operate at a low supply voltage of 1 V.
46
Yang, Hui-Chen, and 楊蕙甄. "A Short-Channel Variable Gain Amplifier with DC Offset Cancellation and Gain Calibration Loop." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/63026791132656734491.
Abstract:
碩士國立清華大學
電機工程學系
98
In this thesis, a short-channel variable gain amplifier with digital feedback loops is proposed. For the purpose of area saving, the entire work is implemented with minimum gate length CMOS devices. This results in severe circuit process variations. To overcome this problem, two digital feedback loops are needed for the DC offset cancellation and gain calibration. The VGA circuit is based on a fully-differential gain stage with a degeneration resistor network. The resistance of this resistor network is digitally controlled to provide enough gain range and resolution. To properly set the VGA gain, the digital gain calibration loop is enabled before the VGA operates. The DC offset cancellation loop is always active to prevent the VGA output from DC saturation. With the aid of both loops, the proposed VGA is robust against process variations. An experimental chip is fabricated in TSMC 0.18-μm 1P6M CMOS process. The core area occupies 292 μm × 592 μm. The available gain range of the VGA is -3.9 ~ 48.3 dB. For a 6-dB gain step requirement, the gain error is less than 0.5 dB. The bandwidth at the maximum gain setting is 10.85 MHz. With 10-MHz 400-mVppd sinusoidal output waveform, the total harmonic distortion (THD) at maximum and minimum gain setting are -33.82 dB and -48.08 dB respectively. The output DC offset voltage is less than 20 mV when the input DC offset voltage is within -70 ~ +50 mV. The current consumption from a single 1.8-V power supply is 12.1 mA.
47
Lu, De-Ren, and 盧德任. "Research on Millimeter-Wave Low-phase-variation Variable-gain Amplifier and Low-noise Amplifier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/83910802420622187767.
Abstract:
碩士國立臺灣大學
電信工程學研究所
100
As the progress of communication techniques and the advance in process technology, the interest in the millimeter-wave band has rapidly grown since the wide bandwidth allows high data transferring rate for short-range wireless applications. In this thesis, a low noise amplifier (LNA) and a variable-gain amplifier (VGA) are implemented in CMOS technology for W-band and V-band, respectively. In the first part, the W-band LNA, which is an essential component in the receiver, has been designed by TSMC 65-nm 1P9M CMOS process. The circuit is implemented by 4-stage cascode configuration to achieve high gain and wideband performance. This LNA has a peak gain of 25.3 dB at 117.5 GHz, and the gain is better than 20 dB from 75.5 GHz to 120.5 GHz. It features the measured noise figure is from 6 to 8.3 dB from 87 to 100 GHz, OP1dB of -3 dBm, and Psat of 0.5 dBm. The quiescent current of the LNA is 24 mA from 2-V supply voltage. In the second part, the V-band VGA can be applied in the receiver of a phased-array system. The circuit has been implemented by TSMC 65-nm 1P9M CMOS process and adopted two current-steering stages to achieve variable-gain function. Resonant technique is proposed to cancel the intrinsic capacitor and reduce insertion phase variation while the gain of the VGA is varied. In addition, the noise figure of the VGA can be reduced by using this method simultaneously. A peak gain of 18 dB with a 1-dB bandwidth of 54-62 GHz is measured. In addition, the circuit has a minimum measured NF of 4.4 dB. The insertion phase variation is lower than 6.2° while the gain is varied from 15 dB to 0 dB. The total dc power consumption is 18 mW from 1.8-V supply voltage. A low-phase-variation VGA can not only reduce the complexity of control systems in the phased-array system but also enhance the quality of modulated signals in vector sum modulators.
48
Chang, Yu-Cheng, and 張佑誠. "Design of Wideband Power Amplifier with Gain Control." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/36601877257000234299.
Abstract:
碩士逢甲大學
電子工程所
91
The thesis is to design and implement the Wide Band Power Amplifier with Gain Control in MMIC (Monolithic Microwave Integrated Circuit) which will satisfy the standard of IEEE 802.11 b in ISM（Industrial Scientific and Medical） band. The operating DC power supply is 3 V. We use simulation tool ADS 2002 （Advance Design System 2002） from Agilent corporation to simulate and analyze the circuits. The models of InGaP/GaAs Power HBT, resistor, capacitance, and inductance are given by GCTC（Global Communication Technology Corporation）. Layout software will use Cadence Virtuoso Layout Editor. A Class A low power supply and high linear RF PA will be designed. Further more, we will design a wide band PA by using network matching theory and also add a variable gain amplifier in the front of MMIC to control the gain. Finally, we use surface mount devices （SMD） to implement the circuit and compare with MMIC. The wide band power amplifier with gain control will offer more than 20 dBm output power, 800 MHz operating bandwidth and more than 20 dB gain control.
49
Chen, Jhih-bin, and 陳志彬. "Design of Variable Gain Low Noise Amplifier for IEEE 802.11a Application." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/824urv.
Abstract:
碩士國立中山大學
電機工程學系研究所
101
The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). In order to keep RF receiver to operate at linear region under receiving strong signal, the gain of low noise amplifier must be tunable to avoid influencing the subsequent block. Traditional variable gain low noise amplifier is mainly adopted in cascade. Owing to the cascade includes amplifier, attenuator and buffer stages, the more complexity and power consumption increased. This thesis utilizes dual stage to simplify complexity of the circuit and variable gain low noise amplifier fabricated in TSMC 0.18 µm CMOS technology for IEEE 802.11a application. Without sacrificing gain, the variable gain low noise amplifier employ current-reuse structure to amplifier stage to reduce power consumption, variable-impedence structure to load stage to achieve variable gain, source follower structure to buffer to improve output matching, N-type diode load and source-degeneration structure to input stage to improve input matching. The proposed variable gain low noise amplifier with 1.1 mm × 1.1 mm chip size and its 5.2 GHz operating frequency is well suited for IEEE 802.11a (5~6 GHz) application. Measurement resutls demonstrate the highest and lowest gain of 15.29 and 8.19 dB respectivly, the gain tuning range is approximated as 7.1 dB. Moreover, the amplifier shows input return loss of -16.17 dB (highest gain mode)/-15.2 dB (lowest gain mode) and very good output return loss of -17.22 dB (highest gain mode)/-19.1 dB (lowest gain mode). Simultaneously, the amplifier shows isolation of -39.42 dB (highest gain mode)/-38.72 dB (lowest gain mode). Finally, a moderate consuming power are 16.05 mW (highest gain mode)/15.3 mW (lowest gain mode) of such varible gain low noise amplifier can be achieved from 1.6 V supply voltage.
50
YAN, LIU GUANG, and 劉光硯. "Implementation of Digital control Variable Gain Amplifier using Feedback Block Diagram." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/20033866785725962660.
Abstract:
碩士中華大學
電機工程學系碩士班
102
This thesis design a Digital control Variable Gain Amplifier be based on the CMOS current mirror and improve the linear gain by using the feedback and Pade approximation. Finally, we use HSPICE and MATLAB for circuit simulation and analysis. Circuit layout is used the Laker which provided by CIC. The chip is fabricated by TSMC 0.18μm CMOS process. In this thesis, the simulated result is based on the input range of -10μA to 10μA, the power supply of 1.8V, the linear gain range is 53dB and 63dB, the linear error within ±1dB and ±1.5dB, the bandwidth is 137MHz to 865MHz and 122MHz to 918MHz, the power consumption is from 4.4mW to 5.6mW and the area of chip is 0.432*0.432(mm2).