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Wu, Wei. "MICRO-CIRCUIT DIODE FOR ULTRA-LOW-POWER ENERGY HARVESTING." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1415.
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Harvesting energy from ultra-low-power vibration energy sources typically employs a rectifier circuit as the first power conditioning stage. The Schottky diode has a 0.15 V - 0.2 V threshold voltage and can not extract energy efficiently at low voltage. Other technologies such as MOSFET bridge or active diode are designed to minimize the voltage drop to reduce the conduction loss. However, these designs require either additional power supplies to operate comparators or have a larger threshold turn-on voltage than Schottky. Therefore, most rectifiers have an unresponsive or significant low-efficiency zone when the input power is low. This dissertation will elaborate on a backward diode based self-powered micro-circuit diode that will operate in the extremely weak or low alternating source applications, where the existing approaches offer poor outcomes. This proposed micro-circuit diode was compared to a Schottky diode in several experiment setup. The micro-circuit based half-wave rectifier circuit harvested 3.1 mV DC at a 239.5 Ohm load when the input magnitude is 50 mV while the Schottky diode was unable to convert this ultra-low AC power. This dissertation also provides the analysis of two alternating sources, the oscillatory electromagnetic generator and the piezoelectric energy harvester, to conduct experiments in a more realistic context. The micro-circuit diode shows excellent advantages in electromagnetic generator experiment, the micro-circuit based half-wave rectifier circuit harvested 5.16 mV DC at a 0.5 kOhm load when the input magnitude is 40 mV. However, due to the large leakage current in negative resistance region, this micro-circuit is unable to show advantages in piezoelectric energy harvester applications.
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Davidova, Rebeka. "Ultra-Low Power Electronics for Autonomous Micro-Sensor Applications." Scholar Commons, 2011. http://scholarcommons.usf.edu/etd/3063.
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This thesis presented the research, design and fabrication associated with a unique application of rectenna technology combined with lock-in amplification. An extremely low-power harmonic transponder is conjoined with an interrogator base-station, and utilizing coherent demodulation the Remote Lock-In Amplifier (RLIA) concept is realized. Utilizing harmonic re-radiation with very low-power input, the 1st generation transponder detects a transmitted interrogation signal and responds by retransmitting the second harmonic of the signal. The 1st generation transponder performs this task while using no additional power besides that which accompanies the wireless signal. Demonstration of the first complete configuration provided proof of concept for the RLIA and feasibility of processing relevant information under "zero" power operating conditions with a remote transponder.
Design and fabrication of a new transponder where the existing zero-bias transponder was modified to include a DC bias to the diode-based frequency doubler is presented. Applied bias voltage directly changed the impedance match between the receiving 1.3 GHz antenna and the diode causing a change in conversion loss. Testing demonstrated that a change in conversion loss induces an amplitude modulation on the retransmission of the signal from the transponder. A test of bias sweep at the optimal operating frequency was performed on the 2nd generation transponder and it was seen that a change of ~ 0.1 V in either a positive or negative bias configuration induced an approximate 15 dB change in transponder output power.
A diode-integrated radar detector is designed to sense microwaves occurring at a certain frequency within its local environment and transform the microwave energy to a DC voltage proportional the strength of the signal impinging on its receiving antenna. The output of the radar detector could then be redirected to the bias input of the 2nd generation transponder, where this DC voltage input would cause a change in conversion loss and modulate the retransmitted interrogation signal from the transponder to the base station. When the base station receives the modulated interrogation signal the information sensed by the radar detector is extracted. Simulations and testing results of the fabricated radar detector demonstrate capability of sensing a signal of approximately -53.3 dBm, and accordingly producing a rectified DC voltage output of 0.05 mV. A comparison is made between these findings and the transponder measurements to demonstrate feasibility of pairing the radar detector and the 2nd generation transponder together at the remote sensor node to perform modulation of interrogation signals.
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Eriksson, Gustav. "Towards Long-Range Backscatter Communication with Tunnel Diode Reflection Amplifiers." Thesis, Uppsala universitet, Fasta tillståndets elektronik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-354901.
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Backscatter communication enables wireless communication at a power consumption orders of magnitude lower than conventional wireless communication. Instead of generating new RF-signals backscatter communication leverages ambient signals, such as WiFi-, Bluetooth- or TV-signals, and reflects them by changing the impedance of the antenna. Backscatter communication is known as a short-range communication technique achieving ranges in the order of meters. To improve the communication range, we explore the use of a tunnel diode as an amplifier of the backscattered RF-signal. We developed the amplifier on a PCB-board together with a matching network tuned to give maximum gain at 868 MHz. Our work demonstrates that the 1N3712 tunnel diode can achieve gains up to 35 dB compared to a tag without amplification while having a peak power consumption of 48 μW. With this amplifier the communication distance can be increased by up to two orders of magnitude.
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Guttman, Jeremy. "Polymer-based Tunnel Diodes Fabricated using Ultra-thin, ALD Deposited, Interfacial Films." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1469125487.
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Forestiere, Giuseppe. "Ultra-low power circuits for power management." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-143812.
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Recent developments in energy harvesting techniques allowed implementation of completely autonomous biosensor nodes. However, an energy harvesting device generally demands a customized power management unit (PMU) in order to provide the adequate voltage supply for the biosensor. One of the key blocks within this PMU is a regulation DC-DC converter. In this Master Thesis, the most relevant switched-capacitor DC-DC converter topologies that are suitable for biosensors are compared. The topology that can achieve the best efficiency and has the minimum area is chosen and designed. In order to maintain the supply voltage of the biosensor constant when the input voltage and the output current vary, a traditional Pulse-Frequency-Modulation (PFM) control is employed. An ultra-low-power PFM control circuit is designed to operate in weak inversion region. The post-layout simulations show that the designed DC-DC converter can provide an output voltage of 900mV when the output current varies between 5μA and 40μA. Additionally, the post layout simulations of the entire system, which includes the DC-DC converter and PFM control, show that the selected topology can achieve 87% peak efficiency, when the control losses are included. The main advantages of the proposed topology are its smaller chip area and its high efficiency during processing ultra-low power levels.
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Dancy, Abram P. (Abram Paul). "Power supplies for ultra low power applications." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/10069.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.<br>Includes bibliographical references (p. 101-103).<br>by Abram P. Dancy.<br>M.Eng.
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Vashisth, Abhishek. "LOW DEVICE COUNT ULTRA LOW POWER NEMS FPGA." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1383618426.
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El-Damak, Dina Reda. "Power management circuits for ultra-low power systems." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99821.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 137-145).<br>Power management circuits perform a wide range of vital tasks for electronic systems including DC-DC conversion, energy harvesting, battery charging and protection as well as dynamic voltage scaling. The impact of the efficiency of the power management circuits is highly profound for ultra-low power systems such as implantable, ingestible or wearable devices. Typically the size of the system for such applications does not allow the integration of a large energy storage device. Therefore, extreme energy efficiency of the power management circuits is critical for extended operation time. In addition, flexibility and small form factor are desirable to conform to the human body and reduce the system's over all size. Thus, this thesis presents highly efficient and miniature power converters for multiple applications using architecture and circuit level optimization as well as emerging technologies. The first part presents a power management IC (PMIC) featuring an integrated reconfigurable switched capacitor DC-DC converter using on-chip ferroelectric caps in 130 nm CMOS process. Digital pulse frequency modulation and gain selection circuits allow for efficient output voltage regulation. The converter utilizes four gain settings (1, 2/3, 1/2, 1/3) to support an output voltage of 0.4 V to 1.1 V from 1.5 V input while delivering load current of 20 [mu]A to 1 mA. The PMIC occupies 0.366 mm² and achieves a peak efficiency of 93% including the control circuit overhead at a load current of 500 [mu]A. The second part presents a solar energy harvesting system with 3.2 nW overall quiescent power. The chip integrates self-startup, battery management, supplies 1 V regulated rail with a single inductor and supports power range of 10 nW to 1 [mu]W. The control circuit is designed in an asynchronous fashion that scales the effective switching frequency of the converter with the level of the power transferred. The ontime of the converter switches adapts dynamically to the input and output voltages for peak-current control and zero-current switching. The system has been implemented in 180 nm CMOS process. For input power of 500 nW, the proposed system achieves an efficiency of 82%, including the control circuit overhead, while charging a battery at 3 V from 0.5 V input. The third part focuses on developing an energy harvesting system for an ingestible device using gastric acid. An integrated switched capacitor DC-DC converter is designed to efficiently power sensors and RF transmitter with a 2.5 V regulated voltage rail. A reconfigurable Dickson topology with four gain settings (3, 4, 6, 10) is used to support a wide input voltage range from 0.3 V to 1.1 V. The converter is designed in 65 nm CMOS process and achieves a peak efficiency of 80% in simulation for output power of 2 [mu]W. The last part focuses on flexible circuit design using Molybdenum Disulfide (MoS₂), one of the emerging 2D materials. A computer-aided design flow is developed for MoS₂-based circuits supporting device modeling, circuit simulation and parametric cell-based layout - which paves the road for the realization of large-scale flexible MoS₂ systems.<br>by Dina Reda El-Damak.<br>Ph. D.
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Sirigiri, Vijay Krishna. "Ultra-Low Power Ultra-Fast Hybrid CNEMS-CMOS FPGAs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1291259866.
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Kaps, Jens-Peter E. "Cryptography for ultra-low power devices." Link to electronic dissertation, 2006. http://www.wpi.edu/Pubs/ETD/Available/etd-050406-152129/.
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Aguilar, Ricardo Jose. "Ultra-low power microbridge gas sensor." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43723.
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A miniature, ultra-low power, sensitive, microbridge gas sensor has been developed.The heat loss from the bridge is a function of the thermal conductivity of thegas ambient. Miniature thermal conductivity sensors have been developed for gaschromatography systems [1] and microhotplates have been built with MEMS technologywhich operates within the mW range of power [2]. In this work a lower power microbridgewas built which allowed for the amplification of the effect of gas thermalconductivity on heat loss from the heated microbridge due to the increase inthe surface-to-volume ratio of the sensing element. For the bridge fabrication,CMOS compatible technology, nanolithography, and polysilicon surfacemicromachining were employed. Eight microbridges were fabricated on each die,of varying lengths and widths, and with a thickness of 1 μm.
A voltagewas applied to the sensor and the resistance was calculated based upon thecurrent flow. The response has been tested with air, carbon dioxide, helium,and nitrogen. The resistance and temperature change for carbon dioxide was thegreatest, while the corresponding change for helium was the least. Thus the selectivity of the sensor todifferent gases was shown, as well as the robustness of the sensor. Another aspect of the sensor is that it hasvery low power consumption. The measuredpower consumption at 4 Volts is that of 11.5 mJ for Nitrogen, and 16.1 mJ forHelium.
Thesensor responds to ambient gas very rapidly. The time constant not only showsthe fast response of the sensor, but it also allows for more accuratedetection, given that each different gas produces a different correspondingtime constant from the sensor. The sensor is able to detect differentconcentrations of the same gas as well. Fromthe slopes that were calculated, the resistance change at 5 Volts operation wasfound to be 2.05mΩ/ppm, 1.14 mΩ/ppm at 4.5 Volts, and 0.7 mΩ/ppm at 4 Volts. Thehigher voltages yielded higher resistance changes for all of the gases thatwere tested.
Theversatility of the microbridge has been studied as well. Experiments were donein order to research the ability of a deposited film on the microbridge, inthis case tin oxide, to act as a sensing element for specific gases. In thissetup, the microbridge no longer is the sensing element, but instead acts as aheating element, whose sole purpose is to keep a constant temperature at whichit can then activate the SnO film, making it able to sense methane.
In conclusion,the microbridge was designed, fabricated, and tested for use as an electrothermalgas sensor. The sensor responds to ambient gas very rapidly with differentlevels of resistance change for different gases, purely due to the differencein thermal conductivity of each of the gases. Not only does it have a fastresponse, but it also operates at low power levels. Further research has beendone in the microbridge's ability to act as a heating element, in which the useof a SnO film as the sensing element, activated by the microbridge, was studied.
REFERENCES:
1. D. Cruz,J.P. Chang, S.K. Showalter, F. Gelbard, R.P. Manginell, M.G. Blain," Microfabricated thermal conductivity detector for themicro-ChemLabTM," Sensors andActuators B, Vol. 121 pp. 414-422, (2007).
2. A. G. Shirke, R. E. Cavicchi, S. Semancik, R. H. Jackson, B.G. Frederick, M. C. Wheeler. "Femtomolar isothermal desorption usingmicrohotplate sensors," J Vac Sci TechnolA, Vol. 25, pp. 514-526 (2007).
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Chang, Yin-Ting Melody. "An ultra-low power SAR ADC." Thesis, University of British Columbia, 2009. http://hdl.handle.net/2429/14703.
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Wireless sensor networks are used in variety of applications including environmental
monitoring, industrial control, healthcare, home automation, traffic control, and temperature and pressure monitoring systems. Many one-time use wireless micro sensor applications require ultra-low-power devices due to the limited energy capacity and lifetime of their small-size battery. Many sensor nodes require an analog-to-digital converter (ADC) to convert the analog output of the sensor to digital for storage and/or further processing. In this work, an 8-bit ultra-low-power successive approximation register (SAR) ADC is presented that operates from a low power supply voltage of 1V. The circuit is implemented in a 0.18 μm bulk CMOS technology without using any 10W-VT devices. In terms of active components, this ADC requires one comparator, 18 D flip-flops, several switches, and one voltage doubler. The ADC achieves an effective number of bits of 7, while operating with a sampling rate of 100kS/s and consuming 1.4 μW from a 1 V supply.
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Bielby, Matthew Iain. "Ultra low power cooperative branch prediction." Thesis, University of Edinburgh, 2015. http://hdl.handle.net/1842/14187.
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Branch Prediction is a key task in the operation of a high performance processor. An inaccurate branch predictor results in increased program run-time and a rise in energy consumption. The drive towards processors with limited die-space and tighter energy requirements will continue to intensify over the coming years, as will the shift towards increasingly multicore processors. Both trends make it increasingly important and increasingly difficult to find effective and efficient branch predictor designs. This thesis presents savings in energy and die-space through the use of more efficient cooperative branch predictors achieved through novel branch prediction designs. The first contribution is a new take on the problem of a hybrid dynamic-static branch predictor allocating branches to be predicted by one of its sub-predictors. A new bias parameter is introduced as a mechanism for trading off a small amount of performance for savings in die-space and energy. This is achieved by predicting more branches with the static predictor, ensuring that only the branches that will most benefit from the dynamic predictor’s resources are predicted dynamically. This reduces pressure on the dynamic predictor’s resources allowing for a smaller predictor to achieve very high accuracy. An improvement in run-time of 7-8% over the baseline BTFN predictor is observed at a cost of a branch predictor bits budget of much less than 1KB. Next, a novel approach to branch prediction for multicore data-parallel applications is presented. The Peloton branch prediction scheme uses a pack of cyclists as an illustration of how a group of processors running similar tasks can share branch predictions to improve accuracy and reduce runtime. The results show that sharing updates for conditional branches across the existing interconnect for I-cache and D-cache updates results in a reduction of mispredictions of up to 25% and a reduction in run-time of up to 6%. McPAT is used to present an energy model that suggests the savings are achieved at little to no increase in energy required. The technique is then extended to architectures where the size of the branch predictors may differ between cores. The results show that such heterogeneity can dramatically reduce the die-space required for an accurate branch predictor while having little impact on performance and up to 9% energy savings. The approach can be combined with the Peloton branch prediction scheme for reduction in branch mispredictions of up to 5%.
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Varanasi, Phani Kameswara Abhishikth. "Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages." University of Cincinnati / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1439307481.
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Troesch, Florian. "Novel low duty cycle schemes from ultra wide band to ultra low power." Berlin Logos-Verl, 2009. http://d-nb.info/1000804887/04.
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Midtflå, Nils Kåre. "A 2.4 GHz Ultra-Low-Power Low-Noise-Amplifier." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10955.
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In this thesis different aspects of general low power design and LNA-design have been studied. A new architecture for an ultra low power LNA is proposed and simple simulation results are presented. Simulations show that there should be possible to design a 2.4 GHz LNA that works sufficiently at 200 µA. The proposed architecture achieved a voltage gain over 20 dB from 2.32 to 2.5 GHz, a noise figure of 4.65 dB, IIP3 of -15.45 dBm and a input match of -9.5 dB. There is still a lot of work do and many simulations to perform before one can inconclusively conclude that the proposed architecture is a feasible solution, although the results generated in this thesis seem promising.
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Choi, Kyu-Won. "Hierarchical power optimization for ultra low-power digital systems." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180111/unrestricted/choi%5Fkyu-won%5F200312%5Fphd.pdf.
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Rajagopal, Mohan Kumar. "Ultra low power wearable sleep diagnostic systems." Thesis, Imperial College London, 2014. http://hdl.handle.net/10044/1/38556.
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Sleep disorders are studied using sleep study systems called Polysomnography that records several biophysical parameters during sleep. However, these are bulky and are typically located in a medical facility where patient monitoring is costly and quite inefficient. Home-based portable systems solve these problems to an extent but they record only a minimal number of channels due to limited battery life. To surmount this, wearable sleep system are desired which need to be unobtrusive and have long battery life. In this thesis, a novel sleep system architecture is presented that enables the design of an ultra low power sleep diagnostic system. This architecture is capable of extending the recording time to 120 hours in a wearable system which is an order of magnitude improvement over commercial wearable systems that record for about 12 hours. This architecture has in effect reduced the average power consumption of 5-6 mW per channel to less than 500 uW per channel. This has been achieved by eliminating sampled data architecture, reducing the wireless transmission rate and by moving the sleep scoring to the sensors. Further, ultra low power instrumentation amplifiers have been designed to operate in weak inversion region to support this architecture. A 40 dB chopper-stabilised low power instrumentation amplifiers to process EEG were designed and tested to operate from 1.0 V consuming just 3.1 uW for peak mode operation with DC servo loop. A 50 dB non-EEG amplifier continuous-time bandpass amplifier with a consumption of 400 nW was also fabricated and tested. Both the amplifiers achieved a high CMRR and impedance that are critical for wearable systems. Combining these amplifiers with the novel architecture enables the design of an ultra low power sleep recording system. This reduces the size of the battery required and hence enables a truly wearable system.
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Song, Ying. "Ultra Low Power Receiver Frontend for WBAN Applications." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-31182.
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As integrated circuit technology as well as intelligent computing technology advances, sensor networks which can monitor environments, systems, and complicated interactions in a range of applications are becoming widespread. Wireless Body Area Network(WBAN), which can provide medical, assisted living, sports and entertainment functions for human being, is now enabled and is gradually matching the needs of society. The realization of the WBAN sensor nodes requires ultra-low power wireless communication capability and small area cost. In order to optimize sensor nodes lifetime in WBAN, a duty cycle controlled wake up receiver is proposed in this paper. The receiver is designed to operate with low accuracy frequency references, enabling low power and low cost wireless sensor nodes. Envelope detection architecture is used here to demodulate the on-off keying signal due to its low power consumption. The receiver front end is duty cycled at pulse level, by which the power consumption decreases dramatically. This paper presents the design of a duty cycled wake up receiver with minimized power consumption while keeping adequate sensitivity to detect the input signal. The circuit is designed using 90nm CMOS and the simulation result shows a sensitivity of about -64dBm at 400MHz with a power consumption of 30uW at 0.5V power supply.
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Chen, Jian. "ULTRA LOW POWER READ-OUT INTEGRATED CIRCUIT DESIGN." Wright State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=wright1345480982.
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Cottini, Nicola. "Ultra-Low-Power Vision Systems for Wireless Applications." Doctoral thesis, Università degli studi di Trento, 2012. https://hdl.handle.net/11572/367662.
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Custom CMOS vision sensors could offer large opportunities for ultra-low power applications, introducing novel visual computation paradigms, aimed at closing the large gap between vision technology and energy-autonomous sensory systems. Energy-aware vision could offer new opportunities to all those applications, such as security, safety, environmental monitoring and many others, where communication infrastructures and power supply are not available or too expensive to be provided.
This thesis aims at demonstrating this concept, exploiting the potential of an energy-aware vision sensor, developed at FBK, that extracts the spatial contrast and delivers compressed data. As a case study, a custom stereo-vision algorithm has been developed, taking advantage of the sensor characteristics, targeted to a lower complexity and reduced memory with respect to a standard stereo-vision processing. Under specific conditions, the proposed approach has proven to be very promising, although much work has still to be done both at sensor and at processing levels.The last part of this thesis is focused on the improvement of the custom sensor. A novel vision sensor architecture has been developed, which is based on a proprietary algorithm, developed by a partner of FBK and targeted to surveillance applications. The algorithm is based on adaptive temporal contrast extraction and is very suitable to be implemented at chip level. Although the output of the algorithm has strong similarities with the spatial contrast vision sensor, it relies on temporal contrast rather than spatial one, which is much more robust for event detection applications. A first prototype of ultra-low power adaptive temporal contrast vision sensor has been developed and tested.
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Cottini, Nicola. "Ultra-Low-Power Vision Systems for Wireless Applications." Doctoral thesis, University of Trento, 2012. http://eprints-phd.biblio.unitn.it/778/1/PhDThesisCottini.pdf.
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Custom CMOS vision sensors could offer large opportunities for ultra-low power applications, introducing novel visual computation paradigms, aimed at closing the large gap between vision technology and energy-autonomous sensory systems. Energy-aware vision could offer new opportunities to all those applications, such as security, safety, environmental monitoring and many others, where communication infrastructures and power supply are not available or too expensive to be provided.
This thesis aims at demonstrating this concept, exploiting the potential of an energy-aware vision sensor, developed at FBK, that extracts the spatial contrast and delivers compressed data. As a case study, a custom stereo-vision algorithm has been developed, taking advantage of the sensor characteristics, targeted to a lower complexity and reduced memory with respect to a standard stereo-vision processing. Under specific conditions, the proposed approach has proven to be very promising, although much work has still to be done both at sensor and at processing levels.The last part of this thesis is focused on the improvement of the custom sensor. A novel vision sensor architecture has been developed, which is based on a proprietary algorithm, developed by a partner of FBK and targeted to surveillance applications. The algorithm is based on adaptive temporal contrast extraction and is very suitable to be implemented at chip level. Although the output of the algorithm has strong similarities with the spatial contrast vision sensor, it relies on temporal contrast rather than spatial one, which is much more robust for event detection applications. A first prototype of ultra-low power adaptive temporal contrast vision sensor has been developed and tested.
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Versari, Enrico. "Progetto PCB di un nodo sensore ultra-low power." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/9262/.
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Lo scopo della tesi è la realizzazione di un circuito PCB di un nodo sensore wireless ultra low power per il monitoraggio della temperatura.
Una volta individuati tutti i componenti si è proseguito con l'implementazione del layout del circuito, che poi potrà eventualmente essere posto in produzione
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Payami, Maryam. "Instruction prefetching techniques for ultra low-power multicore architectures." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2016. http://amslaurea.unibo.it/12462/.
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As the gap between processor and memory speeds increases, memory latencies have become a critical bottleneck for computing performance. To reduce this bottleneck, designers have been working on techniques to hide these latencies. On the other hand, design of embedded processors typically targets low cost and low power consumption. Therefore, techniques which can satisfy these constraints are more desirable for embedded domains. While out-of-order execution, aggressive speculation, and complex branch prediction algorithms can help hide the memory access latency in high-performance systems, yet they can cost a heavy power budget and are not suitable for embedded systems. Prefetching is another popular method for hiding the memory access latency, and has been studied very well for high-performance processors. Similarly, for embedded processors with strict power requirements, the application of complex prefetching techniques is greatly limited, and therefore, a low power/energy solution is mostly desired in this context.
In this work, we focus on instruction prefetching for ultra-low power processing architectures and aim to reduce energy overhead of this operation by proposing a combination of simple, low-cost, and energy efficient prefetching techniques. We study a wide range of applications from cryptography to computer vision and show that our proposed mechanisms can effectively improve the hit-rate of almost all of them to above 95%, achieving an average performance improvement of more than 2X. Plus, by synthesizing our designs using the state-of-the-art technologies we show that the prefetchers increase system’s power consumption less than 15% and total silicon area by less than 1%. Altogether, a total energy reduction of 1.9X is achieved, thanks to the proposed schemes, enabling a significantly higher battery life.
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Yazdani, Aminabadi Reza. "Ultra low-power, high-performance accelerator for speech recognition." Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/667429.
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Automatic Speech Recognition (ASR) is undoubtedly one of the most important and interesting applications in the cutting-edge era of Deep-learning deployment, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost, requiring huge memory storage and computational power, which is not affordable for the tiny power budget of mobile devices.
Hardware acceleration can reduce power consumption of ASR systems as well as reducing its memory pressure, while delivering high-performance.
In this thesis, we present a customized accelerator for large-vocabulary, speaker-independent, continuous speech recognition. A state-of-the-art ASR system consists of two major components: acoustic-scoring using DNN and speech-graph decoding using Viterbi search. As the first step, we focus on the Viterbi search algorithm, that represents the main bottleneck in the ASR system.
The accelerator includes some innovative techniques to improve the memory subsystem, which is the main bottleneck for performance and power, such as a prefetching scheme and a novel bandwidth saving technique tailored to the needs of ASR.
Furthermore, as the speech graph is vast taking more than 1-Gigabyte memory space, we propose to change its representation by partitioning it into several sub-graphs and perform an on-the-fly composition during the Viterbi run-time. This approach together with some simple yet efficient compression techniques result in 31x memory footprint reduction, providing 155x real-time speedup and orders of magnitude power and energy saving compared to CPUs and GPUs.
In the next step, we propose a novel hardware-based ASR system that effectively integrates a DNN accelerator for the pruned/quantized models with the Viterbi accelerator. We show that, when either pruning or quantizing the DNN model used for acoustic scoring, ASR accuracy is maintained but the execution time of the ASR system is increased by 33%. Although pruning and quantization improves the efficiency of the DNN, they result in a huge increase of activity in the Viterbi search since the output scores of the pruned model are less reliable. In order to avoid the aforementioned increase in Viterbi search workload, our system loosely selects the N-best hypotheses at every time step, exploring only the N most likely paths. Our final solution manages to efficiently combine both DNN and Viterbi accelerators using all their optimizations, delivering 222x real-time ASR with a small power budget of 1.26 Watt, small memory footprint of 41 MB, and a peak memory bandwidth of 381 MB/s, being amenable for low-power mobile platforms.<br>Los sistemas de reconocimiento automático del habla (ASR por sus siglas en inglés, Automatic Speech Recognition) son sin lugar a dudas una de las aplicaciones más relevantes en el área emergente de aprendizaje profundo (Deep Learning), specialmente en el segmento de los dispositivos móviles. Realizar el reconocimiento del habla de forma rápida y precisa tiene un elevado coste en energía, requiere de gran capacidad de memoria y de cómputo, lo cual no es deseable en sistemas móviles que tienen severas restricciones de consumo energético y disipación de potencia. El uso de arquitecturas específicas en forma de aceleradores hardware permite reducir el consumo energético de los sistemas de reconocimiento del habla, al tiempo que mejora el rendimiento y reduce la presión en el sistema de memoria. En esta tesis presentamos un acelerador específicamente diseñado para sistemas de reconocimiento del habla de gran vocabulario, independientes del orador y que funcionan en tiempo real. Un sistema de reconocimiento del habla estado del arte consiste principalmente en dos componentes: el modelo acústico basado en una red neuronal profunda (DNN, Deep Neural Network) y la búsqueda de Viterbi basada en un grafo que representa el lenguaje. Como primer objetivo nos centramos en la búsqueda de Viterbi, ya que representa el principal cuello de botella en los sistemas ASR. El acelerador para el algoritmo de Viterbi incluye técnicas innovadoras para mejorar el sistema de memoria, que es el mayor cuello de botella en rendimiento y energía, incluyendo técnicas de pre-búsqueda y una nueva técnica de ahorro de ancho de banda a memoria principal específicamente diseñada para sistemas ASR. Además, como el grafo que representa el lenguaje requiere de gran capacidad de almacenamiento en memoria (más de 1 GB), proponemos cambiar su representación y dividirlo en distintos grafos que se componen en tiempo de ejecución durante la búsqueda de Viterbi. De esta forma conseguimos reducir el almacenamiento en memoria principal en un factor de 31x, alcanzar un rendimiento 155 veces superior a tiempo real y reducir el consumo energético y la disipación de potencia en varios órdenes de magnitud comparado con las CPUs y las GPUs. En el siguiente paso, proponemos un novedoso sistema hardware para reconocimiento del habla que integra de forma efectiva un acelerador para DNNs podadas y cuantizadas con el acelerador de Viterbi. Nuestros resultados muestran que podar y/o cuantizar el DNN para el modelo acústico permite mantener la precisión pero causa un incremento en el tiempo de ejecución del sistema completo de hasta el 33%. Aunque podar/cuantizar mejora la eficiencia del DNN, éstas técnicas producen un gran incremento en la carga de trabajo de la búsqueda de Viterbi ya que las probabilidades calculadas por el DNN son menos fiables, es decir, se reduce la confianza en las predicciones del modelo acústico. Con el fin de evitar un incremento inaceptable en la carga de trabajo de la búsqueda de Viterbi, nuestro sistema restringe la búsqueda a las N hipótesis más probables en cada paso de la búsqueda. Nuestra solución permite combinar de forma efectiva un acelerador de DNNs con un acelerador de Viterbi incluyendo todas las optimizaciones de poda/cuantización. Nuestro resultados experimentales muestran que dicho sistema alcanza un rendimiento 222 veces superior a tiempo real con una disipación de potencia de 1.26 vatios, unos requisitos de memoria modestos de 41 MB y un uso de ancho de banda a memoria principal de, como máximo, 381 MB/s, ofreciendo una solución adecuada para dispositivos móviles.
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Hwang, Chi Jeon. "Ultra-low power radio transceiver for wireless sensor networks." Thesis, University of Glasgow, 2010. http://theses.gla.ac.uk/1690/.
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The objective of this thesis is to present the design and implementation of ultra-low power radio transceivers at microwave frequencies, which are applicable to wireless sensor network (WSN) and, in particular, to the requirement of the Speckled Computing Consortium (or SpeckNet). This was achieved through quasi-MMIC prototypes and monolithic microwave integrated circuit (MMIC) with dc power consumption of less than 1mW and radio communication ranges operating at least one metre. A wireless sensor network is made up of widely distributed autonomous devices incorporating sensors to cooperatively monitor physical environments. There are different kinds of sensor network applications in which sensors perform a wide range of activities. Among these, a certain set of applications require that sensor nodes collect information about the physical environment. Each sensor node operates autonomously without a central node of control. However, there are many implementation challenges associated with sensor nodes. These nodes must consume extremely low power and must communicate with their neighbours at bit-rates in the order of hundreds of kilobits per second and potentially need to operate at high volumetric densities. Since the power constraint is the most challenging requirement, the radio transceiver must consume ultra-low power in order to prolong the limited battery capacity of a node. The radio transceiver must also be compact, less than 5×5 mm2, to achieve a target size for sensor node and operate over a range of at least one metre to allow communication between widely deployed nodes. Different transceiver topologies are discussed to choose the radio transceiver architecture with specifications that are required in this project. The conventional heterodyne and homodyne topologies are discussed to be unsuitable methods to achieve low power transceiver due to power hungry circuits and their high complexity. The super-regenerative transceiver is also discussed to be unsuitable method because it has a drawback of inherent frequency instability and its characteristics strongly depend on the performance of the super-regenerative oscillator. Instead, a more efficient method of modulation and demodulation such as on-off keying (OOK) is presented. Furthermore, design considerations are shown which can be used to achieve relatively large output voltages for small input powers using an OOK modulation system. This is important because transceiver does not require the use of additional circuits to increase gain or sensitivity and consequently it achieves lower power consumption in a sensor node. This thesis details the circuit design with both a commercial and in-house device technology with ultra-low dc power consumption while retaining adequate RF performance. It details the design of radio building blocks including amplifiers, oscillators, switches and detectors. Furthermore, the circuit integration is presented to achieve a compact transceiver and different circuit topologies to minimize dc power consumption are described. To achieve the sensitivity requirements of receiver, a detector design method with large output voltage is presented. The receiver is measured to have output voltages of 1mVp-p for input powers of -60dBm over a 1 metre operating range while consuming as much as 420μW. The first prototype combines all required blocks using an in-house GaAs MMIC process with commercial pseudomorphic high electron mobility transistor (PHEMT). The OOK radio transceiver successfully operates at the centre frequency of 10GHz for compact antenna and with ultra-low power consumption and shows an output power of -10.4dBm for the transmitter, an output voltage of 1mVp-p at an operating range of 1 metre for the receiver and a total power consumption of 840μW. Based on this prototype, an MMIC radio transceiver at the 24GHz band is also designed to further improve the performance and reduce the physical size with an advanced 50nm gate-length GaAs metamorphic high electron mobility transistor (MHEMT) device technology.
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Kraimia, Hassen. "Ultra-Low Power RFIC Solutions for Wireless Sensor Networks." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2013. http://tel.archives-ouvertes.fr/tel-01066815.
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Since their emergence, Wireless Sensor Networks (WSN) have been growing continually becoming a key player in many applications such as military tracking, remote monitoring, bio-sensing and home automation. These networks are based on IEEE 802.15.4 standard which is dedicated to low rate wireless personal area networks (LR-WPANs) in the unlicensed radio band (868MHz/915MHz/2.4GHz). Low power consumption, low cost of implementation and high level of integration are the main challenges of these systems. As radio frequency transceiver is one of the most power hungry block in wireless sensor node, power consumption of radio frequency front-end (RFFE) must be reduced. To deal with, several approaches are possible, either at circuit level by investigating operating modes of transistors and merging functionalities or at system level by searching novel demodulation architecture. This thesis explores the specific requirements and challenges for the design of ultra-low power radio frequency integrated circuits (RFICs), leading to the design of a compact demodulator implemented in 65 nm CMOS technology and compatible with all modulation schemes.
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Yasami, Saeid. "Ultra-Low Power RFIC for Space/Medical/Mobile Applications." Thesis, University of Louisiana at Lafayette, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10003754.
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<p> State-of-the-arts design, implementation, and optimization of Ultra-Low Power Radio Frequency Integrated Circuits (ULP RFIC) for medical, space, and mobile applications have been proposed. New approximated formulas in modeling of the circuits and systems for CAD development have been suggested which make the computer simulations more accurate. Algorithm optimizations for faster design time and possible automations compared to traditional and manual implementations are also offered that reduce the final release time of the products in a more systematic way. These design methodologies are based on advancements of IC fabrication in scaling to Nano-meter regimes, improvement of powerful software simulation tools especially at high frequencies, and manipulating novel ideas in development phases. Note that these design proposals are not only limited to space, biomedical, and mobile application; as a matter of fact, they can be used in any chip design and development ranging from smart watch to glasses and etc.</p><p> To have a comprehensive understanding of wireless system design and circuit implementation requires years of experiences and research on multi-disciplinary areas ranging from semiconductor at physic level, circuit analysis, software programming for simulation, test and automation purposes, architecture level, high frequency and RF behavior of components and many more. That is why it has been said the RF design is challenging and takes more years to become an expert on these areas. There are still huge shortages for RF and Analog engineers due to the challenges throughout the world both in industry and academia.</p><p> For the circuits presented in this dissertation, frequencies range from ISM band 2.4GHz for mobile application to 10GHz and 24 GHz in microwave applications. The detail analyses for implementations and simulations have been shown to verify the implementations. Optimizations are presented by extensive analysis and iterative simulations. Solutions and tips to simplify design flows are mentioned throughout the dissertation.</p><p> Chapters begin with introductions and motivations; next, detail discussion and investigation are presented in subsequent sections; finally summaries giving at the end of each chapter. At the end of dissertation, the possible future works and research orientation have been proposed.</p>
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Zheng, Chenyu. "Ultra-low power energy harvesting wireless sensor network design." Thesis, Kansas State University, 2014. http://hdl.handle.net/2097/18812.
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Master of Science<br>Department of Electrical and Computer Engineering<br>William B. Kuhn and Balasubramaniam Natarajan<br>This thesis presents an energy harvesting wireless sensor network (EHWSN) architecture customized for use within a space suit. The contribution of this research spans both physical (PHY) layer energy harvesting transceiver design and appropriate medium access control (MAC) layer solutions. The EHWSN architecture consists of a star topology with two types of transceiver nodes: a powered Gateway Radio (GR) node and multiple energy harvesting (EH) Bio-Sensor Radio (BSR) nodes. A GR node works as a central controller to receive data from BSR nodes and manages the EHWSN via command packets; low power BSR nodes work to obtain biological signals, packetize the data and transmit it to the GR node.
To demonstrate the feasibility of an EHWSN at the PHY layer, a representative BSR node is designed and implemented. The BSR node is powered by a thermal energy harvesting system (TEHS) which exploits the difference between the temperatures of a space suit's cooling garment and the astronaut's body. It is shown that through appropriate control of the duty-cycle in transmission and receiving modes, it is possible for the transceiver to operate with less than 1mW power generated by the TEHS. A super capacitor, energy storage of TEHS, acts as an energy buffer between TEHS and power consuming units (processing units and transceiver radio). The super capacitor charges when a BSR node is in sleep mode and discharges when the node is active. The node switches from sleep mode to active mode whenever the super capacitor is fully charged. A voltage level monitor detects the system's energy level by measuring voltage across the super capacitor.
Since the power generated by the TEHS is extremely low(less than 1mW) and a BSR node consumes relatively high power (approximately 250mW) during active mode, a BSR node must work under an extremely low duty cycle (approximately 0.4%). This ultra-low duty cycle complicates MAC layer design because a BSR node must sleep for more than 99.6% of overall operation time. Another challenge for MAC layer design is the inability to predict when the BSR node awakens from sleep mode due to unpredictability of the harvested energy. Therefore, two feasible MAC layer designs, CSA (carrier sense ALOHA based)-MAC and GRI (gateway radio initialized)-MAC, are proposed in this thesis.
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Yuksel, Kaan. "Universal hashing for ultra-low-power cryptographic hardware applications." Link to electronic thesis, 2004. http://www.wpi.edu/Pubs/ETD/Available/etd-0428104-195331.
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Thesis (M.S.)--Worcester Polytechnic Institute.<br>Keywords: self-powered; universal hashing; ultra-low-power; message authentication codes; provable security. Includes bibliographical references (p. 55-61).
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Zhang, Dai. "Design of Ultra-Low-Power Analog-to-Digital Converters." Licentiate thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-79276.
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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.
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Leong, Kennith Kin. "Utilising power devices below 100 K to achieve ultra-low power losses." Thesis, University of Warwick, 2011. http://wrap.warwick.ac.uk/46807/.
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One of the main trend in the development of high power electric machines (motors, generators) is to replace the magnetic components with superconducting wires, this inevitably leads to a critical requirement from the industry (Converteam) to operate power devices at cryogenic temperatures. However, the current understanding of the behaviour power devices at cryogenic temperatures is limited, especially below the liquid nitrogen temperature of 77 K. This is a problem since most of the superconducting wires operate at temperatures below 77 K. Furthermore, it is uncertain which device type is better, if at all suited to cryogenic operation. In order to answer this, a thorough analysis of the known cryogenic behaviour of all the generic power devices was performed, including the physical behaviour of silicon at cryogenic temperatures. It is concluded that the power MOSFET is the best likely candidate for cryogenic operation. To understand the cryogenic behaviour of silicon power MOSFETs especially between the temperatures of 20 K and 100 K, a cryogenic measurement system was built to characterise different types of power MOSFETs. All the measured power MOSFETs exhibited large improvement in on-state resistance down to 50 K and non-linear degradation of breakdown voltages with lower temperatures. Various behaviour was observed below 50 K including carrier freeze-out, electric field dependent ionisation of free charge carriers and large variations in on-state resistance between identical devices. Several power Schottky diodes were also characterised and all exhibited merged PiN Schottky diode behaviour at cryogenic temperatures. Non-silicon devices such as silicon carbide power MOSFETs and gallium nitride HEMTs were also measured. Silicon carbide exhibited no improvements at cryogenic temperatures, whereas gallium nitride HEMTs may prove to be the best power device to be utilised in future cryogenic applications. Since unusual behaviour was observed in power MOSFETs below 50 K, an attempt was made to explain these phenomena using theoretical equations of semiconductor physics and analytical models of power MOSFETs. The author suggested that careful control of the dopant concentration at the accumulation region below the oxide gate is required to improve the power MOSFET operations below 50 K. Moreover, the super-junction power MOSFETs could be optimised for better cryogenic operation. It is the intention of this work to demonstrate the benefits of power MOSFET cryogenic operation in a realistic industrial application. A demonstration model was designed and simulated, this circuit uses a back-to-back power MOSFETs configuration to control the freewheeling current flowing through a high temperature superconducting coil. The electrical and thermal design of the model has been described, simulated and presented in this work.
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Joyner, Valencia M. (Valencia Margie) 1976. "A low power display architecture for organic light emitting diode microdisplays." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/9460.
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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (p. 75-78).<br>Organic light-emitting diode (OLED) devices offer a very promising alternative to existing flat panel display technologies, such as liquid crystal displays (LCD) that currently dominate the market. OLED displays offer very attractive characteristics, including higher luminous, larger viewing angle, and low-power consumption, over the established LCD technology. The ability to integrate OLED devices on a silicon microchip is one of the most favorable characteristics of this new technology. The primary goal of this research project is to implement a low-power display driver circuit for an OLED microdisplay. The implementation will be chosen based on the outcome of a feasibility study aimed at investigating the various options available for addressing the display and the design requirements imposed by the operation of the OLED. There are three primary design options to be considered: 1 ). Passive Matrix Addressing with sequentially addressed rows/columns, 2). Active Matrix Addressing with sequentially addressed rows/columns and dynamic storage at each pixel, and 3). Active Matrix Addressing with sequentially addressed rows/columns and static storage at each pixel. Each implementation is compared in terms of the overall power consumed in driving the high capacitance row and column lines in the display matrix.<br>by Valencia M. Joyner.<br>M.Eng.
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Eibna, Halim Md Zubaer. "Passively mode-locked picosecond Nd:KGW laser with low quantum defect diode pumping." Astro Ltd, 2016. http://hdl.handle.net/1993/31913.
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Solid-state lasers are capable of providing versatile output characteristics with greater flexibility compared to other popular laser systems. Lasing action has been achieved in many hundreds of solid-state media, but Nd-ion doped gain media are widely used to reach high power levels with short pulses.
In this work, commercially available Nd:KGW crystal served as a gain medium to achieve pulsed operation at 1067 nm. This laser crystal offers large stimulated emission crosssection and gain bandwidth which facilitates generation of high peak power pulses in the picosecond regime. The KGW crystal is monoclinic and biaxial in structure, and anisotropic in its optical and thermal properties. Due to poor thermal conductivity, this crystal can be operated within a limited power range before crystal fracture takes place. To reduce the amount of heat deposited in the gain media, we introduced a new pumping wavelength of 910 nm which reduces the quantum defect by more than 45%.
Continuous-wave laser operation was optimized to operate in mode-locked regime. In order to achieve short light pulses from the continuous-wave laser, one of the end mirrors was replaced by a semiconductor saturable absorber mirror (SESAM) to generate 2.4 ps pulses at a repetition rate of 83.8 MHz. An average output power of 87 mW was obtained at lasing wavelength of 1067 nm and the beam was nearly diffraction limited with M^2 < 1.18. The peak power of the generated pulses was 427 W and energy of each pulse was >1 nJ. Pumping the crystal at longer wavelength (910 nm) reduced the thermal lensing of the crystal by half when compared to conventional pumping at shorter wavelength (808 nm). To the best of our knowledge, this is the first time passive mode-locking of a Nd:KGW laser was explored using the pump wavelength at 910 nm.<br>February 2017
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Radmanesh, Seyed Mohammad Ali. "Ultra-low Temperature Properties of Correlated Materials." ScholarWorks@UNO, 2018. https://scholarworks.uno.edu/td/2511.
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Abstract
After the discovery of topological insulators (TIs), it has come to be widely recognized that topological states of matter can actually be widespread. In this sense, TIs have established a new paradigm about topological materials. Recent years have seen a surge of interest in topological semimetals, which embody two different ways of generalizing the effectively massless electrons to bulk materials. Dirac and, particularly, Weyl semimetals should support several transport and optical phenomena that are still being sought in experiments. A number of promising experimental results indicate superconductivity in members of half-Hesuler semimetals which realize the mixing singlet and triplet pairing symmetry. We now turn to results we got through the work on topological semimetals. This work presents quantum high field transports on Dirac and Weyl topological semimetals including Sr1-yMn1-zSb2 (y, z < 0.1), YbMnBi2 and TaP. In case of Sr1-yMn1-zSb2 (y, z < 0.1), massless relativistic fermion was reported with m* = 0.04-0.05m0. This material presented a ferromagnetic order for in 304 K < T < 565 K, but a canted antiferromagnetic order with a net ferromagnetic component for T < 304 K. These are considered striking features of Dirac fermions For YbMnBi2, we reported the unusual interlayer quantum transport behavior in magnetoresistivity, resulting from the zeroth LL mode observed in this time reversal symmetry breaking type II Weyl semimetal. Also, for Weyl semimetal TaP the measurements probed multiple Fermi pockets, from which nontrivial π Berry phase and Zeeman splitting were extracted. Our ultra-low penetration depth measurements on half-Heuslers YPdBi and TbPdBi revealed a power- law behavior with n= 2.76 ± 0.04 for YPdBi samples and n=2.6 ± 0.3 for TbPdBi sample. We may conclude the exponent n > 2 implies nodless superconducting gap in our samples. Also, we found that despite the increase in magnetic correlations from YPdBi to TbPdBi, superconductivity remains robust in both systems which indicates that AF fluctuations do not play a major role in superconducting mechanism.
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Bargagli-Stoffi, Agnese [Verfasser]. "Ultra low-voltage, low-power amplifiers in deep submicrometer CMOS / Agnese Bargagli-Stoffi." Aachen : Shaker, 2006. http://d-nb.info/116651336X/34.
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Srivastava, Amit. "Design of Ultra Low Power Transmitter for Wireless medical Application." Thesis, Linköping University, Electronic Devices, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18408.
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<p>Significant advanced development in the field of communication has led many designers and healthcare professionals to look towards wireless communication for the treatment of dreadful diseases. Implant medical device offers many benefits, but design of implantable device at very low power combines with high data rate is still a challenge. However, this device does not rely on external source of power. So, it is important to conserve every joule of energy to maximize the lifetime of a device. Choice of modulation technique, frequency band and data rate can be analyzed to maximize battery life.</p><p>In this thesis work, system level design of FSK and QPSK transmitter is presented. The proposed transmitter is based on direct conversion to RF architecture, which is known for low power application. Both the transmitters are designed and compared in terms of their performance and efficiency. The simulation results show the BER and constellation plots for both FSK and QPSK transmitter.</p>
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Eidenvall, Per, and Nils Gran. "High Level Ultra Low Power Transmitters for the MICS Standard." Thesis, Linköpings universitet, Elektroniska komponenter, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-62656.
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Today, medical implants such as cardiac pacemakers, neurostimulators, hearing aids anddrug delivery systems are increasinglymore important and frequently used in the health caresystem. This type of devices have historically used inductive coupling as communicationmedium. Newdemands on accessibility and increased performance in technology drives newresearch toward using radio communications. The FCCMICS radio standard are specificallydevoted for implantable devices.Basically all published research on transmitters in this area are using frequency shift keying(FSK) modulation. The purpose of this thesis is to explore the viability of using phase shiftkeying (PSK) modulation in ultra low power transmitters and suggest suitable architectures.
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Song, Jinxin. "Ultra low power Analog-to-Digital Converter for Biomedical Devices." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-44790.
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The biomedical devices often operate only with a battery, e.g., blood glucose monitor, pacemaker. Therefore, it is desirable to fully utilize the energy without sacrificing the performance of the system. The Analog-to-Digital Converter (ADC), as a key component of most of the biomedical devices, needs to be designed for minimum power consumption by exploring various techniques from system level to circuit level. In addition, the nature of bio-signal provides more alternatives to reduce the power. In this thesis work, an 8 bit 11 kS/s modified algorithmic analog-to-digital converter for biomedical applications is proposed. All analog components are designed at circuit level using a 90 nm CMOS technology and digital components are implemented using Verilog-A language in Cadence. The ADC is operating in current mode at sub-threshold region with only 0.5 V supply voltage with an input current from 0 nA to 512 nA. The ADC is designed based on a top-down design with bottom-up verification approach. The system level model is described using top level language and then the circuit level is created and verified using Cadence tools according to the system level model. The INL and DNL obtained from simulation is -1/+0.8 LSB and -0.9/+1 LSB respectively. The SNDR is 47 dB (7.5 ENOB) for a -0.2 dBFS at 1 kHz sinusoidal signal. The power consumption is 2.83 μW without biasing and 4μW with biasing.
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Lu, Chao. "Vibration energy scavenging and management for ultra low power applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LU.
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Zhang, Dai. "Ultra-Low-Power Analog-to-Digital Converters for Medical Applications." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110387.
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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successiveapproximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs. The power consumption of SAR ADC is analyzed and its lower bounds are formulated. At low resolution, power is bounded by minimum feature sizes; while at medium to high resolution, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors. Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13μm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitarray capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-VT design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-μW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binary-weighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption.
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Verma, Naveen. "Ultra-low-power SRAM design in high variability advanced CMOS." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/53305.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 163-181).<br>Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target applications. Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia handsets, etc.) are an important class of applications driving ultra-low-power SRAMs. This thesis analyzes the energy of an SRAM sub-array. Since supply- and threshold-voltage have a strong effect, targets for these are established in order to optimize energy. Despite the heavy emphasis on leakage-energy, analysis of a high-density 256x256 sub-array in 45nm LP CMOS points to two necessary optimizations: (1) aggressive supply-voltage reduction (in addition to Vt elevation), and (2) performance enhancement. Important SRAM metrics, including read/write/hold-margin and read-current, are also investigated to identify trade-offs of these optimizations. Based on the need to lower supply-voltage, a 0.35V 256kb SRAM is demonstrated in 65nm LP CMOS. It uses an 8T bit-cell with peripheral circuit-assists to improve write-margin and bit-line leakage. Additionally, redundancy, to manage the increasing impact of variability in the periphery, is proposed to improve the area-offset trade-off of sense-amplifiers, demonstrating promise for highly advanced technology nodes. Based on the need to improve performance, which is limited by density constraints, a 64kb SRAM, using an offset-compensating sense-amplifier, is demonstrated in 45nm LP CMOS with high-density 0.25[mu]m2 bit-cells.<br>(cont.) The sense-amplifier is regenerative, but non -strobed, overcoming timing uncertainties limiting performance, and it is single-ended, for compatibility with 8T cells. Compared to a conventional strobed sense-amplifier, it achieves 34% improvement in worst-case access-time and 4x improvement in the standard deviation of the access-time.<br>by Naveen Verma.<br>Ph.D.
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Zhao, Xin Ph D. Massachusetts Institute of Technology. "III-V vertical nanowire transistor for ultra-low power applications." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/111256.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Materials Science and Engineering, 2017.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 156-166).<br>Combining the superior carrier transport properties and flexible band structure engineering from III-V materials and ultimate scalability of vertical nanowire (VNW) device architecture, III-V VNW transistors are promising to extend Moore's law further than any other device technology. In this thesis, III-V VNW transistor technology has been pioneered via a top down approach for logic applications in future ultra-low power systems. Process flow and critical modules for sub-10 nm VNW transistors are developed from scratch. A novel dry etch technique based on BCl₃/SiCl₄/Ar chemistry for fabricating sub-20 nm III-V nanostructures with smooth, vertical sidewall and high aspect ratio (> 10) is developed. Digital etch (DE) is shown to mitigate the dry etch damage and reduce NW diameter below 10 nm in a controllable fashion while preserving the sidewall roughness and NW shape. Top-down InGaAs VNW MOSFET is demonstrated for the first time. Record Ion of 224 μA/μm is obtained at Ioff = 100 nA/μm with Vdd = 0.5 V in third generation devices. With novel solvent-based, switching characteristics are observed in devices with diameter as small as 14 nm. The impact of the intrinsic source/drain asymmetry on the device electrical characteristics is studied in detail, highlighting the importance of uniform NW diameter. The first experimental demonstration of III-V VNW TFETs with an InGaAs/InAs heterojunction fabricated by a top-down approach is introduced. Second generation TFETs demonstrate sub-thermal subthreshold characteristics over two orders of magnitude of current and a record high I60 in any experimental TFETs for Vds < 1 V at the time of device fabrication. The comparison of two generations of TFETs confirms oxide/semiconductor interface trapassisted tunneling as the source of significant temperature dependence in the first device generation. Detailed analysis on the conductance-voltage characteristics on both generations of devices reveal a 100-120 mV/dec steepness of Urbach tails in the VNW TFETs.<br>by Xin Zhao.<br>Ph. D.
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Verma, Naveen. "An ultra low power ADC for wireless micro-sensor applications." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34462.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 143-147).<br>Autonomous micro-sensor nodes rely on low-power circuits to enable energy harvesting as a means of sustaining long-term, maintenance free operation. This work pursues the design of an ultra low-power analog-to-digital converter (ADC) whose sampling rate and resolution can be scaled to dynamically recover power savings. The proposed ADC has a sampling rate of 0-100 kS/s and a resolution of either 12 or 8 bits. The design is based on the successive approximation register architecture (SAR), which is suitable for scaleable, micro-power operation. Specifically, the number of active blocks has been minimized to allow efficient power-gating, which, in-turn, has been leveraged to implement scalability features. Several new techniques to improve the efficiency of the ADC have been developed and employed. Analog offset calibration in the regenerative latch is used, to improve the power-delay product of the comparator; pre-amplifier cascade optimization is performed with consideration to thermal noise limitations; weak-inversion biasing is employed in the active amplifiers; passive switch-capacitors are used to generate the auto-zero reference voltage such the CMRR of the ADC is maximized;<br>(cont.) integrated capacitors are laid-out in a new common-centroid arrangement that minimizes edge effects; finally, the sub-DAC's transmission gain is adjusted to reduce non-linearities caused by the attenuating effects of parasitics. The ADC has been fabricated in a 0.18,um CMOS technology. All circuits are powered using a 1V supply, though bootstrapping is used internally. At a resolution of 12-bits, and a sampling rate of 100 kS/s, the power consumption of the entire ADC core is 26/MW. The SNDR of the converter with a 48 kHz input tone is 65dB (10.55 ENOB) and the SFDR is 71dB. The power consumption decreases linearly with sampling rate, and is measured to be approximately 200nW at 500 S/s.<br>by Naveen Verma.<br>S.M.
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Zhou, Dao. "Ultra Low-Power Wireless Sensor Node for Structural Health Monitoring." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/31103.
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Structural Health Monitoring (SHM) is the technology of monitoring and assessing the condition of aerospace, civil, and mechanical infrastructures using a sensing system integrated into the structure. Among variety of SHM approaches, impedance-based method is efficient for local damage detection. This thesis focuses on system level concerns for impedance-based SHM. Two essential requirements are reached in the thesis: reduction of power consumption of wireless SHM sensor, and compensation of temperature dependency on impedance. The proposed design minimizes power by employing on-board signal processing, and by eliminating power hungry components such as ADC and DAC. The prototype implemented with MSP430 micro controller is verified to be able to handle SHM operation and wireless communication with extremely low-power: 0.15 mW during the inactive mode and 18 mW during the active mode. Each SHM operation takes about 13 seconds to consume 236 mJ. When our ASN-2 operates once in every four hours, it can run for about 2.5 years with two AAA-size batteries. To compensate for temperature change, we proposed an algorithm to select a small subset of baseline profiles for some critical temperatures and to estimate the baseline profile for a given ambient temperature through interpolation. Experimental results show that our method reduces the number of baseline profiles to be stored by 45%, and estimates the baseline profile of a given temperature accurately.<br>Master of Science
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Corbishley, Phil. "Ultra low power circuits for a miniature apnoea detection device." Thesis, Imperial College London, 2007. http://hdl.handle.net/10044/1/8467.
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Chen, Du. "An ultra-low power neural recording system using pulse representations." [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0013814.
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Aulery, Alexis. "Architecture of Ultra Low Power Node for Body Area Network." Thesis, Lorient, 2016. http://www.theses.fr/2016LORIS419/document.
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Le réseau de capteurs porté est une technologie d’avenir prometteuse à multiple domaines d’application allant du médical à l’interface homme machine. Le projet BoWI a pour ambition d’évaluer la possibilité d’élaborer un réseau de capteurs utilisable au quotidien dans un large spectre d’applications et ergonomiquement acceptable pour le grand public. Cela induit la nécessité de concevoir un nœud de réseau ultra basse consommation pour à la fois convenir à une utilisation prolongée et sans encombrement pour le porteur. La solution retenue est de concevoir un nœud capable de travailler avec une énergie comparable à ce que l’état de l’art de la récolte d’énergie est capable de fournir. Une solution ASIC est privilégiée afin de tenir les contraintes d’intégration et de basse consommation. La conception de l’architecture dédiée a nécessité une étude préalable à plusieurs niveaux. Celle-ci comprend un état de l’art de la récolte d’énergie afin de fixer un objectif de budget énergie/puissance de notre système. Une étude des usages du système a été nécessaire notamment pour la reconnaissance postures afin de déterminer les cas d’applications types. Cette étude a conduit au développement d’algorithmes permettant de répondre aux applications choisies tout en s’assurant de la viabilité de leurs implantations. Le budget énergie fixé est un objectif de 100µW. Les applications choisies sont la reconnaissance de posture, la reconnaissance de geste et la capture de mouvement. Les solutions algorithmiques choisis sont une fusion de données de capteurs inertiels par Filtre de Kalman étendu (EKF) et l’ajout d’une classification par analyse en composante principale. La solution retenue pour obtenir des résultats d’implémentation est la synthèse de haut niveau qui permet un développement rapide. Les résultats de l’implantation matérielle sont dominés principalement par l’EKF. À la suite de l’étude, il apparait qu’il est possible avec une technologie 28nm d’atteindre les objectifs de budget énergie pour la partie algorithme. Une évaluation de la gestion haut niveau de tous les composants du nœud est également effectuée afin de donner une estimation plus précise des performances du système dans un cas d’application réel. Une contribution supplémentaire est obtenue avec l’ajout de la détection d’activité qui permet de prédire la charge de calcul nécessaire et d’adapter dynamiquement l’utilisation des ressources de traitement et des capteurs afin d’optimiser l’énergie en fonction de l’activité<br>Wireless Body Sensor Network (WBSN) is a promising technology that can be used in a lot of application domains from health care to Human Machine Interface (HMI). The BoWI project ambition is to evaluate and design a WBSN that can be used in various applications with daily usage and accessible to the public. This necessitates to design a ultra-low power node that reach a day of use without discomfort for the user. The elected solution is to design a node that operates with the power budget similar to what can be provided by the state of the art of the energy harvesting. An Application Specific Integrated Circuit (ASIC) solution is privileged in order to meet the integration and low power constraints. Designing the dedicated architecture required a preliminary study at several level which are: a state of the art of the energy harvesting in order to determine the objective of energy/power budget of our system, A study of the usage of the system to determine and select typical application cases. A study of the algorithms to address the selected applications while considering the implementation viability of the solutions. The power budget objective is set to 100µW. The application selected are the posture recognition, the gesture recognition and the motion capture. The algorithmic solution proposed are a data-fusion based on an Extended Kalman FIlter (EKF) with the addition of a classification using Principal Component Analysis (PCA). The implementation tool used to design the architecture is an High Level Synthesis (HLS) solution. Implementation results mainly focus on the EKF since this is by far the most power consuming digital part of the system. Using a 28nm technology the power budget objective can be reached for the algorithmic part. A study of the top level management of all components of the node is done in order to estimate performances of the system in real application case. This is possible using an activity detection which dynamically estimates the computing load required and then save a maximum of energy while the node is still
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Ragavan, Rengarajan. "Reconfigurable FSM for Ultra-Low Power Wireless Sensor Network Nodes." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-100121.
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Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour.In order to achieve flexibility in node functionality, it is common to adopt reconfigurablearchitecture for WSN nodes. FPGA-based architectures are popular reconfigurable architectures bywhich WSN nodes can be programmed to take up different roles across time. Area and power are themajor overheads in FPGA based architectures, where interconnect consumes more power and area thanlogic cells. The contemporary WSN standard requires longer battery life and micro size nodes for easyplacement and maintenance-free operation for years together.Three solutions have been studied and evaluated to approach this problem: 1) Homogenousembedded FPGA platform, 2) Power gated reconfigurable finite state machines and 3) Pass transistorlogic (PTL) based reconfigurable finite state machines. Embedded FPGA is a CMOS 65nm customdeveloped small homogenous FPGA which holds the functionality of the WSN nodes and it will bedynamically reconfigured from time to time to change the functionality of the node. In Power gatedreconfigurable FSM architecture, the functionality of the node is expressed in the form of finite statemachines, which will be implemented in a LUT based power gated design. In PTL based reconfigurablefinite state machine architecture, the finite state machines are completely realized using PTL basedcustom designed sets of library components. Low power configuration memory is used to dynamicallyreconfigure the design with various FSMs at different times.
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Polonelli, Tommaso <1990>. "Ultra-low power IoT applications: from transducers to wireless protocols." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amsdottorato.unibo.it/9604/1/Polonelli_Tommaso_tesi.pdf.
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This dissertation aims to explore Internet of Things (IoT) sensor nodes in various application scenarios with different design requirements. The research provides a comprehensive exploration of all the IoT layers composing an advanced device, from transducers to on-board processing, through low power hardware schemes and wireless protocols for wide area networks.
Nowadays, spreading and massive utilization of wireless sensor nodes pushes research and industries to overcome the main limitations of such constrained devices, aiming to make them easily deployable at a lower cost. Significant challenges involve the battery lifetime that directly affects the device operativity and the wireless communication bandwidth. Factors that commonly contrast the system scalability and the energy per bit, as well as the maximum coverage.
This thesis aims to serve as a reference and guideline document for future IoT projects, where results are structured following a conventional development pipeline. They usually consider communication standards and sensing as project requirements and low power operation as a necessity.
A detailed overview of five leading IoT wireless protocols, together with custom solutions to overcome the throughput limitations and decrease the power consumption, are some of the topic discussed. Low power hardware engineering in multiple applications is also introduced, especially focusing on improving the trade-off between energy, functionality, and on-board processing capabilities. To enhance these features and to provide a bottom-top overview of an IoT sensor node, an innovative and low-cost transducer for structural health monitoring is presented. Lastly, the high-performance computing at the extreme edge of the IoT framework is addressed, with special attention to image processing algorithms running on state of the art RISC-V architecture. As a specific deployment scenario, an OpenCV-based stack, together with a convolutional neural network, is assessed on the octa-core PULP SoC.