Journal articles: 'Ultra Low Power CMOS RF'

1

Jin, Jie, Xianming Wu, and Zhijun Li. "Ultra low power mixer with out-of-band RF energy harvesting for wireless sensor networks applications." Engineering review 40, no. 1 (January 27, 2020): 1–6. http://dx.doi.org/10.30765/er.40.1.01.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

An ultra low power mixer with out-of-band radio frequency (RF) energy harvesting suitable for the wireless sensors network (WSN) application is proposed in this paper. The presented mixer is able to harvest the out-of-band RF energy and keep it working in ultra low power condition and extend the battery life of the WSN. The mixer is designed and simulated with Global Foundries ’ 0.18 μ m CMOS RF process, and it operates at 2.4GHz industrial, scientific, and medical (ISM) band. The Cadence IC Design Tools post-layout simulation results demonstrate that the proposed mixer consumes 248 μ W from a 1V supply voltage. Furthermore, the power consumption can be reduced to 120.8 μ W by the out-of-band RF energy harvesting rectifier.

2

La Rosa, Roberto, Danilo Demarchi, Sandro Carrara, and Catherine Dehollain. "High-Efficiency Reconfigurable CMOS RF-to-DC Converter System for Ultra-Low-Power Wireless Sensor Nodes with Efficient MPPT Circuitry." Chips 3, no. 1 (March 12, 2024): 49–68. http://dx.doi.org/10.3390/chips3010003.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

This paper presents a novel CMOS RF-to-DC converter for ultra-low-power wireless sensor nodes powered by RF wireless power transfer. The proposed converter achieves 10% higher power conversion efficiency than a conventional rectifier, with only a 1% increase in power consumption. The system employs a reconfigurable Dickson topology, operates on the unlicensed 868 MHz ISM band, and includes a built-in power-efficient MPPT system architecture. Experimental measurements show a maximum power conversion efficiency of 55% in the power range from −22 dBm to 0 dBm, with a power sensitivity of −22 dBm for a DC output voltage of 2.4 V. The proposed converter offers a promising solution for efficient wireless power transfer and energy harvesting in ultra-low-power wireless sensor nodes.

3

Tan, Gim Heng, Roslina Mohd Sidek, Harikrishnan Ramiah, Wei Keat Chong, and De Xing Lioe. "Ultra-Low-Voltage CMOS-Based Current Bleeding Mixer with High LO-RF Isolation." Scientific World Journal 2014 (2014): 1–5. http://dx.doi.org/10.1155/2014/163414.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm2.

4

Haddad, Fayrouz, Wenceslas Rahajandraibe, and Imen Ghorbel. "RF CMOS Oscillators Design for autonomous Connected Objects." E3S Web of Conferences 88 (2019): 05001. http://dx.doi.org/10.1051/e3sconf/20198805001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

Voltage controlled oscillator (VCO) is an integral part of IoT wireless transceiver components. In this paper, VCOs operating around 2.4 GHz have been designed in CMOS technology. The relation between their components and specifications is studied for their performance optimization. Ultra-low power, less than 270 µW, has been obtained, while performing a frequency tuning range of about 10% between 2.1 and 2.4 GHz. Investigations on phase noise performance have been also achieved.

5

Taris, Thierry, Jennifer Desevedavy, Frederic Hameau, Patrick Audebert, and Dominique Morche. "Inductorless Multi-Mode RF-CMOS Low Noise Amplifier Dedicated to Ultra Low Power Applications." IEEE Access 9 (2021): 83431–40. http://dx.doi.org/10.1109/access.2021.3085990.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Fenni, S. ,., F. Haddad, A. ,. Slimane, R. ,. Touhami, and W. Rahajandraibe. "Design of Monolithic RF CMOS Sub-mW Self-Oscillating-Mixers." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (April 21, 2023): 23–27. http://dx.doi.org/10.37394/23201.2023.22.4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In this paper, different topologies of RF self-oscillating mixers (SOM), stacking the voltage controlled oscillator (VCO) and the mixer on top of each other, are assessed. Their design considerations to address sub-mW operation suitable to ultra-low power applications are presented. Two configurations of SOM circuits are implemented in 130nm CMOS technology. The obtained results are presented and performances in terms of gain, noise, linearity, area, power consumption and stability over process and mismatch are compared and discussed.

7

Huang, Shuigen, Min Lin, Zongkun Zhou, and Xiaoyun Li. "An ultra-low-power 2.4 GHz RF receiver in CMOS 55 nm process." IEICE Electronics Express 15, no. 5 (2018): 20180016. http://dx.doi.org/10.1587/elex.15.20180016.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Murad, S. A. Z., Muhammad M. Ramli, A. Azizan, M. N. M. Yasin, and I. S. Ishak. "Ultra-Low Power CMOS RF Mixer for Wireless Sensor Networks Application: A Review." MATEC Web of Conferences 97 (2017): 01037. http://dx.doi.org/10.1051/matecconf/20179701037.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Jayamon, Ashik C., Ankur Mukherjee, Sai Chandra Teja R., and Ashudeb Dutta. "High-efficiency CMOS charge pump for ultra-low power RF energy harvesting applications." Integration 96 (May 2024): 102161. http://dx.doi.org/10.1016/j.vlsi.2024.102161.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Akhter, Muhammad Ovais, and Najam Muhammad Amin. "Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology." Mathematical Problems in Engineering 2021 (November 19, 2021): 1–12. http://dx.doi.org/10.1155/2021/3364016.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

11

Hashimoto, Takuma, Hikaru Nekozuka, Yoshitaka Toeda, Masayuki Otani, Yasuhiko Fukuoka, and Toru Tanzawa. "A −31.7 dBm Sensitivity 0.011 mm2 CMOS On-Chip Rectifier for Microwave Wireless Power Transfer." Electronics 12, no. 6 (March 15, 2023): 1400. http://dx.doi.org/10.3390/electronics12061400.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

This paper pursued both the lower operating power limit and small area of on-chip rectifiers for microwave wireless power transfer (MWPT). RF–DC charge pump rectifiers can operate in the fast switching limit at a high frequency of 920 MHz even with a small stage capacitor Cin of 100 fF, which contributes to an area reduction in the on-chip rectifiers. Circuit design starts with Cin determined as small as possible, followed by the determination of switching transistors and the number of stages. Even at an extremely low input power of 1 μW, wiring resistance in RF inputs is critical. Routing of the RF inputs is designed in line with stage capacitors. Bonding pad structure also affects the lower input power limit. Ground-shielded pad design can reduce the lower limit. Various types of RF–DC charge pump rectifiers are fabricated in 65 nm CMOS. An ultra-low-power diode RF–DC charge pump rectifier with 32 stages had a lower input power limit of −31.7 dBm at an output voltage of 1.0 V. Its small silicon area of 0.011 mm2 allows RF–DC rectifiers to be integrated in sensor ICs. More advanced technology providing MIM capacitors with higher capacitance density and placing switching MOSFETs under the MIM capacitors will further reduce the area of RF–DC charge pump rectifiers, allowing them to be integrated in sensor ICs.

12

Sen, Dipanjan, Savio J. Sengupta, Swarnil Roy, Manash Chanda, and Subir K. Sarkar. "Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 457–70. http://dx.doi.org/10.2174/2210681209666190730170031.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

13

Ghosh, Sumalya, Bishnu Prasad De, K. B. Maji, R. Kar, D. Mandal, and A. K. Mal. "Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications." Journal of Circuits, Systems and Computers 29, no. 16 (June 30, 2020): 2050261. http://dx.doi.org/10.1142/s0218126620502618.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In this paper, an evolutionary computation-based optimal design of low power, high gain inductive source degenerated CMOS cascode low noise amplifier (LNA) circuit is presented for 2.4[Formula: see text]GHz frequency. The main challenge for the design of radio frequency (RF) LNAs at nanometer range is the thermal noise generated in the short-channel MOSFETs. The short-channel effects (SCEs), such as velocity saturation and channel-length modulation, are considered for the design of CMOS LNA. The evolutionary algorithm taken for this work is Moth-Flame Optimization (MFO) algorithm. MFO is utilized for the optimization of noise figure (NF) while satisfying all the other design performance parameters like gain, matching parameters at input/output, power dissipation, linearity, stability. Optimal values of the sizes of the transistors and other design parameters in designing the LNA circuit are also obtained from the MFO algorithm. The CMOS LNA circuit is designed by using MFO-based optimal design parameters in CADENCE software with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The designed LNA shows a gain of 15.28[Formula: see text]dB, NF of 0.376[Formula: see text]dB, the power dissipation of 936[Formula: see text][Formula: see text]W and IIP3 of [Formula: see text][Formula: see text]dBm at 2.4[Formula: see text]GHz. The designed LNA achieves better trade-off which results in an FOM of 42.3[Formula: see text]mW[Formula: see text] and may be useful in the receiver module of IEEE 802.15.4 for WLAN applications.

14

Liu, Lian-xi, Jun-chao Mu, Ning Ma, Wei Tu, Zhang-ming Zhu, and Yin-tang Yang. "An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process." Circuits, Systems, and Signal Processing 35, no. 2 (June 3, 2015): 421–41. http://dx.doi.org/10.1007/s00034-015-0092-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Nikseresht, Sasan, Daniel Fernández, Jordi Cosp-Vilella, Irina Selin-Lorenzo, and Jordi Madrenas. "CMOS Wireless Hybrid Transceiver Powered by Integrated Photodiodes for Ultra-Low-Power IoT Applications." Electronics 13, no. 1 (December 20, 2023): 28. http://dx.doi.org/10.3390/electronics13010028.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In this article, a communication platform for a self-powered integrated light energy harvester based on a wireless hybrid transceiver is proposed. It consists of an optical receiver and a reconfigurable radio frequency (RF) transmitter. The hybrid optical/RF communication approach improves load balancing, energy efficiency, security, and interference reduction. A light beam for communication in the downlink, coupled with a 1 MHz radio frequency signal for the uplink, offers a small area and ultra-low-power consumption design for Smart Dust/IoT applications. The optical receiver employs a new charge-pump-based technique for the automatic acquisition of a reference voltage, enabling compensation for comparator offset errors and variations in DC-level illumination. On the uplink side, the reconfigurable transmitter supports OOK/FSK/BPSK data modulation. Electronic components and the energy harvester, including integrated photodiodes, have been designed, fabricated, and experimentally tested in a 0.18 µm triple-well CMOS technology in a 1.5 × 1.3 mm2 chip area. Experiments show the correct system behavior for general and pseudo-random stream input data, with a minimum pulse width of 50 µs and a data transmission rate of 20 kb/s for the optical receiver and 1 MHz carrier frequency. The maximum measured power of the signal received from the transmitter is approximately −18.65 dBm when using a light-harvested power supply.

16

Aspemyr, L., and D. Linten. "An Ultra Low Voltage, Low Power, Fully Integrated VCO for GPS in 90 nm RF-CMOS." Analog Integrated Circuits and Signal Processing 46, no. 1 (December 14, 2005): 57–63. http://dx.doi.org/10.1007/s10470-005-4077-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Chen, Ethan, and Vanessa Chen. "Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications." Mathematics 8, no. 5 (May 20, 2020): 829. http://dx.doi.org/10.3390/math8050829.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.

18

Al-Shidaifat, AlaaDdin, Sandeep Kumar, Shubhro Chakrabartty, and Hanjung Song. "A Conceptual Investigation at the Interface between Wireless Power Devices and CMOS Neuron IC for Retinal Image Acquisition." Applied Sciences 10, no. 18 (September 4, 2020): 6154. http://dx.doi.org/10.3390/app10186154.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In this paper, a conceptual investigation of the interface between wireless power devices and a retina complementary metal oxide semiconductor (CMOS) neuron integrated circuit (IC) have been presented. The proposed investigation consists of three designs: design-I, design-II, and design-III. Design-I involves a slotted loop monopole antenna as per American National Standards Institute (ANSI) guidelines, which achieve an ultra-wide band ranging from 3.1 GHz to 10.6 GHz. The biocompatible antenna is made on silicon-nitride substrate using on-wafer packaging technology and it is used as a receiver device. The performance of antenna provides a wideband, sufficient power to receive, and low losses due to the avoidance of printed circuit board (PCB) fabrication. A CMOS based multi-stack power harvesting circuit achieves the output power ranging from 4 mW to 2.7 W and corresponds from the selected Radio Frequency (RF) bands of loop antenna is exhibited in design-II. The power efficiency of 40% to 82%, with respect to output powers of 4 mW to 2.7 W, is achieved. Design-III includes a CMOS based retina neuron circuit that employs a dynamic feedback technique and support to achieve the number of read-out spikes. At the end of the interface between wireless power devices and a CMOS retina neuron IC, 50 mV read-out spikes are achieved, with varying light intensity, from 0 mW/cm2 to 2 mW/cm2. The proposed design-II and design-III are implemented and fabricated using commercial CMOS 0.065 µm, Samsung process. The antenna and RF power harvesting IC could be placed on a contact lens platform while retina neuron IC can be implanted after ganglions cells inside the eye. The antenna and harvesting IC are physically connected to the retina circuit in the form of light. This conceptual investigation could support medical professionals in achieving an interfacing approach to restore the image visualization.

19

Moraes Junior, Tarcisio Oliveira, Raimundo Carlos Silvério Freire, and Cleonilson Protásio de Souza. "A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit." Journal of Integrated Circuits and Systems 13, no. 2 (October 4, 2018): 1–6. http://dx.doi.org/10.29292/jics.v13i2.35.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In MOSFET-transistor based rectifier circuits, leakage currents occur through both source-bulk and drain-bulk connections of their transistors causing some power dissipation decreasing their efficiency. Such a scenario is more worrying in ultra-low power circuits as those used in energy harvesting. As a solution, in this work it is proposed a control circuit of transistor bulk biasing that switches the bulk bias in an efficient way assuring adequate inversion of the source-bulk and drain-bulk junctions. The rectifier based on the proposed bulk biasing control circuit shows to be a high-efficiency one capable of reducing the leakage currents. To obtain experimental results, the circuit was fabricated in a 130 nm CMOS process and tested on a micromanipulator. The results were compared with other works where it is observed that the efficiency of our proposal reaches up to 72.5% or 5% higher that the best previous one.

20

Han, Peiqing, Zhaofeng Zhang, Yajun Xia, and Niansong Mei. "A 920-MHz Dual-Mode Receiver with Energy Harvesting for UHF RFID Tag and IoT." Electronics 9, no. 6 (June 24, 2020): 1042. http://dx.doi.org/10.3390/electronics9061042.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

A low-power dual-mode receiver is presented for ultra-high-frequency (UHF) radio frequency identification (RFID) systems. The reconfigurable architecture of the tag is proposed to be compatible with low-power and high-sensitivity operating modes. The read range of RFID system and the lifetime of the tag are increased by photovoltaic, thermoelectric and RF energy-harvesting topology. The receiver is implemented in a 0.18-μm standard CMOS process and occupies an active area of 0.65 mm × 0.7 mm. For low-power mode, the tag is powered by the rectifier and the sensitivity is −18 dBm. For high-sensitivity mode, the maximum PCE of the fully on-chip energy harvester is 46.5% with over 1-μW output power and the sensitivity is −40 dBm with 880 nW power consumption under the supply voltage of 0.8 V.

21

Rehman, Muhammad Riaz Ur, Imran Ali, Danial Khan, Muhammad Asif, Pervesh Kumar, Seong Jin Oh, Young Gun Pu, et al. "A Design of Adaptive Control and Communication Protocol for SWIPT System in 180 nm CMOS Process for Sensor Applications." Sensors 21, no. 3 (January 27, 2021): 848. http://dx.doi.org/10.3390/s21030848.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

This paper presents an adaptive control and communication protocol (ACCP) for the ultra-low power simultaneous wireless information and power transfer (SWIPT) system for sensor applications. The SWIPT system-related operations depend on harvested radio frequency (RF) energy from the ambient environment. The necessary power for SWIPT system operation is not always available and it depends on the available RF energy in the ambient environment, transmitted RF power from the SWIPT transmitter, and the distance from the transmitter and channel conditions. Thus, an efficient control and communication protocol is required which can control the SWIPT system for sensor applications which mainly consists of a transmitter and a receiver. Multiple data frame structures are used to optimize the exchange of bits for the communication and control of the SWIPT system. Both SWIPT transmitter and receiver are capable of using multiple modulation schemes which can be switched depending on the channel condition and the available RF energy in the ambient environment. This provides support for automatic switching between the time switching scheme and power splitting scheme for the distribution of received RF power in the SWIPT receiver. It also adjusts the digital clock frequency at the SWIPT receiver according to the harvested power level to optimize the power consumption. The SWIPT receiver controller with ACCP is implemented in 180 nm CMOS technology. The RF frequency of the SWIPT operation is 5.8 GHz. Digital clock frequency at the SWIPT receiver can be adjusted between 32 kHz and 2 MHz which provides data rates from 8 to 500 kbps, respectively. The power consumption and area utilization are 12.3 µW and 0.81 mm².

22

Kim, Jihoon. "A Wideband and Low-Power Distributed Cascode Mixer Using Inductive Feedback." Sensors 22, no. 22 (November 21, 2022): 9022. http://dx.doi.org/10.3390/s22229022.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

A wideband and low-power distributed cascode mixer is implemented for future mobile communications. The distributed design inspired by the distributed amplifier (DA) enables a mixer to operate in a wide band. In addition, the cascode structure and inductive positive feedback design allow high conversion gain with low-power consumption. The proposed mixer is fabricated using a 130 nm commercial complementary metal-oxide-semiconductor (CMOS) process. It consists of three cascode gain cells and operates with a drain voltage of 1.5 V and a gate voltage of 0.5 to 0.7 V. The fabricated mixer exhibits conversion gain of −2.9 to 3.1 dB at the radio frequencies (RFs) of 4 to 30 GHz and −1.9 to 0.4 dB at RFs of 54 to 66 GHz under the conditions of 8 to 10 dBm of local oscillator (LO) power and 650 MHz of intermediate frequency (IF). The LO-RF isolation is more than 15 dB over the entire measurement band (0.2 to 67 GHz) as the RF and LO signals are applied to different transistors owing to the cascode structure. The total power consumption is only within 12 mW, and the chip size is 0.056 mm2, making it possible to implement a compact mixer. The proposed mixer shows broadband characteristics covering from ultra-wideband (UWB) and the 28 GHz fifth-generation (5G) communication band to the 60 GHz wireless gigabit alliance (WiGig) band.

23

Lysenko, Igor, Alexey Tkachenko, Elena Sherova, and Alexander Nikitin. "Analytical Approach in the Development of RF MEMS Switches." Electronics 7, no. 12 (December 10, 2018): 415. http://dx.doi.org/10.3390/electronics7120415.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

Currently, the technology of microelectromechanical systems is widely used in the development of high-frequency and ultrahigh-frequency devices. The most important requirements for modern and advanced devices of the ultra-high-frequency range are the reduction of weight and size characteristics, power consumption with an increase in their functionality, operating frequency and level of integration. Radio frequency microelectromechanical switches are developed using the technology of the manufacture of CMOS-integrated circuits. Integrated radio frequency control circuits require low control voltages, the high ratio of losses to the isolation in the open and closed condition, high performance and reliability. This review is devoted to the analytical approach based on the knowledge of materials, basic performance indices and mechanisms of failure, which can be used in the development of radio-frequency microelectromechanical switches.

24

Rui Xu and Cam Nguyen. "An Ultra-Wideband Low Power-Consumption Low Noise-Figure High-Gain RF Power-Efficient DC–3.5-GHz CMOS Integrated Sampling Mixer Subsystem." IEEE Transactions on Microwave Theory and Techniques 56, no. 5 (May 2008): 1069–75. http://dx.doi.org/10.1109/tmtt.2008.920163.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Khaleel, Farooq A., and Mohammed Nadhim Abbas. "Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology." IEICE Electronics Express 14, no. 5 (2017): 20170066. http://dx.doi.org/10.1587/elex.14.20170066.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Seethur, Rashmi, Siva Yellampalli, and Shreedhar H. K. "Design of Common Gate Current-Reuse Noise Cancellation UWB Low Noise Amplifier in 90nm CMOS." International Journal of Electronics, Communications, and Measurement Engineering 11, no. 1 (January 1, 2022): 1–14. http://dx.doi.org/10.4018/ijecme.312257.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In this paper, an ultra-wide band (UWB) low noise amplifier (LNA) is implemented by using 90nm RF CMOS technology. The designed LNA achieves high flat band gain (S21) and low noise figure (NF) in the frequency of interest. The proposed LNA operates in the frequency range of 3GHz to 8GHz. In this work, wide band matching is achieved by designing common gate configuration at the input stage. The current reuse and noise cancellation techniques are introduced to improve flat band gain and minimize both noise figure and power consumption. The noise figure is improved by cancelling dominant noise sources with additional hardware. The proposed LNA attains flat band gain of 26.5dB and input matching less than -12dB for entire UWB band. This work achieves noise figure of 2.1dB to 2.59dB in frequency band of interest. Additionally, power consumption of the circuit is 20mW at 1.8V supply voltage.

27

Zhang, Zhihao, Jing Li, Lin Peng, and Bo Sun. "Multi-Band Power Amplifier Module with Back-Off Efficiency Improvement using Ultra-Compact 3D Vertical Stack Multi-Chip Package for Cellular Handsets." Micromachines 13, no. 11 (November 15, 2022): 1976. http://dx.doi.org/10.3390/mi13111976.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

A highly integrated multi-mode multi-band (MMMB) power amplifier module (PAM) using hybrid bulk complementary metal oxide semiconductor (CMOS), gallium arsenide (GaAs) heterojunction bipolar transistor (HBT), and silicon-on-insulator (SOI) technologies for low band (LB, 824–915 MHz) and high band (HB, 1710–1980 MHz) is proposed. The hybrid MMMB PAM integrates a bulk CMOS controller die, a GaAs HBT power amplifier (PA) die and a SOI switch die on a six-layer laminate. To simultaneously obtain both highly efficient and highly linear characteristics over a wide range of input power levels, a parallel dual-chain PA strategy has been adopted to provide vary bias current and gain for low-power mode (LPM) and high-power mode (HPM) operation. Additionally, a broadband two-section low-pass output matching network design based on the suppression of high-order harmonics is proposed for enhanced efficiency and linearity. In order to achieve further miniaturization, a three-dimensional (3D) die stack multi-chip module (MCM) packaging structure, where the presented CMOS controller die is stacked vertically on the GaAs HBT PA die, is implemented. The measurement results show that the fabricated MMMB PAM achieves 26.1–27 dB of power gains and 38–38.4% of PAEs at an output power (Pout) of 28 dBm in the HPM, and 20.4–20.9 dB of power gains and 12.4–13.8% of PAEs at Pout of 17 dBm in the LPM over LB. For HB, power gains of 24.3–26.7 dB while maintaining PAEs of 38.2–39.9% at Pout of 28 dBm, and power gains of 15.9–17.5 dB while maintaining PAEs of 12.3–12.8% at Pout of 17 dBm are realized in the HPM and LPM, respectively. The fabricated PAM covering five frequency bands and operating at two power modes only occupies a 5 × 3.5 mm2 area. To the best of the authors’ knowledge, this work is the first demonstration of a MMMB PAM adopting an ultra-compact 3D vertical stack MCM package with favorable RF performance.

28

Lee, Yongho, Shinil Chang, Jungah Kim, and Hyunchol Shin. "A CMOS RF Receiver with Improved Resilience to OFDM-Induced Second-Order Intermodulation Distortion for MedRadio Biomedical Devices and Sensors." Sensors 21, no. 16 (August 5, 2021): 5303. http://dx.doi.org/10.3390/s21165303.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

A MedRadio RF receiver integrated circuit for implanted and wearable biomedical devices must be resilient to the out-of-band (OOB) orthogonal frequency division modulation (OFDM) blocker. As the OFDM is widely adopted for various broadcasting and communication systems in the ultra-high frequency (UHF) band, the selectivity performance of the MedRadio RF receiver can severely deteriorate by the second-order intermodulation (IM2) distortion induced by the OOB OFDM blocker. An analytical investigation shows how the OFDM-induced IM2 distortion power can be translated to an equivalent two-tone-induced IM2 distortion power. It makes the OFDM-induced IM2 analysis and characterization process for a MedRadio RF receiver much simpler and more straightforward. A MedRadio RF receiver integrated circuit with a significantly improved resilience to the OOB IM2 distortion is designed in 65 nm complementary metal-oxide-semiconductor (CMOS). The designed RF receiver is based on low-IF architecture, comprising a low-noise amplifier, single-to-differential transconductance stage, quadrature passive mixer, trans-impedance amplifier (TIA), image-rejecting complex bandpass filter, and fractional phase-locked loop synthesizer. We describe design techniques for the IM2 calibration through the gate bias tuning at the mixer, and the dc offset calibration that overcomes the conflict with the preceding IM2 calibration through the body bias tuning at the TIA. Measured results show that the OOB carrier-to-interference ratio (CIR) performance is significantly improved by 4–11 dB through the proposed IM2 calibration. The measured maximum tolerable CIR is found to be between −40.2 and −71.2 dBc for the two-tone blocker condition and between −70 and −77 dBc for the single-tone blocker condition. The analytical and experimental results of this work will be essential to improve the selectivity performance of a MedRadio RF receiver against the OOB OFDM-blocker-induced IM2 distortion and, thus, improve the robustness of the biomedical devices in harsh wireless environments in the MedRadio and UHF bands.

29

Siddiqui, Muhammad Faisal, Mukesh Kumar Maheshwari, Muhammad Raza, and Aurangzeb Rashid Masud. "Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology." Journal of Low Power Electronics and Applications 13, no. 4 (October 7, 2023): 54. http://dx.doi.org/10.3390/jlpea13040054.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

30

Tu, Cheng, Zhao-Qiang Chu, Benjamin Spetzler, Patrick Hayes, Cun-Zheng Dong, Xian-Feng Liang, Huai-Hao Chen, et al. "Mechanical-Resonance-Enhanced Thin-Film Magnetoelectric Heterostructures for Magnetometers, Mechanical Antennas, Tunable RF Inductors, and Filters." Materials 12, no. 14 (July 13, 2019): 2259. http://dx.doi.org/10.3390/ma12142259.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

The strong strain-mediated magnetoelectric (ME) coupling found in thin-film ME heterostructures has attracted an ever-increasing interest and enables realization of a great number of integrated multiferroic devices, such as magnetometers, mechanical antennas, RF tunable inductors and filters. This paper first reviews the thin-film characterization techniques for both piezoelectric and magnetostrictive thin films, which are crucial in determining the strength of the ME coupling. After that, the most recent progress on various integrated multiferroic devices based on thin-film ME heterostructures are presented. In particular, rapid development of thin-film ME magnetometers has been seen over the past few years. These ultra-sensitive magnetometers exhibit extremely low limit of detection (sub-pT/Hz1/2) for low-frequency AC magnetic fields, making them potential candidates for applications of medical diagnostics. Other devices reviewed in this paper include acoustically actuated nanomechanical ME antennas with miniaturized size by 1–2 orders compared to the conventional antenna; integrated RF tunable inductors with a wide operation frequency range; integrated RF tunable bandpass filter with dual H- and E-field tunability. All these integrated multiferroic devices are compact, lightweight, power-efficient, and potentially integrable with current complementary metal oxide semiconductor (CMOS) technology, showing great promise for applications in future biomedical, wireless communication, and reconfigurable electronic systems.

31

Trojman, Lionel, Eduardo Holguin, Marco Villegas, Luis-Miguel Procel, and Ramiro Taco. "From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits." Electronics 11, no. 4 (February 10, 2022): 525. http://dx.doi.org/10.3390/electronics11040525.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.

32

Pekarik, Jack, Vibhor Jain, Crystal Kenney, Judson Holt, Shweta Khokale, Sudesh Saroop, Jeffrey Johnson, et al. "Challenges for Sige Bicmos in Advanced-Node SOI." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1196. http://dx.doi.org/10.1149/ma2022-02321196mtgabs.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integrated along with a high-density CMOS provide such an all-silicon monolithic solution. The US government is fostering the expansion of “unique and differentiated domestic manufacturing” with funding through DARPA’s Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) [1] program to enable disruptive RF mixed-mode technologies by developing high performance RF analog integrated with advanced digital CMOS. Through the T-MUSIC program, DARPA seeks to: 1) advance RF and mixed-mode devices to support ultra-wideband RF frontends from HF to 100 GHz; 2) integrate those devices with high density digital CMOS electronics at the wafer scale to enable embedded digital intelligence; 3) develop and explore ultra-high resolution broadband mixed-mode circuit building blocks for DoD-relevant applications; 4) explore innovative device topologies and materials to form THz devices in an advanced digital CMOS fabrication platform; and 5) establish a domestic ecosystem that facilitates enduring DoD access to differentiated capabilities for high performance RF mixed-mode SoCs. Under T-MUSIC, GlobalFoundries is demonstrating BiCMOS on 45nm PDSOI, which is the focus of this paper, and 22nm FDSOI CMOS with goals of increasing HBT performance of fT/fMAX from 350/500 GHz to 400/600 GHz and 600/700 GHz. HBTs with fT/fMAX of 380/550GHz GHz have been demonstrated building upon previously published results [2]. This paper will touch on some of the challenges that were encountered in achieving that result and discuss those anticipated in future work. Achieving these results required scaling transistor dimensions. Vertical scaling of the emitter, base and collector layers, with higher doping concentrations, reduces transit time but results in higher current densities and higher electric fields. Lateral scaling of the transistor structure reduces parasitic capacitance and resistance but concentrate the power dissipation in a smaller area. The thermal conductivity of silicon is 148W/m-K whereas that of silicon dioxide is ~1.4W/m-K. Even a thin layer of oxide will significantly increase the self-heating of the HBT. Therefore, we replace the SOI with coplanar epitaxy in regions where the HBTs are formed. The vertical scaling of the HBT requires limiting the thermal cycles that the HBT will experience during processing and suggests forming the HBT as late as possible in the CMOS process. However, the thermal cycles associate with the epitaxy and film depositions to form the HBT impact the CMOS transistors which suggests forming the HBT early in the process. We found a point in the process that offers the best compromise minimizing the impact to the doped-channel PDSOI CMOS while achieving the HBT performance goals. Work is just beginning on integration tradeoffs for FDSOI with metal gate and high-K dielectrics. Advanced-node CMOS processes can form components having smaller dimensions which offers advantages for lateral scaling but also presents challenges for forming the HBT. The contact height in 45nm is significantly less than the height of the HBT structure used in GF’s 9HP process. We changed the formation of the emitter and base so that the emitter and base contacts are almost coplanar in contrast to 9HP where the emitter was almost twice the height of the base. This problem is being further exasperated as we migrate to 22nm. The shrinking of BEOL wiring dimensions, along with the ability of the HBT to drive high currents, presents challenges in designing within limits imposed by electromigration. The use of wider wires is constrained by metal density rules. The use of stacked metal levels and redundant vias impact the parasitic capacitances and resistances of the interconnects. The paper and presentation will review these, and other challenges encountered in achieving BiCMOS integration of SiGe HBTs with fT/fMAX of 380/550GHz GHz [see figure] on a 45nm PDSOI CMOS and touch future work. This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) and is Approved for Public Release, Distribution Unlimited. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. [1] https://www.darpa.mil/attachments/T-MUSIC_Proposers%20Day_Presentations_Combined.pdf [2] J. Pekarik et al., 2021 IEEE BCICTS, 2021, pp. 1-4, Figure 1

33

Lee, Yao-Jen, Shu-Wei Chang, Wen-Hsi Lee, and Yeong-Her Wang. "(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration." ECS Meeting Abstracts MA2022-02, no. 35 (October 9, 2022): 1289. http://dx.doi.org/10.1149/ma2022-02351289mtgabs.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit. [1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

34

Lamy, Yann, Florian Dupont, Guillaume Rodriguez, Messaoud Bedjaoui, Pierre Perreau, Marie Bousquet, Alexandre Reinhardt, and Sami Oukassi. "(Invited) Lithium-Based Components Integrated on Silicon: Disruptive, Promising and Credible Solutions for 5G & Beyond." ECS Meeting Abstracts MA2022-01, no. 29 (July 7, 2022): 1286. http://dx.doi.org/10.1149/ma2022-01291286mtgabs.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

Following a trend similar to Moore’s low which prevailed for decades for active circuits, RF integrated passive components have reinvented themselves over the years in order to sustain continuous performance and size requirements. Their roadmap is still unrolling, thanks to a wide variety of new materials integration: high-k dielectrics for capacitors[1] ,[2] , magnetic material for inductors [3], aluminium nitride[4] (now scandium doped) for RF filters, or more recently phase-change materials for RF switches[5]. In the last few years, RF integrated passives built upon Lithium-based materials have attracted strong attention because of their state-of-the-art performances and their direct integration on silicon wafers. Lithium-based piezoelectric materials are used since 40 years by the SAW filters industry, which processes LiTaO3 (LTO) or LiNbO3 (LNO) bulk wafers in dedicated fabs. Recently, however, layered SAW devices exploiting thin films of these materials directly on a silicon wafer have exhibited dramatically improved performances. These devices leverage the latest developments in single crystal Li-based layer transfer, or in deposition techniques (PVD, ALD[6], Pulse-Laser-Deposition, ...) of epitaxial, textured, or amorphous Li-based thin films, all of which achievable in industrial grade semiconductor equipments. In this presentation, we will give an overview of the potential of integrating lithium-based materials on silicon through different examples of promising RF components for 5G. First, we will show how the availability of Li-based Piezoelectric-on-Insulator (POI) wafers[7] is a game changer for 5G filtering. We will present very promising perspectives regarding the development of LNO-based Bulk Acoustics Wave filters (BAW)[8] ,[9],[10] which aim at extending the application space of POI SAW filters towards the upper 5G bands and even Wi-Fi 6E [5-7 GHz] . Different examples of Li-based materials integrations will be given3,4,5,[11] . Secondly, we will discuss the potential of a new type of Li-based hybrid micro supercapacitors integrated on silicon. LiPON thin films offer a unique combination of dual properties, being both a dielectric and an electrolyte[12]. Their integration on silicon is not only bringing potentially ultra-high capacitance densities, but also local on-chip energy storage for 5G components, opening a new paradigm in use of the device in a system[13] ,[14] . After that, we will open the horizon of the potential of Li-based materials integration towards other types of RF devices, like RF switchs, and elaborate on their synergy with Li-transistors for neuromorphic applications[15] and with more conventional lithium microbatteries integrated on silicon[16]. Finally, the integration of Lithium in a silicon industrial environment and the remaining challenges will be discussed. The similarities and discrepancies of the different Li-based processes will be analyzed as well as the compatibility with a silicon CMOS and/or microsystem fab, and the potential for wafers size scaling. Risks like sensitivity to humidity and potential Li contamination will be outlined with some relevant preventive protocols in order to make the Lithium integration on silicon a real and credible disruptive solution regarding 5G challenges. [1] F. Roozeboom, et al. ECS 2007 [2] M. Bousquet et al., ECAPD 2014 [3] J. P. Michel et al., IEEE Trans. Magnetics 55, n°7, pp. 1-7 (2019) » [4] A. Reinhardt et al., IFCS 2011 [5] A. Leon et al., IEEE Trans. Microwave Theory and Techniques, vol. 68, n°1, pp. 60-73 (2020)” [6] M. Bedjaoui et al. ECS Meeting (October 10-14, 2021). [7] E. Butaud et al. IEDM 2020 [8] M. Bousquet et al., Proc. IEEE International Ultrasonics Symposium 2019. [9] M. Bousquet et al., Proc. IEEE International Ultrasonics Symposium 2020. [10] A. Reinhardt et al., Proc. Joint Conference of EFTF & IFCS 2021 [11] L. Sauze et al, Thin solid films, 726, may 2021 [12] L. Le Van-Jodin et al, Solid State ionic, 2013 [13] V. Sallaz et al, Journal of Power Source, 2020 [14] V. Sallaz et al. submitted to ECS 2021 [15] N-A Ngyuen et al,” submitted to ECS 2021 [16] S. Oukassi et al, IEDM 2019

35

Kunert, Bernardette, Yves Mols, Reynald Alcotte, Peter Swekis, Sachin Yadav, Abhitosh Vais, Annie Kumar, et al. "(Invited) Integration of InP Heterojunction Bipolar Transistors on Silicon Substrates for 6G Networks." ECS Meeting Abstracts MA2023-01, no. 33 (August 28, 2023): 1852. http://dx.doi.org/10.1149/ma2023-01331852mtgabs.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

The fast expansion of the global datasphere creates a huge demand on the future wireless communication technologies. Although 5G, the 5th generation of the cellular network technology, is still being rolled out, the potential of 6G is already intensively explored. The vision of 6G implies not only massive connectivity and higher data rate (up to 100 Gb/s and more) in ultra-reliable low-latency communication, but machine-to-machine interaction will dominate over those involving humans. AI (artificial intelligence) and machine learning will be omnipresent. 6G network will address a frequency spectrum beyond 100 GHz, which provides wider bandwidths and, therefore, potentially simpler modulation schemes and eventually lower power consumption. However, a clear disadvantage of these mm-waves or sub-THz frequencies are the atmospheric absorption and blockage effect by physical obstacles or rain. These challenges must be tackled by a sufficiently high transceiver device density per area together with advanced beam steering and AI empowered networks. The power amplifier (PA) is one of the most critical components of the RF front-end module. Here, InP based heterojunction bipolar transistors (HBT) clearly outperform PAs based on CMOS or SiGe BiCMOS concerning saturated output power, energy efficiency and breakdown voltage. However, the limiting downside of InP HBTs is the missing cost-efficient and scalable fabrication, which hampers its adoption in high-volume 6G applications. In this paper we review various InP HBT fabrication concepts with the aim of lowering the production costs and maintaining high device performance. The best HBT device performance is demonstrated for the lattice-matched deposition on native small-diameter (≤ 150 mm) InP substrates due to perfect III-V crystal quality. Although device fabrication on these wafers cannot profit from the advanced tool park available in 200/300 mm fabs, the main drawbacks are the high cost and brittleness of InP substrates. Realizing InP HBTs on Si substrates allows to benefit from their robustness, low cost, and the access to a mature device fabrication on large-diameter wafers. In wafer reconstitution, numerous diced InP wafer tiles, which already contain the grown HBT layer stack, are bonded to a Si carrier to populate the wafer surface. After planarization, the reconstructed Si wafer can be further fabricated in a CMOS compatible 200/300 mm fab. In transfer printing a comparable approach is followed while only the active device stack is transferred to the Si carrier. Transferring only a thin InP layer to the Si carrier, which serves as a starting surface for the HBT deposition, leads to a so-called engineered substrate. Compared to the previous transfer methods, the III-V device deposition is carried out after bonding. The key advantage of all these heterogenous integration concepts is the access to a CMOS compatible and scalable device fabrication while maintaining the high III-V crystal quality. Nevertheless, the HBT production costs can only be significantly reduced with a certain re-usability of the InP substrates. The monolithic deposition directly on Si substrates would be the most cost-efficient integration approach. Unfortunately, the mismatch in lattice constant and thermal expansion coefficient between Si and III-V materials leads to the formation of relaxation defects, which degrade the HBT device performance. The growth of thick strain relaxation buffers allows to reduce the defect density in the device layers but bears new challenges such as wafer warpage or III-V crack formation. Nano-ridge engineering (NRE) is based on selective area growth (SAG) applying trench-patterned Si wafers. The III-V deposition starts inside very narrow trenches to achieve efficient aspect ratio trapping (ART) of misfit defects. After the trench is filled with III-V material, the growth is continued to engineer a broad and pristine nano-ridge (NR) which holds the device stack. A second oxide pattern prevents sidewall deposition around the NRs during the deposition of the HBT heterolayers. In the first part of this paper, pros, and cons of the most common InP HBT integration scenarios as summarized in figure will be compared in detail. Among all concepts, NRE holds the potential of being the most cost-efficient integration approach due to SAG in line with very limited III-V material deposition. However, the key open question is what NR crystal quality, and hence, device performance can be realized. This question will be addressed in the second part of the paper, reporting about the latest developments at imec. Figure 1

36

Steyaert, M. S. J., B. De Muer, P. Leroux, M. Borremans, and K. Mertens. "Low-voltage low-power CMOS-RF transceiver design." IEEE Transactions on Microwave Theory and Techniques 50, no. 1 (2002): 281–87. http://dx.doi.org/10.1109/22.981281.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Salama, Mohammed K., and Ahmed M. Soliman. "Low-voltage low-power CMOS RF low noise amplifier." AEU - International Journal of Electronics and Communications 63, no. 6 (June 2009): 478–82. http://dx.doi.org/10.1016/j.aeue.2008.03.007.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

Yousef, K., H. Jia, R. Pokharel, A. Allam, M. Ragab, H. Kanaya, and K. Yoshida. "CMOS Ultra-Wideband Low Noise Amplifier Design." International Journal of Microwave Science and Technology 2013 (April 30, 2013): 1–6. http://dx.doi.org/10.1155/2013/328406.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

39

Shirazi, Amir Hossein Masnadi, and Shahriar Mirabbasi. "An ultra-low-voltage ultra-low-power CMOS active mixer." Analog Integrated Circuits and Signal Processing 77, no. 3 (October 8, 2013): 513–28. http://dx.doi.org/10.1007/s10470-013-0163-2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Salama, Mohammed K., and Ahmed M. Soliman. "Low-Voltage Low-Power CMOS RF Four-Quadrant Multiplier." AEU - International Journal of Electronics and Communications 57, no. 1 (January 2003): 74–78. http://dx.doi.org/10.1078/1434-8411-54100143.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Khan, Shahid. "Design of Ultra Low Power CMOS Inverter." IJIREEICE 5, no. 3 (March 15, 2017): 55–57. http://dx.doi.org/10.17148/ijireeice.2017.5312.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Yang, Sang-hyeok, Kyoung-bum Kim, Eung-ju Kim, Kwang-hyun Baek, and Suki Kim. "An ultra low power CMOS motion detector." IEEE Transactions on Consumer Electronics 55, no. 4 (November 2009): 2425–30. http://dx.doi.org/10.1109/tce.2009.5373819.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

FERREIRA, L. H. C., T. C. PIMENTA, and R. L. MORENO. "An Ultra Low-Voltage Ultra Low-Power CMOS Threshold Voltage Reference." IEICE Transactions on Electronics E90-C, no. 10 (October 1, 2007): 2044–50. http://dx.doi.org/10.1093/ietele/e90-c.10.2044.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

NASEH, SASAN, and M. JAMAL DEEN. "RF CMOS RELIABILITY." International Journal of High Speed Electronics and Systems 11, no. 04 (December 2001): 1249–95. http://dx.doi.org/10.1142/s0129156401001088.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Abstract:

In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

45

Thanachayanont, A. "Low-voltage low-power high-Q CMOS RF bandpass filter." Electronics Letters 38, no. 13 (2002): 615. http://dx.doi.org/10.1049/el:20020440.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Sreenivasulu, Patikineti, Srinivasa Rao, and Vinaya Babu. "Ultra-Low Power Designing for CMOS Sequential Circuits." International Journal of Communications, Network and System Sciences 08, no. 05 (2015): 146–53. http://dx.doi.org/10.4236/ijcns.2015.85016.

Full text

APA, Harvard, Vancouver, ISO, and other styles

47

Das, Jayita, Syed M. Alam, and Sanjukta Bhanja. "Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 9 (September 2012): 2008–16. http://dx.doi.org/10.1109/tcsi.2012.2185311.

Full text

APA, Harvard, Vancouver, ISO, and other styles

48

Zhou, Sheng-hua, Wancheng Zhang, and Nan-Jian Wu. "An ultra-low power CMOS random number generator." Solid-State Electronics 52, no. 2 (February 2008): 233–38. http://dx.doi.org/10.1016/j.sse.2007.08.008.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Zhou, Yijun, and Michael Yan-Wah Chia. "A Low-Power Ultra-Wideband CMOS True RMS Power Detector." IEEE Transactions on Microwave Theory and Techniques 56, no. 5 (May 2008): 1052–58. http://dx.doi.org/10.1109/tmtt.2008.921299.

Full text

APA, Harvard, Vancouver, ISO, and other styles

50

Wong, Sew-Kin, Fabian Kung Wai Lee, Siti Maisurah, and Mohd Nizam Bin Osman. "A WIMEDIA COMPLIANT CMOS RF POWER AMPLIFIER FOR ULTRA-WIDEBAND (UWB) TRANSMITTER." Progress In Electromagnetics Research 112 (2011): 329–47. http://dx.doi.org/10.2528/pier10122303.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Ultra Low Power CMOS RF'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles