Dissertations / Theses on the topic 'Ultra Low Power CMOS RF'
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Kraimia, Hassen. "Ultra-Low Power RFIC Solutions for Wireless Sensor Networks." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2013. http://tel.archives-ouvertes.fr/tel-01066815.
Abstract:
Since their emergence, Wireless Sensor Networks (WSN) have been growing continually becoming a key player in many applications such as military tracking, remote monitoring, bio-sensing and home automation. These networks are based on IEEE 802.15.4 standard which is dedicated to low rate wireless personal area networks (LR-WPANs) in the unlicensed radio band (868MHz/915MHz/2.4GHz). Low power consumption, low cost of implementation and high level of integration are the main challenges of these systems. As radio frequency transceiver is one of the most power hungry block in wireless sensor node, power consumption of radio frequency front-end (RFFE) must be reduced. To deal with, several approaches are possible, either at circuit level by investigating operating modes of transistors and merging functionalities or at system level by searching novel demodulation architecture. This thesis explores the specific requirements and challenges for the design of ultra-low power radio frequency integrated circuits (RFICs), leading to the design of a compact demodulator implemented in 65 nm CMOS technology and compatible with all modulation schemes.
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Lin, Kuan-Yu. "The design of low power ultra-wideband RF CMOS wireless systems for sensor networks." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22014.
Abstract:
The wireless market is continuing its rapid development towards higher bandwidth, lower power, and lower cost. Recently, wireless sensor networks (WSN) have emerged and captivated the interest of many researchers and the industry. A promising wireless communication technology for wireless sensor networks is the ultra-wideband (UWB) technology. The architecture and circuit designs of UWB wireless communication systems can be very different from traditional narrowband systems. This thesis focuses on the design of UWB radio frequency (RF) front-end transceivers, power scavenging and power management systems for low power wireless sensor networks. A sub-miliWatt ultra-wideband CMOS common gate (CG) low-noise amplifier (LNA) is demonstrated in this work. To achieve good gain, wideband input impedance matching, and low power consumption, the proposed LNA exploits the combination of RF transformers, current reuse, and back-gate coupling techniques to boost the transconductance of the gain transistors. To realize a compact low cost design with no discrete components, the LNA utilizes special high quality bonding wire transformers on an IC package. The LNA prototype, fabricated in a 0.18 µm CMOS process, consumes 698.5 µW from a 1.5 V supply. The design of two low power CMOS ultra-wideband (UWB) pulse-based transmitters is also reported in this thesis. The goal is to propose simple, low power, and tunable topologies for full-band and sub-band UWB transmitters. The first transmitter utilizes a gated ring oscillator, an NMOS switch, and a passive pulse shaping filter to generate a 3.1 - 10.6 GHz full-band UWB signal. The second transmitter multiplies a carrier and a triangular signal to up-convert and to generate a low side-band UWB signal for sub-band applications. We propose the use of two NMOS switches in series to perform this multiplication while consuming minimum power. Control voltages incorporated in both designs are used to adjust the shapes of the pulses to compLe marché sans fil continu à développer vers une bande passante plus large, une réduction de la consommation d'énergie électrique et du coût. La technologie ultra large bande (UWB) est prometteuse dans le domaine de la communication des capteurs des réseaux sans fil. Toutefois, il faut noter que l'architecture et les conceptions de circuit du système de communication sans fil d'UWB peuvent être très différentes des systèmes à bande étroite traditionnels. Cette thèse traite de la conception UWB radio fréquence (RF) des émetteurs récepteurs d'entrée et du système de récupération et de gestion d'énergie pour les capteurs des réseaux sans fil à faible consommation d'énergie électrique. Un CMOS amplificateur à faible bruit (AFB), à large bande et à faible consommation d'énergie électrique est démontré. Pour obtenir une bonne amplification, l'impédance d'entrée du circuit désirée et minimiser la consommation d'énergie électricité, l'AFB propose l'exploitation des transformateurs RF, de la réutilisation du courant électrique, et des techniques de couplage pour amplifier la transconductance des transistors. Pour réaliser une conception compacte à coût réduit sans l'utilisation des composants externe, l'AFB utilise des transformateurs spéciaux composés de fil de liaison de haute qualité sur un paquet d'un circuit intégré. Le prototype AFB fabriqué dans une technologie CMOS de 0.18 µm consomme 698.5 µW avec une tension de 1.5 V. La conception de deux émetteurs CMOS d'impulsion à large bande et à faible consommation d'énergie électrique est décrite. Le but est de proposer une solution simple pour réduire la consommation d'énergie électricité et des topologies réglables des émetteurs à plein-bande et à sous-bande pour la technologie UWB. Le premier émetteur utilise un oscillateur, un commutateur NMOS, et un filtre passif pour produire un signal UWB de 3.1-10.6 GHz à plein-bande. Le deuxième émetteur mu
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Gebreyohannes, Fikre Tsigabu. "Design of Ultra-Low Power Wake-Up Receiver in 130nm CMOS Technology." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78797.
Abstract:
Wireless Sensor Networks have found diverse applications from health to agriculture and industry. They have a potential to profound social changes, however, there are also some challenges that have to be addressed. One of the problems is the limited power source available to energize a sensor node. Longevity of a node is tied to its low power design. One of the areas where great power savings could be made is in nodal communication. Different schemes have been proposed targeting low power communication and short network latency. One of them is the introduction of ultra-low power wake-up receiver for monitoring the channel. Although it is a recent proposal, there has been many works published. In this thesis work, the focus is study and comparison of architectures for a wake-up receiver. As part of this study, an envelope detector based wake-up receiver is designed in 130nm CMOS Technology. It has been implemented in schematic and layout levels. It operates in the 2.4GHz ISM band and consumes a power consumption of 69µA at 1.2V supply voltage. A sensitivity of -52dBm is simulated while receiving 100kb/s OOK modulated wake-up signals.This is a master's thesis work by a communication electronics student in a German company called IMST GmbH.
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Chandernagor, Lucie. "Etude, conception et réalisation d’un récepteur d’activation RF ultra basse consommation pour l’internet des objets." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0126/document.
Abstract:
Grâce au confort d’utilisation qu’elles procurent, les technologies sans fil se retrouvent aujourd’hui dans un vaste panel d’applications. Ainsi le nombre d’éléments de transmission/réception radio se multiplie. Aujourd’hui pour réduire les consommations des éléments radio, il faut les rendre davantage efficaces notamment pour la partie réception. En effet, pour les communications asynchrones, les récepteurs consomment inutilement de l’énergie à attendre qu’une transmission soit faite. Dans l’objectif de réduire ce gaspillage d’énergie, des nouveaux standards ont vu le jour tel que le Zigbee et le Bluetooth Low Energy. Les performances en consommation procurées par ces deux standards résident sur leur fonction périodique à très faible rapport cyclique. Une nouvelle solution émergente pour réduire drastiquement la consommation des récepteurs en les rendant plus efficaces est l’utilisation de récepteur d’activation. Les récepteurs d’activation ou récepteur de réveil sont des récepteurs simples ce qui leur permet d’atteindre une ultra basse consommation uniquement en charge de guetter l’arrivée d’une trame et de réveiller le récepteur principal, placé en veille au préalable, pour traitement de cette dernière. Le récepteur d’activation proposé ici a été réalisé dans la technologie CMOS 160 nm de NXP. Il offre une sensibilité de -54 dBm, pour une consommation moyenne de 35 μA, prodiguant une portée de 70m à 433,92 MHz pour une puissance de 10 dBm émis. Ce récepteur ASK se distingue des autres récepteurs d’activation par le système de calibration breveté avec ajustement automatique la tension de référence requise pour la démodulation. Ce système rend le circuit robuste au problème d’offset DC et ne consomme aucun courant lorsque le circuit est en écoute. Le récepteur d’activation reconnaît un code de Manchester de 24 bits à 25 kbps, programmable grâce à une interface SPIWireless technologies are now widespread due to the easiness of use they provide. Consequently, the number of radio devices increases. Despite of the efforts to reduce radio circuits power consumption as they are more and more numerous, now they must achieve ultra-low power consumption. Today, radio devices are made more efficient to reduce their power consumption especially for the receiving part. Indeed, for asynchronous communication, a lot of energy is wasted by the receiver waiting for a transmission. In order to avoid this waste, new standards have been created such as Zigbee and Bluetooth Low Energy. Due to periodic operation with ultra-low duty cycle, they provide ultra-low power consumption. Another solution to drastically reduce the power consumption has emerged, wake-up receiver. Wake-up receivers are based in simple architecture to provide ultra-low power consumption, they are only in charge to wait for a frame and when it occurs, wake-up the main receiver put in standby mode before that. The proposed wake-up receiver has been designed in NXP CMOS technology 160 μm. It provides a-54 dBm sensitivity, consuming 35 μA which allows a 70m range considering a 10 dBm emitter at 433,92 MHz. This wake-up receiver operates with ASK modulation, compared to others it provides a smart patented calibration system to get the necessary reference voltage for demodulation. This mechanism provide DC offset robustness and does not drain any current while the wake-up receiver is operating. To wake up the main receiver a 24 bits programmable Manchester code is required. This code at 25 kbps is programmable by the use of an SPI interface
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Guigue, Sébastien. "Développement, intégration et prototypage d'un noeud-capteur autonome à récupération d’énergie pour réseaux de capteurs sans fil." Electronic Thesis or Diss., Bordeaux, 2024. http://www.theses.fr/2024BORD0082.
Abstract:
Il y a eu une recrudescence du nombre de dispositifs connectés dans le contexte de l’Internet des objets. La multiplication des réseaux de capteurs sans fil a conduit à une augmentation du nombre de batteries et de déchets générés. Dans un contexte d’électronique verte, le développement de circuits autonomes alimentés par la récupération d’énergie doit être géré. Le premier chapitre donnera un aperçu des réseaux de capteurs sans fil, y compris une brève histoire de ces systèmes, les différents domaines d’application, les défis et quelques solutions possibles pour surmonter ces problèmes. Le second chapitre présentera la conception d’un microcontrôleur sur mesure pour l’application qui contrôle le noeud capteur avec une consommation minimale d’énergie. L’architecture du microcontrôleur, le jeu d’instructions, l’interfaçage et tous les choix de conception seront présentés. Le troisième chapitre décrit la conception d’une radio de réveil, un circuit toujours actif qui active le noeud capteur lorsqu’une requête est envoyée. Le choix de l’architecture de chaque bloc sera expliqué, en détaillant les différents aspects de chaque bloc. Les blocs sont les suivants : Un détecteur d’enveloppe pour la réception des données ; Un comparateur pour la démodulation des données ; Un oscillateur pour fournir une horloge pour le système, ; Un corrélateur pour comparer le message reçu avec une référence ; Une source de courant pour assurer la robustesse thermique.Le dernier chapitre fournit une analyse de l’ensemble du noeud de capteur sans fil. Une estimation de l’autonomie du noeud est présentée et une comparaison avec un noeud conçu avec des composants du marché est également présentée. Des perspectives d’amélioration pour les travaux futurs seront également exposéesThere has been an upsurge in the number of connected devices in the IoT(Internetof Things) context. The multiplication of Wireless Sensor Networks (WSNs) lead toan increase of the number of batteries and of waste generated. In a context of green electronics, the development of self-sustained circuits supplied with energy harvesting has to be managed.Chapter I will give an overview of wireless sensor networks, including a brief history these systems, the different fields of application, the challenges and some possible solutions to overcome these issues.Chapter II will present the design of a custom Microcontroller Unit (MCU) which runs the WSN with a minimum power consumption. The architecture of the microcontroller,the instruction set, the interfacing and all the design choices will be presented.Chapter III describes the design of a Wake-Up Radio (WuRx), an always-on circuit which switches on the WSN when a request is sent. The choice for the architecture of each block Will be explained, while detailing the different aspects of each block.The blocks areas follows : An envelope detector for data reception ;A comparator for data demodulation ; An oscillator to provide a clock for the system ; A correlator to compare the received message with a reference,; A current source to provide temperature robustness.Chapter IV provides an analysis of the entire wireless sensor node. An estimation of the node autonomy is presented and a comparison with a node designed with market components is presented. Perspectives of improvement for future works will also be presented
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Kraemer, Michael M. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS." Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0027/document.
Abstract:
La réglementation mondiale, pour des appareils de courte portée, permet l’utilisation sans licence de plusieurs Gigahertz de bande autour de 60 GHz. La bande des 60 GHz répond aux besoins des applications telles que les réseaux de capteurs très haut débit autonome en énergie,ou les transmissions à plusieurs Gbit/s avec des contraintes de consommation d’énergie. Il y a encore peu de temps, les interfaces radios fonctionnant dans la bande millimétrique n’étaient réalisables qu’en utilisant des technologies III-V couteuses. Aujourd’hui, les avancées des technologies CMOS nanométriques permettent la conception et la production en masse des circuits intégrées radiofréquences (RFIC) à faible coût.Cette thèse s’inscrit dans des travaux de recherches dédiés à la réalisation d’un système dans un boîtier (SiP, System in Package) à 60 GHz contenant à la fois l’interface radio (bande de base et circuits RF) ainsi qu’un réseau d’antennes. La première partie de cette thèse est dédiée la conception de la tête RF de l’émetteur-récepteur à faible consommation pour l’interface radio. Les blocs clefs de cette tête RF (amplificateurs, mélangeurs et un oscillateur commandé en tension) sont conçus, réalisés et mesurés en utilisant la technologie CMOS 65 nm de ST Microelectronics. Des éléments actifs et passifs sont développés spécifiquement pour l’utilisation au sein de ces blocs. Une étape importante vers l’intégration de la tête RF complète de l’émetteur-récepteur est l’assemblage de ces blocs de base afin de réaliser une puce émetteur et une puce récepteur. A ce but, une tête RF pour le récepteur a été réalisée. Ce circuit présent une consommation et un encombrement plus réduit que l’état de l’art.La deuxième partie de cette thèse présente le développement des modèles comportementaux des blocs de base conçus. Ces modèles au niveau système sont nécessaires afin de simuler le comportement du SIP, qui devient trop complexe si des modèles détaillés du niveau circuitsont utilisés. Dans cette thèse, une nouvelle technique modélisant le comportement en régime transitoire et régime permanent ainsi que le bruit de phase des oscillateurs commandés en tension est proposée. Ce modèle est implémenté dans le langage de description de matérielVHDL-AMS. La technique proposée utilise des réseaux de neurones artificiels pour approximer la caractéristique non linéaire du circuit. La dynamique est décrite dans l’espace d’état. Grâce à ce modèle, il est possible de réduire d’une façon drastique le temps de calcul des simulations système tout en conservant une excellente précisionWorldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs)at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form basic transmitter and receiver chips. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished.The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemented. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy
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Coulot, Thomas. "Stratégie d'alimentation pour les SoCs RF très faible consommation." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00951423.
Abstract:
Les réseaux de capteurs sans fil nécessitent des fonctions de calcul et de transmissionradio associées à chaque capteur. Les SoCs RF intégrant ces fonctions doivent avoir uneautonomie la plus grande possible et donc une très faible consommation. Aujourd'hui, leursperformances énergétiques pourraient être fortement améliorées par des systèmes d'alimentationinnovants. En effet, les circuits d'alimentation remplissent leur fonction classique de conversiond'énergie mais aussi des fonctions d'isolation des blocs RF et digitaux. Leurs performancess'évaluent donc en termes d'efficacité énergétique et de réponse transitoire mais aussi d'isolationentre blocs et de réjection de bruit.Ce travail de thèse concerne l'intégration du système de gestion et de distribution del'énergie aux différents blocs RF d'un émetteur/récepteur en élaborant une méthodologie " topdown" pour déterminer la sensibilité de chaque bloc à son alimentation et en construisant unearchitecture innovante et dynamique de gestion/distribution de l'énergie sur le SoC. Cetteméthodologie repose sur la disponibilité de régulateurs de tension présentant des performancesadaptées. Un deuxième volet du travail de thèse a donc été de réaliser un régulateur linéaire detype LDO à forte réjection sur une bande passante relativement large et bien adapté àl'alimentation de blocs RF très sensibles aux bruits de l'alimentation.
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Kraemer, Michael. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS." Phd thesis, INSA de Toulouse, 2010. http://tel.archives-ouvertes.fr/tel-00554674.
Abstract:
Worldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60 GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs) at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed and characterized for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form a basic receiver chip. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished. The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemente d. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy.
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Inanlou, Farzad Michael-David. "Innovative transceiver approaches for low-power near-field and far-field applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52245.
Abstract:
Wireless operation, near-field or far-field, is a core functionality of any mobile or autonomous system. These systems are battery operated or most often utilize energy scavenging as a means of power generation. Limited access to power, expected long and uninterrupted operation, and constrained physical parameters (e.g. weight and size), which limit overall power harvesting capabilities, are factors that outline the importance for innovative low-power approaches and designs in advanced low-power wireless applications. Low-power approaches become especially important for the wireless transceiver, the block in charge of wireless/remote functionality of the system, as this block is usually the most power hungry component in an integrated system-on-chip (SoC). Three such advanced applications with stringent power requirements are examined including space-based exploratory remote sensing probes and their associated radiation effects, millimeter-wave phased-array radar for high-altitude tactical and geological imaging, and implantable biomedical devices (IMDs), leading to the proposal and implementation of low-power wireless solutions for these applications in SiGe BiCMOS and CMOS and platforms.
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Sirigiri, Vijay Krishna. "Ultra-Low Power Ultra-Fast Hybrid CNEMS-CMOS FPGAs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1291259866.
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Verma, Naveen. "Ultra-low-power SRAM design in high variability advanced CMOS." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/53305.
Abstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 163-181).
Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target applications. Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia handsets, etc.) are an important class of applications driving ultra-low-power SRAMs. This thesis analyzes the energy of an SRAM sub-array. Since supply- and threshold-voltage have a strong effect, targets for these are established in order to optimize energy. Despite the heavy emphasis on leakage-energy, analysis of a high-density 256x256 sub-array in 45nm LP CMOS points to two necessary optimizations: (1) aggressive supply-voltage reduction (in addition to Vt elevation), and (2) performance enhancement. Important SRAM metrics, including read/write/hold-margin and read-current, are also investigated to identify trade-offs of these optimizations. Based on the need to lower supply-voltage, a 0.35V 256kb SRAM is demonstrated in 65nm LP CMOS. It uses an 8T bit-cell with peripheral circuit-assists to improve write-margin and bit-line leakage. Additionally, redundancy, to manage the increasing impact of variability in the periphery, is proposed to improve the area-offset trade-off of sense-amplifiers, demonstrating promise for highly advanced technology nodes. Based on the need to improve performance, which is limited by density constraints, a 64kb SRAM, using an offset-compensating sense-amplifier, is demonstrated in 45nm LP CMOS with high-density 0.25[mu]m2 bit-cells.
(cont.) The sense-amplifier is regenerative, but non -strobed, overcoming timing uncertainties limiting performance, and it is single-ended, for compatibility with 8T cells. Compared to a conventional strobed sense-amplifier, it achieves 34% improvement in worst-case access-time and 4x improvement in the standard deviation of the access-time.
by Naveen Verma.
Ph.D.
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Bargagli-Stoffi, Agnese [Verfasser]. "Ultra low-voltage, low-power amplifiers in deep submicrometer CMOS / Agnese Bargagli-Stoffi." Aachen : Shaker, 2006. http://d-nb.info/116651336X/34.
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Sadat, Md Anwar. "LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS ME." Doctoral diss., University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3390.
Abstract:
A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
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Tsui, Hau Yiu. "A 5 GHz integrated low-power CMOS RF front-end IC design /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20TSUI.
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Ordóñez, Hurtado Andrés Fernando. "Design methodology of a modular CMOS ultra-low power self-biased current source." reponame:Repositório Institucional da UFSC, 2017. https://repositorio.ufsc.br/xmlui/handle/123456789/178587.
Abstract:
Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2017.Made available in DSpace on 2017-08-22T04:25:03Z (GMT). No. of bitstreams: 1 347153.pdf: 5611883 bytes, checksum: ffcc82f51f6a3197acb623b2af028078 (MD5) Previous issue date: 2017
Neste documento é desenvolvida uma metodologia de projeto de uma fonte de corrente auto polarizada de ultra baixo consumo de potência em tecnologia CMOS. É descrita uma topologia modular implementada com dois MOSFETs auto cascodados (SCMs) e um amplificador operacional. A metodologia proposta está baseada no conceito de ni´veis de inversão e o espaço de projeto do circuito é descrito principalmente em termos das especificações do amplificador operacional e do espelho de corrente PMOS. O circuito foi projetado usando uma tecnologia padrão CMOS de 130 nm. Os resultados das simulações são apresentados neste documento para validar a metodologia de projeto e o desempenho da fonte de corrente, mostrando que o circuito proposto pode operar com uma tensão de alimentação menor de 1 V e com menos de 1%/V na regulação de linha.
Abstract : In this document a design procedure of a CMOS ultra-low-power self-biased current source is developed. A modular topology using two self-cascode MOSFETs (SCMs), a current mirror and an operational amplifier is implemented. The described methodology is based on the concept of inversion level, and the design space of the current source is described mainly in terms of the specifications of the operational amplifier and the PMOS current mirror. The circuit was designed in a 130 nm standard CMOS technology. Simulation results are provided to validate the design methodology and the performance of the current source, showing that the proposed circuit can operate at a supply voltage less than 1 V with less than 1%/V of line regulation.
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Dornelas, Helga Uchoa. "Low power SAR analog-to-digital converter for internet-of-things RF receivers." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/186015.
Abstract:
The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microprocessor and data storage unit. Energy supply is a limiting factor in many applications and the transceiver usually demands a significant amount of power. In this scenario the emerging wireless communication standard IEEE 802.11ah, in which this work focuses, was proposed as an option for low power sub-GHz radio communication. A typical architecture of modern radio receivers contains the analog radio-frequency (RF) front-end, which amplifies, demodulates and filters the input signal, and also analog-to-digital converters (ADC), that translate the analog signals to the digital domain. Additionally, the Successive-Approximation (SAR) ADC architecture has become popular recently due to its power efficiency, simplicity, and compatibility with scaled-down integrated CMOS technology. In this work, the RF receiver architecture and its specifications aiming low power consumption and IEEE 802.11ah standard complying are outlined, being the basis to the proposition of an 8-bit resolution and 10 MHz sampling rate ADC. A power efficient switching scheme for the charge redistribution SAR ADC architecture is explored in detail, along with the circuit-level design of the digital-to-analog converter (DAC). The transistor-level design of the two remaining ADC main blocks, sampling switch and comparator, are also explored. Electrical simulation of the physical layout, including parasitics, at a 130nm CMOS process resulted in a SINAD of 47:3 dB and 45:5 dB and at the receiver IF 3 MHz and at the Nyquist rate, respectively, consuming 21 W with a power supply of 1 V . The SAR ADC resulting Figure-of-Merit (FoM) corresponded to 11:1 fJ/conv-step at IF, and 13:7 fJ/conv-step at the Nyquist rate.
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Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.
Abstract:
Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Marsden, Kevin Matthew. "A Study of a Versatile Low Power CMOS Pulse Generator for Ultra Wideband Radios." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9754.
Abstract:
Ultra-Wideband (UWB) technologies are at the forefront of wireless communications, offering the possibility to provide extremely high data rate wireless solutions. In addition to high data rate applications, UWB technologies also offer an extremely low cost alternative for many low data rate systems. In this thesis, we describe the design of a CMOS pulse generator for impulse based UWB systems. The structure of our pulse generator is based on the topology of a single tap CMOS power amplifier. By increasing the number of taps on a CMOS power amplifier, it is possible to generate sub-nanosecond pulses with a desired shape. A power saving scheme that significantly reduces the power consumed at low data rates is also described. The versatility of our design lies in the ability to support dynamically varying output power levels and center frequencies. Our pulse generator design is extended to a rectified cosine generator, necessary for a multiband approach. The performance of our pulse generators is estimated through simulation with a target technology of TSMC 0.18 µm CMOS at a supply voltage of 1.8 V. The simulation results indicate that our pulse generator produces high fidelity Gaussian monocycle pulses with a pulse width of approximately 160 ps and a peak output power of more than 10 mW. We believe that our design of a CMOS pulse generator for UWB systems is a feasible option for many applications in which power and cost are most important.Master of Science
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Muppalla, Ashwin K. "Ultra low power multi-gigabit digital CMOS modem technology for millimeter wave wireless systems." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41084.
Abstract:
The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system.
The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis,
Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure.
The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a multi-gigabit wireless communication system. The demodulator operates at input data rates of multiple gigabits per second, which presents the challenge of designing the building blocks to operate at speeds of multiple GHz. The high speed complex multiplier is a major component of the non coherent demodulator. As part of the coherent demodulator the complex multiplier derotates the input sequence by multiplying with cosine and sine functions, Costas error calculator computes the phase error in the derotated input signal. The NCO (Numerically controlled Oscillator) is a look up table based system used to generate the cosine and sine functions, used by the derotator.The CIC filter is used to decimate the costas error signal as the loop bandwidth is significantly smaller compared to the sampling frequency. All these modules put together form the coherent demodulator which is an integral part of the wireless communication system. An implementation of Serdes is also presented which acts as an interface between the baseband modules and the RF front end.
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Paidimarri, Arun. "Architecture for ultra-low power multi-channel transmitters for Body Area Networks using RF resonators." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66473.
Abstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 99-103).
Body Area Networks (BANs) are gaining prominence for their use in medical and sports monitoring. This thesis develops the specifications of a ultra-low power 2.4GHz transmitter for use in a Body Area Networks, taking advantage of the asymmetric energy constraints on the sensor node and the basestation. The specifications include low transmit output powers, around -10dBm, low startup time, simple modulation schemes of OOK, FSK and BPSK and high datarates of 1Mbps. An architecture that is suited for the unique requirements of transmitters in these BANs is developed. RF Resonators, and in particular Film Bulk Acoustic Wave Resonators (FBARs) are explored as carrier frequency generators since they provide stable frequencies without the need for PLLs. The frequency of oscillation is directly modulated to generate FSK. Since these oscillators have low tuning range, the architecture uses multiple resonators to define the center frequencies of the multiple channels. A scalable scheme that uses a resonant buffer is developed to multiplex the oscillators' outputs to the Power Amplifier (PA). The buffer is also capable of generating BPSK signals. Finally a PA optimized for efficiently delivering the low output powers required in BANs is developed. A tunable matching network in the PA also enables pulse-shaping for spectrally efficient modulation. A prototype transmitter supporting 3 FBAR-oscillator channels in the 2.4GHz ISM band was designed in a 65nm CMOS process. It operates from a 0.7V supply for the RF portion and 1V for the digital section. The transmitter achieves 1Mbps FSK, up to 10Mbps for OOK and BPSK without pulse shaping and 1Mbps for OOK and BPSK with pulse shaping. The power amplifier has an efficiency of up to 43% and outputs between -15dBm and -7.5dBm onto a 50Q antenna. Overall, the transmitter achieves an efficiency of upto 26% and energy per bit of 483pJ/bit at 1Mbps.
by Arun Paidimarri.
S.M.
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Rafeei, Lalleh. "Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/31678.
Abstract:
Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or within a certain region of transistor operation. This thesis presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage all the way down into the subthreshold region. The framework uses the nominal frequency and power of a target circuit, which can be obtained using gate-level or transistor-level simulation tools as well as normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. A specific contribution of this thesis is to introduce a weighted average method, which is a major improvement to a previously published form of this framework. Another contribution is that the amount of process variation in ULV regions of a circuit can be estimated using the proposed framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being many orders of magnitude lower than the nominal voltage, the errors are no greater than 11.27 percent for circuit delay, 16.96 percent for active energy, and 4.86 percent for leakage power for the weighted averages technique. This is in contrast to the original framework which has a maximum error of 39.75, 17.60, and 8.90 percent for circuit delay, active energy, and leakage power, respectively. To validate our framework, a detailed analysis is given in the presence of a variety of design parameters such as fanout, transistor widths, et cetera. In addition, we also validate our framework for a range of sequential benchmark circuits.Master of Science
22
Johansson, Mattias, and Jonas Ehrs. "Low-Power Low-Noise IQ Modulator Designs in 90nm CMOS for GSM/EDGE/WCDMA/LTE." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54552.
Abstract:
The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator.
A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal.
The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.
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Roy, Sajib, and Md Murad Kabir Nipun. "Understanding Sub-threshold source coupled logic for ultra-low power application." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69404.
Abstract:
This thesis work primarily focuses on the applicability of sub-threshold source coupled logic (STSCL) for building digital circuits and systems that run at very low voltage and promise to provide desirable performance with excellent energy savings. Sectors like bio-engineering and smart sensors require the energy consumption to be effectively very low for long battery life. Alongside meeting the ultra-low power specification, the system must also be reliable, robust, and perform well under harsh conditions. In this thesis work, logic gates are designed and analyzed, using STSCL. These gates are further used for implementation of digital subsystems in small-sized smart dust sensors which would operate at very low supply voltages and consume extremely low power. For understanding the performance of STSCL with respect to ultra-low power and energy; a seven-stage ring oscillator, a 4-by-4 array multiplier, a fifth-order FIR filter and finally a fifty-fifth-order FIR filter were designed. The subcircuits and systems have been simulated for different supply voltages, scaling down to 0.2 V, at different temperature values (-20oC and 70oC) in both 45 nm and 65 nm process technologies. The chosen architectures for the FIR filters and array multiplier were conventional and essentially taken from traditional CMOS-based designs. The simulated results are studied, analyzed and compared with same CMOS-based digital circuits. The results show on the advantage of STSCL-based digital systems over CMOS. Simulation results provide an energy consumption of 1.1388 nJ for a fifty-fifth-order FIR filter, at low temperatures (-20oC), using STSCL logic, which is comparatively less than for the corresponding CMOS logic implementation.
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Zhang, Dai. "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.
Abstract:
Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.
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Værnes, Magne. "Trade-offs between Performance and Robustness for Ultra Low Power/Low Energy Subthreshold D flip-flops in 65nm CMOS." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2013. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-22704.
Abstract:
The need for Ultra Low Power systems has increased with increasing number of portable devices. The maintenance costs of battery powered systems can be greatly reduced by improving the battery time, especially in places where battery replacement is hard or impossible. Implementation of subthreshold D flip-flops in layout is one step closer to having a subthreshold building block library. The task for this thesis is to implement D flip-flop blocks, which are highly suitable for subthreshold operation in layout. These are the PowerPC 603, C$^2$MOS, a Classic NAND-based D flip-flop, and two Minority3-based D flip-flops. The D flip-flops are first custom designed for $250mV$ in schematic at transistor level, and then implemented in layout. The implementation in layout focuses on high robustness against process variations, by using high regularity for the cost of area.The D flip-flops are simulated in both schematic and layout, and the results are compared to each other and earlier results found in papers. The results show that the PowerPC 603 has the lowest PDP, the lowest power consumption, very low propagation delay, and an average relative standard deviation for delay. The C$^2$MOS has the lowest propagation delay, low power consumption and low PDP results. However, it has the highest relative standard deviation on delay. The Minority3-based D flip-flops have a very low relative standard deviation for delay, which makes them the most robust against process variations in this sense. However, they have the highest propagation delay, highest power consumption and PDP, and consumes the highest chip area. The Classic NAND-based D flip-flop has good PDP and power consumption results, but a high delay and average standard deviation for delay.Earlier papers show similar results for the C$^2$MOS and the PowerPC 603, but no results are found for the rest. Future work consists of implementing and testing forced-stacked blocks, body biasing, high threshold voltage transistors, and tape-out measurements.
26
Liendo, sanchez Andreina. "Study of adaptation mechanisms of the wireless sensor nodes to the context for ultra-low power consumption." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT095/document.
Abstract:
L'Internet des objets (IoT) est annoncé comme la prochaine grande révolution technologique où des milliards d'appareils s'interconnecteront en utilisant les technologies d’Internet et permettront aux utilisateurs d'interagir avec le monde physique, permettant Smart Home, Smart Cities, tout intelligent. Les réseaux de capteurs sans fil (WSN) sont cruciales pour tourner la vision de l'IoT dans une réalité, mais pour que cela devienne réalité, beaucoup de ces dispositifs doivent être autonomes en énergie. Par conséquent, un défi majeur est de fournir une durée de vie de plusieurs années tout en alimentant les nœuds par batteries ou en utilisant l'énergie récoltée. Bluetooth Low Energy (BLE) a montré une efficacité énergétique et une robustesse supérieures à celles d'autres protocoles WSN bien connus, ce qui fait BLE un candidat solide pour la mise en œuvre dans des scénarios IoT. En outre, BLE est présent dans presque tous les smartphones, ce qui en fait une télécommande universelle omniprésente pour les maisons intelligentes, les bâtiments ou les villes. Néanmoins, l'amélioration de la performance BLE pour les cas typiques d'utilisation de l'IoT, où la durée de vie de la batterie de nombreuses années, est toujours nécessaire.Dans ce travail, nous avons évalué les performances de BLE en termes de latence et de consommation d'énergie sur la base de modèles analytiques afin d'optimiser ses performances et d'obtenir son niveau maximal d'efficacité énergétique sans modification de la spécification en premier lieu. À cette fin, nous avons proposé une classification des scénarios ainsi que des modes de fonctionnement pour chaque scénario. L'efficacité énergétique est atteinte pour chaque mode de fonctionnement en optimisant les paramètres qui sont affectés aux nœuds BLE pendant la phase de découverte du voisin. Cette optimisation des paramètres a été réalisée à partir d'un modèle énergétique extrait de l'état de la technique. Le modèle, à son tour, a été optimisé pour obtenir une latence et une consommation d'énergie quel que soit le comportement des nœuds à différents niveaux: application et communication. Puisqu'un nœud peut être le périphérique central à un niveau, alors qu'il peut être le périphérique à l'autre niveau en même temps, ce qui affecte la performance finale des nœuds.En outre, un nouveau modèle d'estimation de la durée de vie de la batterie a été présenté pour montrer l'impact réel de l'optimisation de la consommation énergétique sur la durée de vie des nœuds, de façon rapide (en termes de temps de simulation) et réaliste (en tenant compte des données empiriques). Les résultats de performance ont été obtenus dans notre simulateur Matlab basé sur le paradigme OOP, à travers l'utilisation de plusieurs cas de test IoT. En outre, le modèle de latence utilisé pour notre étude a été validé expérimentalement ainsi que l'optimisation des paramètres proposée, montrant une grande précision.Après avoir obtenu les meilleures performances possibles de BLE sans modification de la spécification, nous avons évalué les performances du protocole en implémentant le concept de Wake-Up radio (WuR), qui est un récepteur d’ultra-faible consommation et qui est en charge de détecter le canal de communication, en attente d'un signal adressé au nœud, puis réveiller la radio principale. Ainsi, la radio principale, qui consomme beaucoup plus d'énergie, peut rester en mode veille pendant de longues périodes et passer en mode actif uniquement pour la réception de paquets, économisant ainsi une quantité d'énergie considérable. Nous avons démontré que la durée de vie de BLE peut être significativement augmentée en implémentant une WuR et nous proposons une modification du protocole afin de rendre ce protocole compatible avec un mode de fonctionnement qui inclut une WuR. Pour cela, nous avons étudié l'état de l'art de la WuR et évalué la durée de vie des périphériques BLE lorsqu'une WuR sélectionnée est implémentée du côté masterThe Internet of Things (IoT) is announced as the next big technological revolution where billions of devices will interconnect using Internet technologies and let users interact with the physical world, allowing Smart Home, Smart Cities, smart everything. Wireless Sensor Network (WSN) are crucial for turning the vision of IoT into a reality, but for this to come true, many of these devices need to be autonomous in energy. Hence, one major challenge is to provide multi-year lifetime while powered on batteries or using harvested energy. Bluetooth Low Energy (BLE) has shown higher energy efficiency and robustness than other well known WSN protocols, making it a strong candidate for implementation in IoT scenarios. Additionally, BLE is present in almost every smartphone, turning it into perfect ubiquitous remote control for smart homes, buildings or cities. Nevertheless, BLE performance improvement for typical IoT use cases, where battery lifetime should reach many years, is still necessary.In this work we evaluated BLE performance in terms of latency and energy consumption based on analytical models in order to optimize its performance and obtain its maximum level of energy efficiency without modification of the specification in a first place. For this purpose, we proposed a scenarios classification as well as modes of operation for each scenario. Energy efficiency is achieved for each mode of operation by optimizing the parameters that are assigned to the BLE nodes during the neighbor discovery phase. This optimization of the parameters was made based on an energy model extracted from the state of the art. The model, in turn, has been optimized to obtain latency and energy consumption regardless of the behavior of the nodes at different levels: application and communication. Since a node can be the central device at one level, while it can be the peripheral device at the other level at the same time, which affects the final performance of the nodes.In addition, a novel battery lifetime estimation model was presented to show the actual impact that energy consumption optimization have on nodes lifetime in a fast (in terms of simulation time) and realistic way (by taking into account empirical data). Performance results were obtained in our Matlab based simulator based on OOP paradigm, through the use of several IoT test cases. In addition, the latency model used for our investigation was experimentally validated as well as the proposed parameter optimization, showing a high accuracy.After obtaining the best performance possible of BLE without modification of the specification, we evaluated the protocol performance when implementing the concept of Wake-Up radio, which is an ultra low power receiver in charge on sensing the communication channel, waiting for a signal addressed to the node and then wake the main radio up. Thus, the main radio which consumes higher energy, can remain in sleep mode for long periods of time and switch to an active mode only for packet reception, therefore saving considerable amount of energy. We demonstrated that BLE lifetime can be significantly increased by implementing a Wake-Up radio and we propose a modification of the protocol in order to render this protocol compatible with an operating mode which includes a Wake-Up radio. For this, we studied the Wake-Up radio state of the art and evaluated BLE devices lifetime when a selected Wake-Up radio is implemented at the master side
27
Vauché, Rémy. "Conception de générateurs d'impulsions ultra-large bande en technologie CMOS." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10098.
Abstract:
La théorie de l'information développée par Claude Shannon (1916 - 2001) met en évidence le fait que pour accroître la capacité d'un canal de transmission, il est préférable d'élargir la bande de fréquences sur laquelle les informations sont émises plutôt que les puissances d'émissions. Cette constatation est le point de départ de nombreux travaux de recherche sur les communications Ultra-Large Bande (ULB) qui ont abouti en 2002 à la création aux Etats-Unis d'une bande fréquence dîtes ULB où aucun mode de communication n'est privilégié. C'est ainsi que 2 années plus tard ont débuté à l'IM2NP des travaux portant sur les communications ULB impulsionnelles, et notamment la conception d'amplificateur faible bruit, de détecteur d'énergie, mais également de générateurs d'impulsions qui est l'élément clé des émetteurs impulsionnels. Ces derniers constituent la base des travaux présentés dans le manuscrit qui se sont déroulés de 2008 à 2011. La nature discontinue des communications impulsionnelles a tout d'abord impliquée l'introduction de nouvelles figures de mérite permettant de mesurer les performances des générateurs d'impulsions. Ensuite, il est question de méthodes de conception permettant de dimensionner des structures fonctionnant aux fréquences en jeu mais également d'en réduire les consommations statiques principalement de fuite, et ce en vue de répondre aux contraintes de consommation des systèmes embarqués. Enfin sont développées 3 architectures de générateurs d'impulsions, chacune permettant de répondre à des contraintes différentes en termes de bande de fréquences, de consommation et de portéeThe information theory developed by Claude Shannon (1916 - 2001) highlights the fact that in order to increase the capacity of a transmission channel, it is preferable to extend the bandwidth used rather than the transmission power. This finding is the starting point of many papers on Ultra-Wideband (UWB) which led to the creation in the United States of UWB band since 2002 where no modulation is privileged. Two years later, many works on Impulsionnal Radio UWB (IR-UWB) communications began at IM2NP including the design of low noise amplifier, power detector, but also pulse generators which is the key element of IR-UWB emitters. These form basis of works presented in the manuscript that took place from 2008 to 2011. The discontinuous nature of communications impulse was first implied the introduction of new figures of merit for measuring performances of pulse generators. Then it deals with design techniques for sizing structures operating at frequencies involved, but also to reduce consumption and especially static leakage to reduce enough power consumption for embedded systems. Finally three architectures of pulse generators are developed, each one responding to different constraints in terms of frequency, consumption and range
28
Safari, Naeim. "Design of a DC/DC buck converter for ultra-low power applications in 65nm CMOS Process." Thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80395.
Abstract:
Switching mode DC/DC converters are critical building blocks in portable devices and hence their power efficiency, accuracy and cost are a major issue. The primary focus of this thesis is to address these critical issues.This thesis focuses on the different methods of feedback control loop which are employed in the switching mode DC/DC converters such as voltage mode control and current mode control. It also discusses about the structure of buck converter and tries to find an efficient solution for stepping-down the DC voltage level in ultra-low power applications. Based on this analysis, a 20 MHz voltage mode DC/DC buck converter with an on-chip compensated error amplifier in 65 nm CMOS process is designed and implemented.The power efficiency has been improved by sizing the power switches to have a low parasitic output and gate capacitances to reduce the capacitive and gate-drive losses. Also the error amplifier biasing current is chosen a small value (12.5 μA) to reduce the power dissipations in the control loop of the system. The maximum 84% power efficiency is achieved at 1.1 V to 500 mV conversion, above 81% efficiency can be achieved at load current from 0.5 mA to 1.26 mA. Due to wide bandwidth error amplifier and proper compensation network the fast transient response with settling time around 45 μs is achieved.
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Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.
30
Sen, Shreyas. "Design of process and environment adaptive ultra-low power wireless circuits and systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45755.
Abstract:
The objective of the proposed research is to investigate the design of Self-Aware Radio Frequency Circuits and Wireless Communication Systems that can adapt to environmental and process variations to always operate at minimum power levels possible, extending battery life.
The explosive growth of portable battery operated devices has mandated design of low power circuits and systems to prolong battery life. These devices fabricated in modern nanoscale CMOS technologies suffer from severe process variation due to the reduced controllability of the fabrication process, causing yield loss. This calls for integrated low power and process tolerant design techniques, or design of systems that can adapt to its process and environment to maintain its performance while minimizing power consumption.
Currently, most of the wireless circuits are designed to meet minimum quality-of-service requirements under worst-case wireless link conditions (interference, noise, multi-path effects), leading to high power consumption when the channel is better than worst-case. In this research, we develop a multi-dimensional adaptation approach for wireless transmitters and receivers that optimally trades-off power vs. performance across temporally changing operating conditions by concurrently tuning control parameters in the RF front end to lower power consumption. Tunable circuits (e.g. LNA) with built-in tuning knobs providing independent controllability of important specifications allow optimal adaptation. Process sensing using intelligent test and calibration facilitates yield improvement and the design of process tolerant environment adaptive systems.
Low cost testing methodologies are developed for identification of the health of the wireless circuit/system. These are used in conjunction with tuning algorithms that tune a wireless system under process variation to meet performance specifications and recover yield loss. This testing and adaptation is performed once during the post manufacture test/tune phase to compensate for manufacturing variations. This can also be applied periodically during in field operation of a device to account for performance degradation due to ageing. Finally, process tolerant environment adaptive systems are designed.
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Camponeschi, Matteo. "Analysis and design of CMOS and bipolar SiGe:C integrated circuits for low power RF receivers and radar applications." Doctoral thesis, Università degli studi di Padova, 2010. http://hdl.handle.net/11577/3427529.
Abstract:
This dissertation proposes the analysis and the design of two radio-frequency integrated circuits.
In the first part a low-power wireless receiver front-end for Wireless Sensor Networks is developed. The circuit comprises a Low-Noise Amplifier, Voltage Controlled Oscillators and Mixers, building a complete single-stage quadrature receiver front-end for low-power applications. The compact architecture based on a current reuse topology is described and motivated; an in-depth time-variant analysis is performed to optimize the circuit; a test 2.4GHz receiver is finally designed and realized in a cheap 90nm CMOS technology with a 3μm thick top metal for high-quality integrated inductors. Measurement results confirm the correctness of our analysis and the validity of the proposed circuit architecture.
In the second part of this dissertation a X-band upconverter for a Frequency-Modulated Continuous-Wave radar system is developed. The goal of the project is that of developing a wideband upconverter with a clean output spectrum and low phase noise. The proposed architecture is constituted by two mixers, baseband interfaces, a pre-power amplifier and the on-chip circuitry to generate quadrature local oscillator signals from an external reference local oscillator. Several mechanisms which lead to spurious tones at the output are discussed, with emphasis on the design issues related to the image-rejection, the mismatches and the nonlinearities in the large-signal baseband interface.
Two versions of the modulator are designed and compared: a) a CMOS version built in a 65nm digital technology based on a zero DC current passive mixer for minimum flicker noise and b) a bipolar version built in a 0.35μm SiGe:C technology based on an active Gilbert mixerQuesta tesi di dottorato propone l'analisi e la progettazione di due circuiti integrati a radio-frequenza. Nella prima parte del lavoro viene sviluppato il front-end di un ricevitore wireless a basso consumo di potenza per Wireless Sensor Networks. Il circuito, che comprende un amplificatore a basso rumore, oscillatori locali e mixer, costituisce un sistema di ricezione completo implementato in un singolo stadio per ridurre il consumo di potenza. L'architettura proposta, basata sulla tecnica del riutilizzo della corrente di polarizzazione, viene motivata e descritta in dettaglio; segue un'accurata analisi tempo-variante dell'architettura per l'ottimizzazione del circuito proposto; il ricevitore a 2.4GHz è stato infine realizzato con una tecnologia CMOS digitale a 90nm con top metal ottimizzato per la realizzazione di induttori integrati con alto fattore di qualità. Le misure effettute sui campioni confermano la correttezza della nostra analisi e la validità dell'architettura proposta. Nella seconda parte di questa tesi di dottorato viene sviluppato un upconverter per un Frequency-Modulated Continuous-Wave radar in banda X. L'obiettivo del progetto è quello di realizzare un upconverter a banda larga, con uno spettro in uscita libero da toni spuri e con minimo phase noise. L'architettura proposta comprende due mixer con relative interfacce in banda base, un amplificatore a radiofrequenza e tutta la circuiteria per la generazione dei segnali in quadratura per pilotare i mixer a partire da un oscillatore locale esterno di riferimento. Vengono analizzati vari meccanismi di generazione di toni spuri all'uscita, con particolare enfasi sui problemi legati alla reiezione dell'immagine, ai mismatches ed alle nonlinearità generate nell'interfaccia in banda base. Due versioni del modulatore sono state progettate e confrontate: a) una versione realizzata in una tecnologia CMOS a 65nm digitale basata su un mixer passivo a corrente di polarizzazione nulla per minimizzare la generazione di rumore flicker e b) una versione realizzata in una tecnologia bipolare SiGe:C a 0.35μm basata su un mixer di Gilbert attivo
32
El, Ghouli Salim. "UTBB FDSOI mosfet dynamic behavior study and modeling for ultra-low power RF and mm-Wave IC Design." Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAD015/document.
Abstract:
Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l’art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l’impact de la grille arrière, à l’aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l’inversion modérée jusqu’à 110 GHzThis research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz
33
Papotto, Giuseppe. "Batteryless RF transceiver for wireless sensor networks." Doctoral thesis, Università di Catania, 2012. http://hdl.handle.net/10761/1082.
Abstract:
Wireless sensor network (WSN) is a fast growing research area which has attracted considerable attentions both in industrial and academic environments in the last few years. In this work a complete RF transceiver for WSN applications is presented, which includes a RF energy harvesting system, a power management unit and a RF front end. The transceiver is able to operate by scavenging the required DC power from the incoming RF signal, thus avoiding the use of a battery. The use of a quartz oscillator has been avoided as well by exploiting the input signal as a frequency reference. This results in a highly integrated and low-cost transceiver solution.
The circuit was designed in a 90-nm CMOS technology by TSMC. The device operates with a minimum input power of 15 dBm and supports a 915 MHz FSK downlink and a 2.45 GHz OOK uplink, which attain a data rate up to 5 and 10 Mbps, respectively.
34
Ben, Amor Inès. "Gestion dynamique de la consommation de récepteurs RF : intégration de fronts-end RF ultra faible consommation." Thesis, Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4323.
Abstract:
L’émergence de l’internet des objets (IoT), les applications de types réseaux de capteurs et les nouveaux réseaux pour les objets nécessite le développement d’un nouvel écosystème. De nos jours, elle bouscule plusieurs secteurs de notre société. Cela, sollicite la conception des émetteurs-récepteurs radios fréquence à basse consommation étant donné que la réduction de la consommation d’énergie présente une contrainte importante dans le cas de ces applications afin d’obtenir une autonomie accrue. Dans ce contexte l’objet des travaux de thèse est de proposer des techniques de réduction de la consommation des récepteurs radio fréquence tout en cherchant à minimiser l’impact de ces techniques sur les performances des récepteurs réalisés. Dans l’optique de réaliser un démonstrateur composé d’un émetteur récepteur permettant une transmission vidéo, deux récepteurs UWB impulsionnel non cohérent à gestion dynamique d’énergie ont été réalisés en technologie HCMOS9 0.13µm de STMicroelectronics. Dans un premier temps, une étude des techniques de gestion dynamique d’alimentation sur les circuits analogiques radio fréquences a été proposée. Cette étude a été menée sur différents circuits qui semblent être le plus utilisés en conception de circuits analogiques à hautes fréquences. La technique proposée permet d’allumer et éteindre les circuits entre deux impulsions reçues afin de réduire leur consommation. L’application de cette technique nécessite par ailleurs une réduction du temps de latence causé par l’allumage et les extinctions des fonctions radio fréquence. Dans ce cas, un modèle permettant de minimiser l’impact de l’effet d’encapsulation a été proposéThe emergence of the Internet of Things (IoT), sensors networks and new networks to objects requires the development of a new ecosystem. Nowadays, it upsets many sectors of our society. It solicits design of low power radio transceivers as reducing energy consumption presents a major constraint in the case of these applications in order to obtain greater autonomy. In this context, the purpose of the thesis is to provide techniques allowing reducing the power consumption of radio frequency receivers while seeking to minimize the impact of these technologies on the performance of the achieved receiver. In order to realize a demonstrator consists of a transmitter and receiver for video transmission, two UWB receivers with dynamic power management have been made in 0.13µm HCMOS9 technology from STMicroelectronics. First, a study of dynamic power management techniques on analog radio frequency circuits was proposed. This study was conducted on different circuits that seem to be the most used in design of analog circuits at high frequencies. The proposed technique allows to turn on and off the circuit between two pulses received to reduce their consumption. The application of this technique also requires a reduction of the latency caused by the ignition and the extinction radio frequency functions. In this case, a model to minimize the impact of the encapsulating effect has been proposed. Secondly, the first receiver was performed for 6-10GHz frequency band and implements dynamic power management using the technique of "Power Gating"
35
Iwaki, Takao. "Ultra-low power single crystal silicon SOI-CMOS micro-hotplate with novel temperature-modulation principle for chemical sensing." Thesis, University of Warwick, 2007. http://wrap.warwick.ac.uk/89582/.
Abstract:
There is great need for the widespread use of indoor gas monitors as modern hermetically-sealed domestic buildings increasingly suffer from indoor air pollution. However, neither modern technologies of gas sensors nor analytical instruments are ideally suited to this purpose. The problems of gas sensors are poor selectivity and the fact that normally they can detect only one gas, and analytical instruments suffer from their large size and high price. Therefore, the aim of the project is "to develop a novel gas sensor with low cost, low power consumption, high reliability, which can detect multiple gases with excellent selectivity" for indoor gas monitoring. In the first part of the project, an SOI-CMOS micro-hotplate with a single crystal silicon (SCS) resistive heater was proposed, fabricated and characterised. The design obviates issues of traditional heater materials i.e. platinum is not CMOS compatible and polysilicon is not thermally stable due to its polycrystalline structure. The SCS micro-hotplate was found to have an ultra low power consumption of 11.6 mW to operate at 500°C, and an excellent reliability with less than 1% drift after 500 hour operation at 500°C. In the second part, a novel temperature modulation technique for a carbon black/polymer composite sensor was theoretically derived based upon linear solvation and Fickian diffusion. The processing technique comprises only two steps; summing the off and on transient conductance signals from a temperature-stepped sensor, and subtracting the steady-state signal. The technique was demonstrated by applying to a carbon black/polyvinylpyrrolidone composite sensor employing the novel micro-hotplate. Identification of water. methanol and ethanol vapours was successfully demonstrated using the peak time of the resultant curve. Furthermore, quantification of those vapours was found to be possible using the height of the peaks, which was linearly proportional to the concentration. In conclusion, a novel low-cost gas sensor has been realised that is capable of detecting more than one gas with a single sensing element and thermal modulation. This has the potential for commercial exploitation in the area of indoor air pollution monitoring.
36
Szilàgyi, Làszlò, Guido Belfiore, Ronny Henker, and Frank Ellinger. "20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS." Cambridge University Press, 2017. https://tud.qucosa.de/id/qucosa%3A70657.
Abstract:
The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm² , is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10⁻¹² at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.
37
Hu, Xin. "RF CMOS Tunable Gilbert Mixer with Wide Tuning Frequency and Controllable Bandwidth: Design Sythesis and Verification." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright149572725296626.
38
Mattia, Neto Oscar Elisio. "NanoWatt resistorless CMOS voltage references for Sub-1 V applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107131.
Abstract:
Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas.Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.
39
yasami, saeed. "Design and Evaluation of an Ultra-Low PowerLow Noise Amplifier LNA." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50923.
Abstract:
This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW
40
Alena, Đugova. "Nova konfiguracija širokopojasnog nisko-šumnog pojačavača u CMOS tehnologiji." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2016. https://www.cris.uns.ac.rs/record.jsf?recordId=100329&source=NDLTD&language=en.
Abstract:
Nisko-šumni pojačavač (NŠP) nalazi se u prijemnom delu bežičnogprimopredajnika neposredno nakon antene. NJegova uloga je da ulaznisignal određene frekvencije i male snage izdvoji i pojača iznad nivoašuma prijemnika. U okviru doktorske disertacije prikazane su iopisane metode za projektovanje širokopojasnih (UWB) NŠP u CMOStehnologiji. Ukupno je predloženo devet novih konfiguracija NŠP. Naosnovu dobijenih rezultata, u 0,18 μm UMC CMOS tehnologijirealizovan je i fabrikovan NŠP jednostavne topologije, kojapredstavlja zbir dva pristupa, pojačavačkog stepena kaskodnestrukture sa povratnom spregom i stepena sa višestrukimiskorišćenjem struje. NŠP je projektovan za frekvencijski opseg od3,1 do 5 GHz. Takođe, opisana je metoda za merenje parametara NŠP, azatim je i izvršena njegova karakterizacija.In the transceiver chain the low noise amplifier (LNA) is placed in the frontendof the receiver after the antenna. The LNA needs to isolate and amplifyreceived weak signal at a specific frequency above the noise level of thereceiver. In the scope of this doctoral dissertation methods for designingultra-wideband (UWB) LNA in CMOS technology are presented anddescribed. Nine new LNA configurations were proposed. Based on theobtained results, simple LNA configuration, obtained by merging casodefeedback topology and current-reuse technique, was realized and fabricatedin 0.18 μm UMC CMOS technology. The LNA is designed for the frequencyband from 3.1 to 5 GHz. In addition, the method for measurement LNAparameters is described and the proposed LNA was characterized.
41
Ben, Amor Inès. "Gestion dynamique de la consommation de récepteurs RF : intégration de fronts-end RF ultra faible consommation." Electronic Thesis or Diss., Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4323.
Abstract:
L’émergence de l’internet des objets (IoT), les applications de types réseaux de capteurs et les nouveaux réseaux pour les objets nécessite le développement d’un nouvel écosystème. De nos jours, elle bouscule plusieurs secteurs de notre société. Cela, sollicite la conception des émetteurs-récepteurs radios fréquence à basse consommation étant donné que la réduction de la consommation d’énergie présente une contrainte importante dans le cas de ces applications afin d’obtenir une autonomie accrue. Dans ce contexte l’objet des travaux de thèse est de proposer des techniques de réduction de la consommation des récepteurs radio fréquence tout en cherchant à minimiser l’impact de ces techniques sur les performances des récepteurs réalisés. Dans l’optique de réaliser un démonstrateur composé d’un émetteur récepteur permettant une transmission vidéo, deux récepteurs UWB impulsionnel non cohérent à gestion dynamique d’énergie ont été réalisés en technologie HCMOS9 0.13µm de STMicroelectronics. Dans un premier temps, une étude des techniques de gestion dynamique d’alimentation sur les circuits analogiques radio fréquences a été proposée. Cette étude a été menée sur différents circuits qui semblent être le plus utilisés en conception de circuits analogiques à hautes fréquences. La technique proposée permet d’allumer et éteindre les circuits entre deux impulsions reçues afin de réduire leur consommation. L’application de cette technique nécessite par ailleurs une réduction du temps de latence causé par l’allumage et les extinctions des fonctions radio fréquence. Dans ce cas, un modèle permettant de minimiser l’impact de l’effet d’encapsulation a été proposéThe emergence of the Internet of Things (IoT), sensors networks and new networks to objects requires the development of a new ecosystem. Nowadays, it upsets many sectors of our society. It solicits design of low power radio transceivers as reducing energy consumption presents a major constraint in the case of these applications in order to obtain greater autonomy. In this context, the purpose of the thesis is to provide techniques allowing reducing the power consumption of radio frequency receivers while seeking to minimize the impact of these technologies on the performance of the achieved receiver. In order to realize a demonstrator consists of a transmitter and receiver for video transmission, two UWB receivers with dynamic power management have been made in 0.13µm HCMOS9 technology from STMicroelectronics. First, a study of dynamic power management techniques on analog radio frequency circuits was proposed. This study was conducted on different circuits that seem to be the most used in design of analog circuits at high frequencies. The proposed technique allows to turn on and off the circuit between two pulses received to reduce their consumption. The application of this technique also requires a reduction of the latency caused by the ignition and the extinction radio frequency functions. In this case, a model to minimize the impact of the encapsulating effect has been proposed. Secondly, the first receiver was performed for 6-10GHz frequency band and implements dynamic power management using the technique of "Power Gating"
42
Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.
Abstract:
In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture. Based on this analysis, dynamic two-stage comparator is selected due to its energy efficiency and capability of working in low supply voltages. Eventually, based on these studies an ultra-low power 10-bit SAR ADC in 65 nm technology is designed. Simulation results predict that the ADC consumes 12.4nW and achieves an energy efficiency of 14.7fJ/conversion at supply voltage of 1V and sampling frequency of 1kS/s. It has a signal-to-noise-and-distortion (SINAD) ratio of 60.29dB and effective-number-of-bits (ENOB) of 9.72 bits. The ADC is functional down to supply voltage of 0.5V with proper performance and minimal power consumption of 6.28nW.
43
Ippolito, Calogero. "A CMOS Frequency Synthesizer for Wireless Sensor Network transceivers." Doctoral thesis, Università di Catania, 2012. http://hdl.handle.net/10761/1080.
Abstract:
Negli ultimi anni il mercato dei sistemi wireless è cresciuto immensamente. I sistemi di comunicazione wireless sono penetrati in tutti gli aspetti della nostra vita, dal lavoro al tempo libero, e sono diventati per noi indispensabili.
Lo sviluppo di dispositivi a bassissimo consumo di potenza utilizzabili nei sistemi di comunicazione wireless può estendere le frontiere delle reti di sensori verso nuove applicazioni, ad esempio quelle automobilistiche, per la casa, trattamenti medicali avanzati, oppure il monitoraggio di strutture complesse. Queste applicazioni hanno esigenze comuni, come l alta autonomia operativa dei nodi, piccole dimensioni fisiche, e alta affidabilità.
Oggigiorno, l interfaccia di comunicazione radio è la parte più critica nella realizzazione di un nodo wireless poiché contribuisce significativamente al consumo di potenza di tutto il sistema e impatta fortemente sulle prestazioni. In particolare il sintetizzatore di frequenza è un blocco molto critico, poiché deve garantire alte prestazioni mantenendo bassissimi consumi di potenza.
Il lavoro oggetto di questa tesi focalizza l attenzione sulla progettazione, l implementazione e la caratterizzazione sperimentale di un sintetizzatore di frequenza che garantisce un ampia banda operativa di frequenza e bassissimi consumi di potenza, utilizzabile nelle interfacce a radio frequenza all interno di una rete di sensori.
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Brandano, Davide. "Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS." Doctoral thesis, Universitat Politècnica de Catalunya, 2012. http://hdl.handle.net/10803/81303.
Abstract:
Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.
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Lee, Hyung-Jin. "Digital CMOS Design for Ultra Wideband Communication Systems: from Circuit-Level Low Noise Amplifier Implementation to a System-Level Architecture." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/26195.
Abstract:
CMOS technology is particularly attractive for commercialization of ultra wideband (UWB) radios due to its low power and low cost. In addition to CMOS implementation, UWB radios would also significantly benefit from a radio architecture that enables digital communications. In addition to the normal challenges of CMOS RFIC design, there are two major technical challenges for the implementation of CMOS digital UWB radios. The first is building RF and analog circuitry covering wide bandwidth over several GHz. The second is sampling and digitizing high frequency signals in the UWB frequency range of 3 GHz to 10 GHz, which is not feasible for existing CMOS analog-to-digital converters.
In this dissertation, we investigate the two technical challenges at the circuit level and the system level. We propose a systematic approach at the circuit level for optimal transistor sizing and biasing conditions that result in optimal noise and power matching over a wide bandwidth. We also propose a general scheme for wideband matching. To verify our methods, we design two single-stage low noise amplifiers (LNAs) in TSMC 0.18µm CMOS technology. Measurement results from fabricated chips indicate that the proposed LNAs could achieve as high as 16 dB power gain and as low as 2.2 dB noise figure with only 6.4 mA current dissipation under a supply voltage of 1.2 V.
At the system level, we propose a unique frequency domain receiver architecture. The receiver samples frequency components of a received signal rather than the traditional approach of sampling a received signal at discrete instances in time. The frequency domain sampling leads to a simple RF front-end architecture that directly samples an RF signal without the need to downconvert it into a baseband signal. Further, our approach significantly reduces the sampling rate to the pulse repetition rate. We investigate a simple, low-power implementation of the frequency domain sampler with 1-bit ADCs. Simulation results show that the proposed frequency-domain UWB receiver significantly outperforms a conventional analog correlator.
A digital UWB receiver can be implemented efficiently in CMOS with the proposed LNA as an RF front-end, followed by the frequency domain sampler.Ph. D.
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Liu, Yidong. "CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.
Abstract:
Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.; The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (Vsubscript T) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (Vsubscript T]) shift and 25% to electron mobility (mu subscript n]) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation.ID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
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Khan, Abbas. "Optimization through Co-Simulation of Antenna, Bandpass Filter and Low-Noise Amplifier at 6-9 GHz." Thesis, Linköpings universitet, Fysik och elektroteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110575.
Abstract:
Ultra-wide band (UWB) 6-9 GHz antenna, band pass filter and low-noise amplifier (LNA) optimization using co-simulation of the RF front-end. At higher frequencies, carefully conducted design methodologies are required for RF front-end parameter optimization, such as power gain and low noise figure with low power consumption.
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Zhang, Tao [Verfasser], Georg [Akademischer Betreuer] Böck, and Stefan [Akademischer Betreuer] Heinen. "Low power CMOS RF-transceiver circuits for K-band wireless localization systems / Tao Zhang. Gutachter: Georg Böck ; Stefan Heinen. Betreuer: Georg Böck." Berlin : Technische Universität Berlin, 2014. http://d-nb.info/1067387412/34.
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Liu, Jing. "Développement de cellules élémentaires radiofréquences faible consommation en technologie FDSOI pour des applications liées à l'internet des objets." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT057.
Abstract:
Les applications sans fil sont presque par définition des appareils alimentés par des batteries. La consommation d’énergie est donc une préoccupation majeure pour la conception des LNAs. Il existe toujours des compromis pour satisfaire le facteur de faible bruit, un gain raisonnable, une linéarité élevée, une faible consommation et un faible coût.L’objectif de ce travail est de concevoir un amplificateur faible bruit LNA en technologie CMOS 28 nm FDSOI fournit par STMicroelectronics en mettant en œuvre la méthode de conception en gm/ID et la technique RFPG (RF power gating). La partie principale de cette conception est de réaliser des LNAs avec une très faible consommation sans dégrader les performances.Dans un premier temps, la conception du LNA est basée sur la méthodologie gm/ID et sur les caractéristiques de la technologie de 28nm FDSOI. Pour ces technologies avancées, des travaux récents montrent que des bons compromis entre les performances et la consommation d’énergie peuvent être obtenus dans les régions d'inversions modérées ou faibles. Dans ce travail, nous présentons une méthode complète pour dimensionner les LNA à la topologie de capacité feedback. Cette topologie a été choisie pour sa compacité puisqu'une seule inductance est utilisée (dans le réseau d'adaptation d'entrée). Cette conception présentée permet d’atteindre certaines performances données NF (Noise Figure) et Glna (gain en tension) avec une consommation d’énergie minimale et une faible valeur d’inductance afin de mieux contrôler le coût du LNA. Cette conception LNA à faible consommation repose sur une approche gm/ID adaptée à la conception RF dans des technologies avancées comme FDSOI. Cette méthode permet également de dimensionner tous les composants pour atteindre un Glna et de NF donné, en maximisant le rapport gm/ID afin de minimiser la consommation d’énergie. De plus, même si la linéarité n’est pas considérée comme une contrainte de conception, cette méthode a des bonnes performances IIP3 car elle tend à réduire le facteur de qualité en entrée, ce qui entraîne une non-linéarité élevée. Cette méthode proposée permet également d'avoir une faible valeur d'inductance d'entrée pour l'adaptation. Cette inductance peut être remplacée des bonding.Dans un deuxième temps, un LNA avec la technique RFPG est présenté. Sur la base du premier LNA, un LNA RFPG est conçu avec pour principale caractéristiques sa très faible consommation (allumer et éteindre rapidement le LNA). Le principe de RFPG consiste à utiliser des blocs RF tels que LNA ou Mixer pendant le temps des symboles. Cette approche est basée sur l'observation que, dans le cas d'un bon canal de propagation, il n'est pas nécessaire de collecter toute l'énergie du symbole. Avec cette technique, il est possible d'adapter les performances du récepteur à la qualité du canal et ainsi d'adapter la consommation d'énergie.Avec la méthode gm/ID, la technique RFPG sur la technologie avancée FDSOI, la consommation de LNA peut être largement réduit en gardant les bonnes performances.Mots-clés: Amplificateur faible bruit; capacitive feedback; faible consommation; gm/ID; RFPG(RF power gating); 28nm FDSOIWireless applications are almost by definition battery powered devices. Power consumption is therefore a major concern for the LNA design. There are always compromises to satisfy the low noise factor, reasonable gain, high linearity, low power and low cost.The objective of this work is to design a low noise amplifier LNA in 28 nm FDSOI technology provided by STMicroelectronics by implementing the design method of gm/ID and the RFPG (RF power gating) technique. The main part of this design is to achieve LNAs with very low power consumption without degrading performance.At first, the LNA design is based on the gm/ID methodology and the characteristics of the 28nm FDSOI technology. For such technologies, recent works show that good trade-offs between performances and consumption can be obtained in moderate or weak inversion region. In this work we present a complete method to size capacitive feedback LNAs. This topology is chosen for its compactness since only one inductor is used (in the input matching network). The presented design flow allows reaching some given performances (Noise Figure NF and voltage gain Glna) with the minimum power consumption while having a design constraint on the value of the inductor to better control the cost of the LNA. This low-power LNA conception is based on a gm/ID approach which is suitable for RF design in advanced technologies such as FDSOI. This method allows the sizing of all the components to reach a given NF and voltage gain while maximizing the gm/ID to minimize the power consumption. In addition, even if the linearity is not considered as a design constraint, this method leads to good IIP3 performances because it tends to reduce the input quality factor which causes high non-linearity. Moreover, this proposed method makes it possible to have a low input inductance value for adaptation. This inductance can also be replaced by bonding.In a second step, a LNA with the RFPG technique is presented. Based on a first LNA, a RFPG LNA is designated in very low consumption by turning on and off the LNA quickly. The principle of RFPG consists on power gating RF blocs such as LNA or Mixer during the symbol time. This approach is based on the observation that, in the case of a good propagation channel, it is not necessary to collect all the energy of the symbol. With this technique, it is possible to adapt the performance of the receiver to the quality of the channel and thus to adapt the power consumption.With the gm/ID method, the RFPG technique on advanced FDSOI technology, LNA consumption can be greatly reduced in keeping good performance.Mots-clés: Low noise amplifier; capacitive feedback; low power; gm/ID; RFPG (RF power gating); 28nm FDSOI
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Funke, Dominic A. [Verfasser], Jürgen [Gutachter] Oehm, and Nils [Gutachter] Pohl. "Ultra-Low-Power Schaltungen für Mikrosysteme in CMOS-Technologie / Dominic A. Funke ; Gutachter: Jürgen Oehm, Nils Pohl ; Fakultät für Elektrotechnik und Informationstechnik." Bochum : Ruhr-Universität Bochum, 2019. http://d-nb.info/1199613959/34.