Dissertations / Theses on the topic 'Tunneling field effect transistor'
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1
Nirschl, Thomas [Verfasser]. "Circuit Applications of the Tunneling Field Effect Transistor (TFET) / Thomas Nirschl." Aachen : Shaker, 2007. http://d-nb.info/1166512053/34.
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Chou, Mike Chuan 1969. "Process development for a silicon planar resonant-tunneling field-effect transistor." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/34047.
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Shao, Ye. "Study of wide bandgap semiconductor nanowire field effect transistor and resonant tunneling device." The Ohio State University, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=osu1448230793.
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AL-SHADEEDI, AKRAM. "LATERAL AND VERTICAL ORGANIC TRANSISTORS." Kent State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=kent1492441683969202.
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Glaß, Stefan [Verfasser], Siegfried [Akademischer Betreuer] Mantl, and Matthias [Akademischer Betreuer] Wuttig. "Si/SiGe-based gate-normal tunneling field-effect transistors / Stefan Glaß ; Siegfried Mantl, Matthias Wuttig." Aachen : Universitätsbibliothek der RWTH Aachen, 2019. http://d-nb.info/1193181453/34.
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Rolseth, Erlend Granbo [Verfasser], and Jörg [Akademischer Betreuer] Schulze. "Experimental studies on germanium-tin p-channel tunneling field effect transistors / Erlend Granbo Rolseth ; Betreuer: Jörg Schulze." Stuttgart : Universitätsbibliothek der Universität Stuttgart, 2017. http://d-nb.info/1156603994/34.
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Schmidt, Matthias [Verfasser]. "Fabrication, characterization and simulation of band-to-band tunneling field-effect transistors based on silicon-germanium / Matthias Schmidt." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2013. http://d-nb.info/1044748915/34.
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Wang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling." Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.Philip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.
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Nadimi, Ebrahim. "Quantum Mechanical and Atomic Level ab initio Calculation of Electron Transport through Ultrathin Gate Dielectrics of Metal-Oxide-Semiconductor Field Effect Transistors." Doctoral thesis, Universitätsbibliothek Chemnitz, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200800477.
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The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing quantum mechanical effects, which are no longer negligible. Gate tunneling current is one of such effects, that is responsible for high power consumption and high working temperature in microprocessors. This in turn put limits on further down scaling of devices. Therefore modeling and calculation of tunneling current is of a great interest. This work provides a review of existing models for the calculation of the gate tunneling current in MOSFETs. The quantum mechanical effects are studied with a model, based on a self-consistent solution of the Schrödinger and Poisson equations within the effective mass approximation. The calculation of the tunneling current is focused on models based on the calculation of carrier’s lifetime on quasi-bound states (QBSs). A new method for the determination of carrier’s lifetime is suggested and then the tunneling current is calculated for different samples and compared to measurements. The model is also applied to the extraction of the “tunneling effective mass” of electrons in ultrathin oxynitride gate dielectrics. Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore, atomic scale deformations at interfaces and within the dielectric could have great influences on the performance of the dielectric layer and consequently on the tunneling current. On the other hand the specific material parameters would be changed due to atomic level deformations at interfaces. A combination of DFT and NEGF formalisms has been applied to the tunneling problem in the second part of this work. Such atomic level ab initio models take atomic level distortions automatically into account. An atomic scale model interface for the Si/SiO2 interface has been constructed and the tunneling currents through Si/SiO2/Si stack structures are calculated. The influence of single and double oxygen vacancies on the tunneling current is investigated. Atomic level distortions caused by a tensile or compression strains on SiO2 layer as well as their influence on the tunneling current are also investigatedDie vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden
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Vishnoi, Rajat. "Modelling of nanoscale tunnelling field effect transistors." Thesis, IIT Delhi, 2016. http://localhost:8080/xmlui/handle/12345678/7030.
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Johnson, Simon. "Field effect transistor type sensors." Thesis, Cardiff University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.259174.
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Takshi, Arash. "Organic metal-semiconductor field-effect transistor (OMESFET)." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/31531.
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Organic electronics offers the possibility of producing ultra-low-cost and large-area electronics using printing methods. Two challenges limiting the utility of printed electronic circuits are the high operating voltage and the relatively poor performance of printed transistors. It is shown that voltages can be reduced by replacing the capacitive gate used in Organic Field-Effect Transistors (OFETs) with a Schottky contact, creating a thin-film Organic Metal-Semiconductor Field-Effect Transistor (OMESFET). This geometry solves the voltage issue, and promises to be useful in situations where low voltage operation is important, but good performance is not essential. In cases where high voltage is acceptable or required, it is shown that OFET performance can be greatly improved by employing a Schottky contact as a second gate. The relatively thick insulating layer between the gate and the semiconductor in OFETs makes it necessary to employ a large change of gate voltage (~40 V) to control the drain current. In order to reduce the voltage to less than 5 V a very thin (<10 nm) insulating layer and/or high-k dielectric materials can be used, but these solutions are not compatible with current printing technology. Simulations and implementations of OMESFET devices demonstrate low voltage operation (<5 V) and improved sub-threshold swing compared to the OFET. However, these benefits are achieved at the expense of mobility. In order to achieve good performance in an OFET, including threshold voltage, current ratio and output resistance, the semiconductor thickness has to be less than 50 nm, whereas the thickness of a printed semiconductor is typically larger than 200 nm. The addition of a top Schottky contact on the OFET creates a depletion region thereby reducing the effective thickness of the semiconductor, and resulting in enhanced transistor performance. Simulations and experimental results show improvements in the threshold voltage, the current ratio, and the output resistance of a dual gate transistor, when compared to those in an OFET of the same thickness. The transistors introduced in this work demonstrate means of improving the performance of thick-film OFETs and of achieving substantially lower operation voltage in organic transistors.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
13
Dölle, Michael. "Field effect transistor based CMOS stress sensors /." Tönning ; Lübeck Marburg : Der Andere Verlag, 2006. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=016086105&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
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Arthur, Joshua N. "Hygroscopic insulator organic field effect transistor sensors." Thesis, Queensland University of Technology, 2022. https://eprints.qut.edu.au/232689/1/Joshua_Arthur_Thesis.pdf.
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Hygroscopic insulator field effect transistors (HIFETs) are organic transistors with promising characteristics for biosensing applications. However, their fundamental sensing mechanisms are not yet fully understood. This thesis explores HIFET sensors through detailed electrical and optical characterisation, providing vital insights into the distinct mechanisms by which HIFETs detect biologically relevant chemicals. Hydrogen peroxide, a by-product of enzymatic reactions, oxidises the organic semiconductor, modulating the output current. Ionic solutions, such as KCl, NaCl and HCl, modulate the current by changing double layer capacitance. These insights are foundational for the continued development of HIFETs as effective multipurpose biosensing platforms.
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Günther, Alrun Aline. "Vertical Organic Field-Effect Transistors." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-207731.
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Diese Arbeit stellt eine eingehende Studie des sogenannten Vertikalen Organischen Feld-Effekt-Transistors (VOFET) dar, einer neuen Transistor-Geometrie, welche dem stetig wachsenden Bereich der organischen Elektronik entspringt. Dieses neuartige Bauteil hat bereits bewiesen, dass es in der Lage ist, eine der fundamentalen Einschränkungen herkömmlicher organischer Feld-Effekt-Transistoren (OFETs) zu überwinden: Die für Schaltfrequenz und An-Strom wichtige Kanallänge des Transistors kann im VOFET stark reduziert werden, ohne dass teure und komplexe Strukturierungsmethoden genutzt werden müssen. Das genaue Funktionsprinzip des VOFET ist bisher jedoch weitgehend unerforscht. Durch den Vergleich von experimentellen Daten mit Simulationsdaten des erwarteten Bauteil-Verhaltens wird hier ein erstes, grundlegendes Verständnis des VOFETs erarbeitet. Die so gewonnenen Erkenntnisse werden im Folgenden genutzt, um bestimmte Parameter des VOFETs kontrolliert zu manipulieren. So wird beispielsweise gezeigt, dass die Morphologie des organischen Halbleiters, und damit seine Abscheidungsparameter, sowohl für die VOFET-Herstellung als auch für den Ladungsträgertransport im fertigen Bauteil eine wichtige Rolle spielen. Weiterhin wird gezeigt, dass der VOFET, genau wie der konventionelle OFET, durch das Einbringen von Kontaktdotierung deutlich verbessert werden kann. Mit Hilfe dieser Ergebnisse kann gezeigt werden, dass das Funktionsprinzip des VOFETs mit dem eines konventionellen OFETs nahezu identisch ist, wenn man von geringen Abweichungen aufgrund der unterschiedlichen Geometrien absieht. Basierend auf dieser Erkenntnis wird schließlich ein VOFET präsentiert, welcher im Inversionsmodus betrieben werden kann und so die Lücke zur konventionellen MOSFET-Technologie schließt. Dieser Inversions-VOFET stellt folglich einen vielversprechenden Ansatz für leistungsfähige organische Transistoren dar, welche als Grundbausteine für komplexe Elektronikanwendungen auf flexiblen Substraten genutzt werden könnenThis work represents a comprehensive study of the so-called vertical organic field-effect transistor (VOFET), a novel transistor geometry originating from the fast-growing field of organic electronics. This device has already demonstrated its potential to overcome one of the fundamental limitations met in conventional organic transistor architectures (OFETs): In the VOFET, it is possible to reduce the channel length and thus increase On-state current and switching frequency without using expensive and complex structuring methods. Yet the VOFET's operational principles are presently not understood in full detail. By simulating the expected device behaviour and correlating it with experimental findings, a basic understanding of the charge transport in VOFETs is established and this knowledge is subsequently applied in order to manipulate certain parameters and materials in the VOFET. In particular, it is found that the morphology, and thus the deposition parameters, of the organic semiconductor play an important role, both for a successful VOFET fabrication and for the charge transport in the finished device. Furthermore, it is shown that VOFETs, just like their conventional counterparts, are greatly improved by the application of contact doping. This result, in turn, is used to demonstrate that the VOFET essentially works in almost exactly the same way as a conventional OFET, with only minor changes due to the altered contact arrangement. Working from this realisation, a vertical organic transistor is developed which operates in the inversion regime, thus closing the gap to conventional MOSFET technology and providing a truly promising candidate for high-performance organic transistors as the building blocks for advanced, flexible electronics applications
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Lebby, M. S. "Fabrication and characterisation of the Heterojunction field effect transistor (HFET) and the bipolar inversion channel field effect transistor (BIFCET)." Thesis, University of Bradford, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379863.
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Goh, Roland Ghim Siong. "Carbon nanotubes for organic electronics." Thesis, Queensland University of Technology, 2008. https://eprints.qut.edu.au/20849/1/Roland_Goh_Thesis.pdf.
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This thesis investigated the use of carbon nanotubes as active components in solution processible organic semiconductor devices. We investigated the use of functionalized carbon nanotubes in carbon nanotubes network transistors (CNNFET) and in photoactive composites with conjugated polymers. For CNNFETs, the objective was to obtain detailed understanding of the dependence of transistor characteristics on nanotubes bundle sizes, device geometry and processing. Single walled carbon nanotubes were functionalized by grafting octadecylamine chains onto the tubes, which rendered them dispersible in organic solvents for solution processing. To investigate the dependence of electronic properties of carbon nanotubes networks on bundle size, we developed a centrifugal fractionation protocol that enabled us to obtain nanotube bundles of different diameters. The electronic properties of networks of nanotube bundles deposited from solution were investigated within a CNNFET device configuration. By comparing devices with different degree of bundling we elucidated the dependence of key device parameters (field effect mobility and on/off ratio) on bundle sizes. We further found that, in contrast to traditional inorganic transistors, the electronic properties of the CNNFETs were dominated by the channel rather than contact resistance. Specifically, the apparent mobility of our devices increased with decreasing channel length, suggesting that the charge transport properties of CNNFETs are bulk rather than contacts dominated. This meant that charge traps in the channel of the device had a significant effect on transport properties. We found that charge traps in the channel region introduced by adsorbed oxygen and silanol groups on the SiO2 surface were responsible for the dominant p-type conductance in as-fabricated devices. Based on this understanding, we demonstrated the p-type to n-type conversion of the transistor characteristics of CNNFETs by depositing nanotubes on electron-trapfree dielectric surfaces. Finally, by combining annealing and surface treatment, we fabricated CNNFETs with high n-type mobility of 6cm2/V.s. For polymer composites, the objective was to obtain detailed understanding of the interactions between carbon nanotubes and the conjugated polymer; a prerequisite for using these composites in organic electronic devices. We fabricated well dispersed nanotube/polymer composites by using functionalized carbon nanotubes and studied the effect of nanotubes addition on the photophysical properties of the technologically important conjugated polymer poly(3-hexylthiophene) (P3HT). Measurement of the photoluminescence efficiency of nanotubes/polymer composites showed that addition of 10wt% carbon nanotubes effectively quenched the polymer emission indicating close electronic interactions. This indicated that nanotubes/polymer composites have potential in organic photovoltaic or light-sensing devices. Further analysis of the steady-state photoluminescence spectra revealed that nanotube addition resulted in increased structural disorder in the polymer. The incorporation of structural disorder into the polymer with the addition of even a small amount of carbon nanotubes may be detrimental to charge transport. UV-vis adsorption studies revealed that one-dimensional templating of P3HT chains by nanotubes resulted in a red-shifted feature in the solutionstate optical adsorption spectra of P3HT. This suggested that presence of nanotube surface templates the polymer self-organisation to produce highly ordered coating of P3HT chains around the nanotube. In order to elucidate the nanoscale origin of this phenomenon, we performed detailed STM studies on individual nanotubes adsorbed with P3HT chains. Since carbon nanotubes can be considered as rolled up sheets of graphite, we also performed STM on P3HT chains assembly on graphite for comparison. For P3HT assembly on HOPG, we found that while 2D crystals were observed when P3HT was cast onto HOPG from dilute solution, a thicker and more disordered film resulted when cast from concentrated solutions and subsequent layers were more likely to align normal to an underlying monolayer of P3HT on the HOPG surface. STM studies of nanotube/polymer mixtures revealed that the P3HT chains are adsorbed on nanotubes surface in such a way that the thiophene and hexyl moieties of the polymer associated with the nanotube surface in identical manner to P3HT monolayer depositions on graphite. This resulted in the increased order as inferred from adsorption UV-Vis spectroscopy, where the polymer chains, which are otherwise prone to chain kinks and twists in solution, adopt a planar configuration when adsorbed onto the nanotube surface.
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Goh, Roland Ghim Siong. "Carbon nanotubes for organic electronics." Queensland University of Technology, 2008. http://eprints.qut.edu.au/20849/.
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This thesis investigated the use of carbon nanotubes as active components in solution processible organic semiconductor devices. We investigated the use of functionalized carbon nanotubes in carbon nanotubes network transistors (CNNFET) and in photoactive composites with conjugated polymers. For CNNFETs, the objective was to obtain detailed understanding of the dependence of transistor characteristics on nanotubes bundle sizes, device geometry and processing. Single walled carbon nanotubes were functionalized by grafting octadecylamine chains onto the tubes, which rendered them dispersible in organic solvents for solution processing. To investigate the dependence of electronic properties of carbon nanotubes networks on bundle size, we developed a centrifugal fractionation protocol that enabled us to obtain nanotube bundles of different diameters. The electronic properties of networks of nanotube bundles deposited from solution were investigated within a CNNFET device configuration. By comparing devices with different degree of bundling we elucidated the dependence of key device parameters (field effect mobility and on/off ratio) on bundle sizes. We further found that, in contrast to traditional inorganic transistors, the electronic properties of the CNNFETs were dominated by the channel rather than contact resistance. Specifically, the apparent mobility of our devices increased with decreasing channel length, suggesting that the charge transport properties of CNNFETs are bulk rather than contacts dominated. This meant that charge traps in the channel of the device had a significant effect on transport properties. We found that charge traps in the channel region introduced by adsorbed oxygen and silanol groups on the SiO2 surface were responsible for the dominant p-type conductance in as-fabricated devices. Based on this understanding, we demonstrated the p-type to n-type conversion of the transistor characteristics of CNNFETs by depositing nanotubes on electron-trapfree dielectric surfaces. Finally, by combining annealing and surface treatment, we fabricated CNNFETs with high n-type mobility of 6cm2/V.s. For polymer composites, the objective was to obtain detailed understanding of the interactions between carbon nanotubes and the conjugated polymer; a prerequisite for using these composites in organic electronic devices. We fabricated well dispersed nanotube/polymer composites by using functionalized carbon nanotubes and studied the effect of nanotubes addition on the photophysical properties of the technologically important conjugated polymer poly(3-hexylthiophene) (P3HT). Measurement of the photoluminescence efficiency of nanotubes/polymer composites showed that addition of 10wt% carbon nanotubes effectively quenched the polymer emission indicating close electronic interactions. This indicated that nanotubes/polymer composites have potential in organic photovoltaic or light-sensing devices. Further analysis of the steady-state photoluminescence spectra revealed that nanotube addition resulted in increased structural disorder in the polymer. The incorporation of structural disorder into the polymer with the addition of even a small amount of carbon nanotubes may be detrimental to charge transport. UV-vis adsorption studies revealed that one-dimensional templating of P3HT chains by nanotubes resulted in a red-shifted feature in the solutionstate optical adsorption spectra of P3HT. This suggested that presence of nanotube surface templates the polymer self-organisation to produce highly ordered coating of P3HT chains around the nanotube. In order to elucidate the nanoscale origin of this phenomenon, we performed detailed STM studies on individual nanotubes adsorbed with P3HT chains. Since carbon nanotubes can be considered as rolled up sheets of graphite, we also performed STM on P3HT chains assembly on graphite for comparison. For P3HT assembly on HOPG, we found that while 2D crystals were observed when P3HT was cast onto HOPG from dilute solution, a thicker and more disordered film resulted when cast from concentrated solutions and subsequent layers were more likely to align normal to an underlying monolayer of P3HT on the HOPG surface. STM studies of nanotube/polymer mixtures revealed that the P3HT chains are adsorbed on nanotubes surface in such a way that the thiophene and hexyl moieties of the polymer associated with the nanotube surface in identical manner to P3HT monolayer depositions on graphite. This resulted in the increased order as inferred from adsorption UV-Vis spectroscopy, where the polymer chains, which are otherwise prone to chain kinks and twists in solution, adopt a planar configuration when adsorbed onto the nanotube surface.
19
Chiu, Yu-Jui. "Wet Organic Field Effect Transistor as DNA sensor." Thesis, Linköping University, The Department of Physics, Chemistry and Biology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11761.
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Label-free detection of DNA has been successfully demonstrated on field effect transistor (FET) based devices. Since conducting organic materials was discovered and have attracted more and more research efforts by their profound advantages, this work will focus on utilizing an organic field effect transistor (OFET) as DNA sensor.
An OFET constructed with a transporting fluidic channel, WetOFET, forms a fluid-polymer (active layer) interface where the probe DNA can be introduced. DNA hybridization and non-hybridization after injecting target DNA and non-target DNA were monitored by transistor characteristics. The Hysteresis area of transfer curve increased after DNA hybridization which may be caused by the increasing electrostatic screening induced by the increasing negative charge from target DNA. The different morphology of coating surface could also influence the OFET response.
20
Sou, Antony. "Principles of organic field effect transistor circuit design." Thesis, University of Cambridge, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.708548.
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Mihăilă, Andrei-Petru. "Silicon carbide high power field effect transistor switches." Thesis, University of Cambridge, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.614951.
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Speer, Kevin M. "The Silicon Carbide Vacuum Field-Effect Transistor (VacFET)." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1301445427.
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Wiederspahn, H. Lee. "Quantum model of the modulation doped field effect transistor." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13355.
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Tian, Jing. "Theory, modelling and implementation of graphene field-effect transistor." Thesis, Queen Mary, University of London, 2017. http://qmro.qmul.ac.uk/xmlui/handle/123456789/31870.
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Two-dimensional materials with atomic thickness have attracted a lot of attention from researchers worldwide due to their excellent electronic and optical properties. As the silicon technology is approaching its limit, graphene with ultrahigh carrier mobility and ultralow resistivity shows the potential as channel material for novel high speed transistor beyond silicon. This thesis summarises my Ph.D. work including the theory and modelling of graphene field-effect transistors (GFETs) as well as their potential RF applications. The introduction and review of existing graphene transistors are presented. Multiscale modelling approaches for graphene devices are also introduced. A novel analytical GFET model based on the drift-diffusion transport theory is then developed for RF/microwave circuit analysis. Since the electrons and holes have different mobility variations against the channel potential in graphene, the ambipolar GFET cannot be modelled with constant carrier mobility. A new carrier mobility function, which enables the accurate modelling of the ambipolar property of GFET, is hence developed for this purpose. The new model takes into account the carrier mobility variation against the bias voltage as well as the mobility difference between electrons and holes. It is proved to be more accurate for the DC current calculation. The model has been written in Verilog-A language and can be import into commercial software such as Keysight ADS for circuit simulation. In addition, based on the proposed model two GFET non-Foster circuits (NFCs) are conducted. As a negative impedance element, NFCs find their applications in impedance matching of electrically small antennas and bandwidth improvement of metasurfaces. One of the NFCs studied in this thesis is based on the Linvill's technique in which a pair of identical GFETs is used while the other circuit utilises the negative resistance of a single GFET. The stability analysis of NFCs is also presented. Finally, a high impedance surface loaded with proposed NFCs is also studied, demonstrating significant bandwidth enhancement.
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Liu, Shiyi. "Understanding Doped Organic Field-Effect Transistors." Kent State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=kent1574127009556301.
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Huang, Shih-yuan, and 黃士源. "Design of 100-nm Tunneling Field-Effect Transistor." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/t32z96.
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碩士國立臺灣科技大學
電子工程系
99
In the progress of the electronics industry, the scaled down of the conventional MOSFET device will emerge some reliability problems, such as short-channel effect, hot-carrier effect, and gate-induced-drain leakage (GIDL). Tunneling field effect transistor (TFET) has the immunity from these problems in high scaling fabrication due to its operation mechanism is different from the MOSFET device. So far, some issues of TFET are still need to be resolved. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. In this study, there are two newly designed TFET structures. They are “TFET with LDS (lightly doped Source) structure” and “Modified TFET structure” with n+ doping in Source. From the simulation results, the newly designed TFET structures do have better performance than the conventional TFET. For example, they have higher on current or lower off current. Since TFET has fewer reliability problems than the conventional MOSFET device in high scaling fabrication, and TFET also has the structural similarity as MOSFET. So, the TFET can be thought of as a promising alternative to the MOSFET in the future.
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Lee, Ming-Shih, and 李明師. "Technology Development of Novel Naonwire Tunneling Field-Effect Transistor." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/48487529732558268290.
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碩士國立中央大學
電機工程研究所
99
This thesis integrated one dimension poly-Si nanowire and PIN structure into a device, which fabricated nanowire tunneling field-effect transistor (NWT-FET). We are looking forward to improving short channel effects (SCE), subthreshold slope, (S.S.) and static leakage current (IOFF) in the metal oxide semiconductor field-effect transistor (MOS-FET). The key process of NWT-FET is described as follows: By using etched back technique, we can form one dimension poly-Si nanowire on steep mesa-sidewall. Then by using two photolithography processes, we can implant P+ and N+ on one dimension poly-Si nanowire, respectively, to form the PIN structure. Via the variable temperature measurement (300 K, 250 K, 200 K and 150 K), we experimental characterized the current-voltage (I-V), subthreshold slope-temperature (S.S.-Temp.) and on current-temperature (Ion-Temp.).
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Lai, Guan-Fu, and 賴冠甫. "Design of Nanoscale Lateral Trench-Type Tunneling Field-Effect Transistor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/28823414545853161968.
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碩士國立臺灣科技大學
電子工程系
103
In the progress of the electronics industry, the scaled down of the conventional MOSFET device will emerge some reliability problems, such as short-channel effect, hot-carrier effect, and gate-induced-drain leakage (GIDL). Tunneling Field Effect transistors (TFETs) are semiconductor devices that carry current via inter-band source-to- channel tunneling rather than by carrier transport over the source barrier. In other words, TFET has the immunity from these problems in high scaling fabrication due to its operation mechanism is different from the MOSFET device. Although tunneling-field effect transistors (TFETs) can improve disadvantages of conventional MOSTFT and become very promising candidates for future low power applications, some problems of TFET are still needed to be resolved such as very low on-state current compared to the conventional MOSFETs. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. In this study, there is a newly designed TFET structure called“the trench TFET with n-pocket”. For nanoscale devices, as compared to the planar TFET, the trench TFET with n-pocket can lead to a much smaller off-state current but comparable on-state current, due to the corner effect. Consequently, the trench TFET with n-pocket can be promising for nanoscale integrated-circuit devices.
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Hu, Pei-sheng, and 胡倍慎. "Study of Tunneling Field Effect Transistors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/d53z7c.
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碩士國立臺灣科技大學
電子工程系
95
As MOS devices are scaled down to the deep-submicron process, new reliability problems emerge. These include short-channel effect, hot-carrier effects, and gate-induced-drain leakage (GIDL). The tunneling field effect transistor (TFET) provides less short-channel effect, little hot-carrier effect, and little GIDL in high scaling fabrication. A band to band tunneling field effect transistor consists of n+-drain (source) and p+-source (drain). The electron-hole pairs are generated by band to band tunneling. So far, some issues of TFET are still need to be resolved. In this study, further study of various device parameters for obtaining high-performance TFET is carried out via process and device simulation. This simulation was investigated with various parameters for obtaining high-performance TFET. These parameters include channel length (with various sidewall spacer length), substrate thickness, substrate doping concentration, gate oxide thickness, various drain biases, and substrate materials. The performance of device is really improved by some parameters. For example, the on-current is increased by use of single crystalline SiGe substrate and off-current is reduced by a smaller drain biases. On the other hand, certain simulation indicates off-current is reduced and on-current is increased by certain ion-implantation profile and location. Since there are not too many additional process steps compare with MOSFET, the TFET is an advancing device for low-power mobile applications fabricated with the standard CMOS process flow.
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Nah, Junghyo 1978. "High performance germanium nanowire field-effect transistors and tunneling field-effect transistors." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2268.
Full textAbstract:
The scaling of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) has continued for over four decades, providing device performance gains and considerable economic benefits. However, continuing this scaling trend is being impeded by the increase in dissipated power. Considering the exponential increase of the number of transistors per unit area in high speed processors, the power dissipation has now become the major challenge for device scaling, and has led to tremendous research activity to mitigate this issue, and thereby extend device scaling limits. In such efforts, non-planar device structures, high mobility channel materials, and devices operating under different physics have been extensively investigated. Non-planar device geometries reduce short-channel effects by enhancing the electrostatic control over the channel. The devices using high mobility channel materials such as germanium (Ge), SiGe, and III-V can outperform Si MOSFETs in terms of switching speed. Tunneling field-effect transistors use interband tunneling of carriers rather than thermal emission, and can potentially realize low power devices by achieving subthreshold swings below the thermal limit of 60 mV/dec at room temperature. In this work, we examine two device options which can potentially provide high switching speed combined with reduced power, namely germanium nanowire (NW) field-effect transistors (FETs) and tunneling field-effect transistors (TFETs). The devices use germanium (Ge) – silicon-germanium (Si[subscript x]Ge[subscript 1-x]) core-shell nanowires (NWs) as channel material for the realization of the devices, synthesized using a 'bottom-up' growth process. The device design and material choice are motivated by enhanced electrostatic control in the cylindrical geometry, high hole mobility, and lower bandgap by comparison to Si. We employ low energy ion implantation of boron and phosphorous to realize highly doped contact regions, which in turn provide efficient carrier injection. Our Ge-Si[subscript x]Ge[subscript 1-x] core-shell NW FETs and NW TFETs were fabricated using a conventional CMOS process and their electrical properties were systematically characterized. In addition, TCAD (Technology computer-aided design) simulation is also employed for the analysis of the devices.text
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Juang, He-Kai, and 莊賀凱. "Fabrication and Analysis of Silicon-Based Vertical-Type Tunneling Field-Effect Transistor." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/78454520049893103686.
Full textAbstract:
碩士國立臺灣師範大學
光電科技研究所
103
Recently, a transistor with tunneling mechanism called Tunnel FET was proposed as the candidate of MOSFET. Compared to MOSFET, TFET has several advantages: (1)TFET is suitable for low power device due to the higher barrier of the reversed p-i-n junction in TFET. (2)The band-to-band tunneling region is about 10nm, so that the transistor can be shrunk down to 20nm gate length. (3)The subthreshold swing of TFET has ability to surmount 60mV/dec of MOSFET’s physical limit by its distinct working principle. (4)The threshold voltage of TFET depends on bending in the small region, but not in the whole channel region, Vt roll-off is much smaller than that of MOSFET while scaling. The major challenge of TFET is the boosting of on current. In this paper, we design a device with vertical tunneling structure for investigating how to enhance the on current of TFET. The analytic results show that we can find two parts of boosting current, the second boosting current is caused by vertical tunneling, we have proved it by band gap diagram of simulation. And the best source concentration is about 1x1019~1x1020cm-3. It can be adjusted to have appropriate threshold voltage and better subthreshold swing in this region. At the same time, we investigate the issue of fabrication by simulation. It shows that the major issue affecting our performance of device is the quality of gate oxide.The bad gate oxide induces trap assist tunneling, then the current of gate will directly tunnel through the gate oxide, and that’s where the leakage current come from.
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Rezanezhad, Gatabi Iman. "Tunnel MOS Heterostructure Field Effect Transistor for RF Switching Applications." Thesis, 2013. http://hdl.handle.net/1969.1/151047.
Full textAbstract:
GaN RF switches are widely used in today’s communication systems. With digital communications getting more and more popular nowadays, the need for improving the performance of involved RF switches is inevitable. Designing low ON-state resistance GaN switches are exceedingly important to improve the switch insertion loss, isolation and power loss. Moreover, considerations need to be taken into account to improve the switching speed of the involved GaN HEMTs.
In this dissertation, a new GaN HEMT structure called “Tunnel MOS Heterostructure FET (TMOSHFET)” is introduced which has lower ON-state resistance and faster switching speed compared to conventional AlGaN/GaN HEMTs. In the switch ON process, the channel of this device is charged up by electron tunneling from a layer underneath the channel as opposed to typical AlGaN/GaN HEMTs in which electron injection from the source is charging up the channel. The tunneling nature of this process together with the shorter travel distance of electrons in TMOSHFET provide for a faster switching speed.
In order to understand the tunneling mechanisms in TMOSHFET, the fabrication of AlGaN/GaN Schottky Barrier Diodes (SBDs) with various AlGaN thicknesses is demonstrated on Si (111) substrate. The impacts of SF6 dry etching on the trap density and trap state energy of AlGaN surface are investigated using the GP/w- w method. Various tunneling mechanisms at different biases are then characterized in samples and compared with each other.
To improve the source and drain resistances in TMOSHFET, a model is generated to optimize the 2DEG density and electric field in AlGaN/GaN heterostructure based on Al mole fraction, AlGaN thickness and the thickness of SiN passivation layer and it is experimentally verified by non-contact Hall 2DEG density measurements. The spontaneous and piezoelectric polarizations together with strain relaxation have been implemented into the model, taking into account the annealing effects. From the experimental data on obtained parameters, the operation and device parameterization of the TMOSHFET is outlined and design considerations to improve the device R_(ON)-V_(BR) figure of merit are discussed.
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Chang, Kuan-Yu, and 張貫宇. "Performance Enhancement of Tunneling Field Effect Transistor by a New Current Enhancing Scheme." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/84730787605065691292.
Full text
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Lee, Ya-Jui, and 李亞叡. "Investigation of electrical characteristics for multi gate tunneling-carbon nanotube field effect transistor." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96155269652851592356.
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Lin, Hsin-Yi, and 林欣逸. "Study of Fin-shaped Nanowires Tunneling-Field-Effect-Transistor Charge Trapping Nonvolatile Memory." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/21574027888647336316.
Full textAbstract:
碩士國立清華大學
工程與系統科學系
101
The Pi-gate polycrystalline silicon (poly-Si) nanowires tunneling field effect transistor (TFET) charge trapping(CT) nonvolatile memory (NVM) with all programming mechanisms and shows a large memory window and good reliability is demonstrated for the first time. Pi-gate nanowires structure performs faster program/erase speed. Otherwise, the SONOS-type structure can improve excellent reliability. Furthermore, due to the poly-Si channel technology, it is possible to develop in 3D high-density stacked NVM. In FN tunneling programming, operation of conducting current and program/erase are based on all quantum tunneling transportation. Pi-gate T-SONOS NVM generates a large memory window (ΔVth=4.75V at Vg = 17V, tp = 1ms) and excellent reliability of 88 % endurance behavior after 10k P/E cycles and 65 % retained ability for ten years at 85 oC. In CHE programming, Pi-gate T-SONOS NVM presents a large memory window (ΔVth=4V at Vg=8V, Vd=6V, tp=1ms), and 74 % endurance behavior after 10k P/E cycles. Moreover, a superior 81 % retention behavior for ten years at 85 oC is presented. In BBHE programming, Pi-gate T-SONOS NVM performs a high programming efficiency, larger memory window (ΔVth=4V at Vg=3V, Vs=-6V, tp=1ms), excellent reliability of 74 % endurance after 10k P/E cycles and 63 % retention for ten years at 85 oC can be achieved. Based on above-mentioned description, Pi-gate nanowires T-SONOS NVM is suitable to use in future 3D high-density embedded portable applications with low stand-by power consumption and ultra low program voltage.
36
Lin, Yang-You, and 林揚祐. "Lateral trench-type insulated-gate bipolar transistor triggered by using tunneling-field-effect structure." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/52173970303839533036.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
103
The lateral insulated-gate bipolar transistor power device has been proposed that a smaller on-state voltage drop compared with metal-oxide-semiconductor field-effect transistor power device and tunneling-field-effect transistor power device. Because the P+-anode/N- drift junction of the device turn on, the large series resistance in the drift region can be effectively reduced. In this thesis, the results of different gate-positions of planar TFET-IGBT have been discussed, there is a trade-off between the electric field in P+-cathode/N- drift junction and N- drift region. Furthermore, planar TFET-IGBT with removal of P-well and ion implant to form n-pocket can significantly enhance the band-to-band tunneling near the P+-cathode/N- drift junction, and the on-current of the device would be obviously increased. Nevertheless, a large electric field in the depletion region of P+-cathode/N- drift junction would result in breakdown voltage degradation. Therefore, the optimization of the characteristics of planar TFET-IGBT requires a trade-off between forward current and reverse blocking voltage. For improving the blocking voltage of the device, trench-type TFET-IGBT be studied with better breakdown characteristic. It is found that the usage of n-pocket can enhance the electric field of trench-type TFET-IGBT not only near the P+-cathode/N- drift junction but also in N- drift region. As a result, the on-state capability and blocking voltage characteristic of trench-type TFET-IGBT can be obviously improved compared with those of MOS-IGBT.
37
Lin, Yi-Hsien, and 林宜憲. "Design of Complementary Tilt-Gate Tunneling Field Effect Transistor for Ultra-Low-Power Applications." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/ekc467.
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Kang, Ting Shiuan, and 康庭絢. "Metal Source Tunnel Field-Effect Transistors with Tunneling Dielectrics." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/14876822607226420399.
Full textAbstract:
碩士國立清華大學
電子工程研究所
103
Tunnel field-effect transistor (TFET) is considered as an attractive candidate for future low-power applications because of its steep subthreshold slope. However, conventional TFET transistor suffers from a low on-state current. This thesis proposes a new metal source TFET to increase the on-state current by combining the band-to-band tunneling and Schottky barrier tunneling. Two-dimensional simulations with nonlocal models were performed to examine the physical mechanism and associated design. The results show that an additional tunneling dielectric between the source and the channel can be utilized along with the metal source to ensure a high on-state current while retaining an abrupt on-off switching of TFET devices.
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Ramesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. https://etd.iisc.ac.in/handle/2005/792.
Full textAbstract:
The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries.
Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.
40
Ramesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. http://hdl.handle.net/2005/792.
Full textAbstract:
The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries.
Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.
41
Liu, Ping-Jung, and 劉秉融. "Study of Tunneling-Field-Effect Poly-Si Thin-Film-Transistors." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/4awym3.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
99
In the progress of the electronics industry, the scale down of conventional metal oxide semiconductor thin film transistor (MOSFET) will emerge some reliability problems, such as short-channel effect, hot- carrier effect and drain-induce barrier lowering (GIDL). When scale down of tunneling-field-effect transistor, it can make lower short-channel effect, hot-carrier effect and drain-induce barrier lowering. It can solve the reliability problems that it is scaled down. Although tunneling-field effect transistor (TFET) can improve disadvantages of conventional MOSTFT, some issues of TFET are still need to be resolved. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. Above this new device structure, a counter-doping pocket region enclosing the source region is formed. The performance of device is really improved by changing different dose and energy. From the simulation results, the newly designed TFET structures do have better performance than the conventional TFET. TFET improves the leakage current problem of conventional MOSTFT that is produced in high scaling fabrication. Since there are not too many additional process steps compare with MOSFET, the new designed of TFET is an advancing device instead of MOSTFT in the future.
42
Wang, Yu-Long, and 王裕隆. "Improving electrical characteristics of Fin-shaped Tunneling-Field-Effect-Transistor using Microwave dopant activation and Asymmetry structure." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/45990305348300769134.
Full textAbstract:
碩士國立清華大學
工程與系統科學系
101
The market demand for portable electric equipment increase dramatically year by year. Although transistors develop toward low cost and high density, maintaining device characteristics becomes difficult due to the device fabrication and physics limitations of the device. Designing a device that different from conventional MOSFET is a necessary way. This thesis based on Fin-shaped Tunneling Transistor which operated by quantum tunneling mechanism. Thus, compared with conventional MOSFET operated by drift mechanism, the Tunneling Transistor can achieve fast on/off characteristic. By the Fin-shaped structure, it can affect the active layer electric potential distribution by multi-direction, increasing the gate control ability and enhance the characteristics. Above the discussion, the Fin-shaped tunneling transistor is a device with high-efficiency and good transfer characteristic. In this thesis, we focus on demonstrate that microwave dopant activation technique can help TFETs to form an abrupt tunneling junction. Subthreshold slope and driving current can be greatly enhanced by microwave annealing as the dopant activation method compare to traditional rapid thermal annealing. An interesting phenomenon of negative differential conductance in the output characteristic was observed, which is attributed to hot-carrier effect at the high gate overdrive operation. A positive temperature dependence of transfer characteristic is also observed, which is related to the bandgap narrowing effect and the enhancement of the thermionic field emissions of the grain boundary states. Finally, with the geometric difference between source and drain, we demonstrate a device with high on-state current and low off-state current, simultaneously. This work shows experimental data for device’s reliability; all the data can display Fin-shaped tunneling transistor has applied to high value actually, it would become the next-generation device.
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Hsu, Ching-Yi, and 徐慶議. "Optimization of Vertical InAs/GaSb Hetero-Junction Tunneling Field-Effect Transistors." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/nq64s2.
Full textAbstract:
博士國立交通大學
電子研究所
105
The semiconductors technology has entered 10 nanometers generation node by 2016. In the near future, the semiconductors technology will reach 7/5 nanometers generation or even move toward the 3 dimensional stacking. However, accompanying the increase of device density, the heat dissipation of the IC chip becomes a major issue. Hence the reduction of the supply voltage and suppressing the leakage current are important for sustaining the Moore’s law in the future. Meanwhile, the scaling of the transistors dimension requires the transistors to maintain the low subthreshold slope and the high ION/IOFF under low supplied voltage. Recently, several MOSFETs architectures had been proposed to push the switching characteristics close to their thermionic emission physical limitation (60 mV/dec), like finFETs and nanowire FETs. At present, finFET technology has already been applied to the advanced IC fabrication in industry. Recently, several novel transistor concepts have been proposed to further suppress the subthreshold swing to lower than 60 mV/dec, like tunneling FETs, negative capacitance FET and nano-mechanical switching. The switching mechanism of the tunneling FET is the gate-controlled band to band tunneling between source and channel. The tunneling FETs can result in very sharp switching characteristics. The tunneling barrier in tunneling FETs can cause a very low on-current level, hence the narrow bandgap materials and hetero-junction materials have been proposed as channel materials to decrease the tunneling barrier and to enhance the on-current level of tunneling FETs. Using InAs/GaSb hetero-junction with type-III near to type-II hetero-junction, a very small tunneling barrier can be achieved by modulation of the device structure. A recent study indicates that the on-current level of InAs/GaSb double gate tunneling FET can reach 752 mA/mm. Gate electrical field of vertical tunneling FETs is parallel to tunneling direction, and vertical to tunneling junction, which leads to a very good tunneling junction control. With InAs/GaSb hetero-junction, the on-current of tunneling FETs can be much improved. This dissertation will focus on the fabrication, electrical characteristics and simulation of the vertical InAs/AlSb/GaSb tunneling FETs. The insertion of AlSb layer can result in adjustable band offset between InAs/GaSb and the on-current and switching characteristics can be further improved. Experimental results show that the device has 22 µA/µm2 on-current density at VDS = 0.4 V and VGS = 0.4 V, 194 mV/decade subthreshold swing (SS) at VDS = 0.1 V with an Ion/Ioff > 10^3. This study also investigates the impact of lateral etching depth to the device performance. In addition to the transistors characteristics, we also develop the physical model to demonstrate the multi-peak negative differential resistance phenomena which were observed in the forward bias region. TCAD Sentaurus simulation is also performed in this study to optimize the vertical InAs/GaSb tunneling FETs design. It is found that some factors can degrade the switching characteristics of the vertical InAs/GaSb tunneling FET due to the tunneling onset voltage non-uniformity: (1) Fermi pinning at the exposed InAs surface makes the Fermi level pin at close to or even higher than conduction band of InAs, (2) Geometry of L-shape leads to the non-uniformity of gate to channel coupling over the junction. For the inherent coupling non-uniformity issue, the developed model suggests that the tunneling onset voltage non-uniformity can be eliminated by (1) band offset modulation and (2) coupling ratio matching. On the other hand, for the Fermi-pinning induced switching characteristics degradation, the use of dual-metal gate structure can suppress the issue.
44
Hsu, Chia-wei, and 許家偉. "Channel Engineering of Tunneling-Field-Effect Poly-Si Thin-Film Transistors." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/71581049138535731102.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
101
In the progress of the electronics industry, the scale down of conventional metal oxide semiconductor thin film transistor (MOSFET) will emerge some reliability problems, such as short-channel effect, hot- carrier effect, drain-induce barrier lowering (DIBL) and gate-induced drain leakage (GIDL). However, the scale down of tunneling-field-effect transistor would not encounter the above issues. Although tunneling-field effect transistor (TFET) can improve disadvantages of conventional MOSTFT, some problems of TFET are still needed to be resolved. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. The poly-SiC has a larger energy band gap than the poly-Si. Hence, the stacked poly-Si/poly-SiC channel layer can lead to a larger on-state current than the single poly-Si channel layer, due to higher electric field at source region. On the other hand, the poly-SiGe has a smaller energy band gap than the poly-Si. Hence, the stacked poly-Si/poly-SiGe channel layer can show a larger current than the single poly-Si channel layer, whereas the stacked poly-Si/poly-SiGe channel layer would show a smaller off-state current than the single poly-SiGe channel layer.
45
Chen, Jin-Yang, and 陳妗仰. "Design and Simulation of P-channel InGaAs/GaAsSb Staggered Hetero-Junction Tunneling Field-Effect Transistors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/pgn936.
Full textAbstract:
碩士國立中央大學
電機工程學系
106
With the progress of semiconductor science and technology, the number of metal-oxide-semiconductor field-effect transistors (MOSFETs) in integrated circuits continuely increases over the last 50 years following Moore’s Law. The rapidly increasing power consumption associated with transistor density becomes one of the major bottlenecks in the development of future integrated circuits. An intuitive approach to this problem is to lower the operation voltage and threshold voltage simultaneously. Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing (S.S.) is limited to 60 mV/decade or higher at room temperature. Whereas, tunneling field-effect transistors (TFETs) is considered as a promising candidate device for low voltage and low power integrated circuits, which is based on band-to-band tunneling (BTBT) to generate current that can break through the limit of S.S. (60 mV/decade). In III-V compound semiconductors, InGaAs/GaAsSb material system allows us to modulate band lineups by changing their compositions to form staggered type heterojunction TFETs. In this study, pTFETs based on this material system is investigated using Synopsys Sentaurus TCAD tool. The effects of band alignment, doping concentration, gate position and traps at III-V/oxide interface on the electrical properties of InGaAs/GaAsSb TFETs are systematically studied. Simulation results show that there is a strong correlation between tunneling barrier (Ebeff) with on/off-currents (ION and IOFF). Higher Ebeff leads to lower ION and IOFF, while the lower Ebeff results in higher ION and IOFF. To reach high ION and low IOFF, In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer is proposed to reduce Ebeff from 0.63 eV to 0.38 eV at the source/channel junction, which leads to an ION current equal to 24 μA/μm at VDS = - 0.3 V，VGS = - 0.5 V, while IOFF remains at 4×10-11 μA/μm at VGS = 0 V, simultaneously. To improve the device performance further and increase the switching speed, a low IOFF of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET combination with a high ION of InAs/GaAs0.1Sb0.9 insertion layer is proposed. Based on this design, ION can be further enhanced to 86 μA/μm and the threshold voltage can be reduced to - 40 mV. The effects of strain introduced by lattice mismatch between GaAsSb and In0.53Ga0.47As on the device performance are also studied. A 2 % compressive strain makes ION increase to 28 μA/μm, which is equal to the ION of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer, and its IOFF also remains at 10-11 μA/μm.
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Hung, Che-wei, and 洪哲緯. "Study of P-I Interface Band Structures across GaAsSb/In(Al)As Tunneling Field Effect Transistors." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/29541421134599915027.
Full textAbstract:
碩士國立中山大學
物理學系研究所
103
Recently, tunnel field-effect transistor (TFET) is one of the most promising candidates of metal-oxide-semiconductor field-effect transistors (MOSFET) because of the advantage of low operating voltage. The ultra-low power TFET can be achieved by adjusting materials of the source terminal and the channel to control the band gap. The working principle of TFET is that the shift of the energy band caused by applying voltage makes the valence band of the source and conduction band of the channel cross at the interface, and thus the device will be switched on by the band to band tunneling. That’s the reason why the study of the band structure of P-type/Intrinsic interface is so important. In this work, the electronic structures across P-type/Intrinsic hetero-interface of tunnel field-effect transistor have been observed by cross-sectional scanning tunneling microscopy spectroscopy locally and directly, and the band alignment of P-type/Intrinsic interface can be drawn according to its electronic structures. The experimental result shows the band structure of P-type/Intrinsic hetero-interface of TFET, and the tunneling barrier height which has an effect on the degree of consuming energy of the device.
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Wu, Zhi-Cheng, and 吳治成. "Bandgap Engineering for Normally-off GaAsSb/InGaAs Hetero-junction Tunneling Field-Effect Transistors with High On-state Current." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/31815109273558924388.
Full textAbstract:
碩士國立中央大學
電機工程學系
104
Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing is limited to 60 mV/decade or higher at room temperature. Whereas, tunnel field-effect transistors (TFETs), whose current conduction is based on quantum mechanical band-to-band tunneling mechanism that gives a sub-60 mV/decade subthreshold slope, have been considered a promising energy-efficient device for low voltage and low power circuits. Since the inception of this proposal, TFETs based on Si/Ge material system have been demonstrated by a few groups. However, the devices are limited by either a low on-current or a high off-current due to the unfavored bandgap and band alignment of Si/Ge. Attention is then switched to narrow bandgap III-V compounds as the aforementioned issues could be solved by band gap engineering. This study is focused on III-V TFETs, aiming at the design and analysis of a normally-off TFET with high-on current. It covers the setup of a physical model in the TCAD tool, the effects of band alignments, gate position, and doping concentration on the electrical properties of the type-II band lineup GaAsxSb1-x/InyGa1-yAs heterojunction TFETs. Our simulation indicate that although GaAsxSb1-x/InyGa1-yAs TFETs could be designed to have a small Ebeff at the hetero-interface for high-on current, their high off-state current manifest themselves unacceptable for practical use. To solve this issue, a GaAs0.51Sb0.49/InAs/In0.53Ga0.47As TFET with an InAs quantum well (QW) is proposed to reduce the Ebeff from 0.5 eV to 0.1 eV at the source/channel interface, leading to an on-state current increasing from 27 A/m to 89 A/m at VGS=VDS=0.5 V, while the IOFF still maintains on the order of 10-7 μA/μm at VGS=0 V, simultaneously. To improve the device performance further and increase noise immunity at the gate, a graded InGaAs QW is designed to replace the InAs QW in the GaAs0.51Sb0.49/In0.53Ga0.47As TFET above. On this design, a normally-off TFET with high on-state current and threshold voltage greater than 50 mV has been achieved.
48
Brahma, Madhuchhanda. "Multiscale Modeling of Quantum Transport in 2D Material Based MoS Transistors." Thesis, 2019. https://etd.iisc.ac.in/handle/2005/5133.
Full textAbstract:
Atomically thin 2D materials have ushered in a new era in the fi eld of nano-science and tech-
nology and have been translated to notable advancements in the design of sensors, optoelectronic
devices, exible electronics. These atomically thin materials are predicted to replace conven-
tional bulk materials, Si and Ge, for transistor channels and extend the complementary metal
oxide semiconductor technology road-map beyond the deca-nanometer regime. Constant efforts
are being made to fabricate devices based on some of the recently discovered van der Waal's
materials such as graphene, hexagonal boron nitride, MoS2, phosphorene. Apart from these, a
large number of novel 2D materials and their derivatives are being constantly explored through
both experiments and density functional theory analysis. In order to narrow down the mate-
rial and design selection space for time- and cost-heavy experimental device fabrication, atomic
level density functional theory (DFT) calculations need to be coupled with device-level physics
models. Thus, we propose a multiscale computational framework bridging first principles based
DFT calculations with device physics simulations. Under this framework, we start with crys-
tallographic information of a 2D material and perform DFT simulations to extract important
electronic parameters, such as effective mass, band gap, real and complex band dispersion, and
phonon spectrum. This is followed by construction of the material hamiltonian based on the
DFT extracted parameters. Next, the hamiltonian is used to perform self-consistent solution
of the Schrodinger and the Poisson's equations through the non-equilibrium Green's function
approach in order to describe the complex, spatially heterogeneous intrinsic carrier transport
and resulting device performance in both ballistic and dissipative regimes. Modeling studies
on three devices: (i) monolayer germanane metal oxide semiconductor fi eld effect transistors
(MOSFETs), (ii) monolayer GeSe based tunneling field effect transistor (TFET), and (iii)
phosphorene based MOSFET and TFET, will be presented in the thesis and their design and
performance limits will be evaluated to guide future material selection and device fabrication.
49
Fahad, Hossain M. "3D NANOTUBE FIELD EFFECT TRANSISTORS FOR HYBRID HIGH-PERFORMANCE AND LOW-POWER OPERATION WITH HIGH CHIP-AREA EFFICIENCY." Diss., 2014. http://hdl.handle.net/10754/313701.
Full textAbstract:
Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environment and a sustainable future, the demand for faster and more computationally efficient electronics will continue to rise. Keeping up with this demand requires extensive innovation at the transistor level, which is at the core of all electronics. Up until recently, classical silicon transistor technology has traditionally been weary of disruptive innovation. But with the aggressive scaling trend, there has been two dramatic changes to the transistor landscape. The first was the re-introduction of metal/high-K gate stacks with strain engineering in the 45 nm technology node, which enabled further scaling on silicon to smaller nodes by alleviating the problem of gate leakage and improving the channel mobility. The second innovation was the use of non-planar 3D silicon fins as opposed to classical planar architectures for stronger electrostatic control leading to significantly lower off-state leakage and other short-channel effects. Both these innovations have prolonged the life of silicon based electronics by at least another 1-2 decades. The next generation 14 nm technology node will utilize silicon fin channels that have gate lengths of 14 nm and fin thicknesses of 7 nm. These dimensions are almost at the extreme end of current lithographic capabilities. Moreover, as fins become smaller, the parasitic capacitances and resistances increase significantly resulting in degraded performance. It is of popular consensus that the next evolutionary step in transistor technology is in the form of gate-all-around silicon nanowires (GAA NWFETs), which offer the tightest electrostatic configuration leading to the lowest possible leakage and short channel characteristics in over-the-barrier type devices. However, to keep scaling on silicon, the amount of current generated per device has to be increased while keeping short channel effects and off-state leakage at bay.
The objective of this doctoral thesis is the investigation of an innovative vertical silicon based architecture called the silicon nanotube field effect transistor (Si NTFET). This topology incorporates a dual inner/outer core/shell gate stack strategy to control the volume inversion properties in a hollow silicon 1D quasi-nanotube under a tight electrostatic configuration. Together with vertically aligned source and drain, the Si NTFET is capable of very high on-state performance (drive current) in an area-efficient configuration as opposed to arrays of gate-all-around nanowires, while maintaining leakage characteristics similar to a single nanowire. Such a device architecture offsets the need of device arraying that is needed with fin and nanowire architectures. Extensive simulations are used to validate the potential benefits of Si NTFETs over GAA NWFETs on a variety of platforms such as conventional MOSFETs, tunnel FETs, junction-less FETs. This thesis demonstrates a novel CMOS compatible process flow to fabricate vertical nanotube transistors that offer a variety of advantages such as lithography-independent gate length definition, integration of epitaxially grown silicon nanotubes with spacer based gate dielectrics and abrupt in-situ doped source/drain junctions. Experimental measurement data will showcase the various materials and processing challenges in fabricating these devices. Finally, an extension of this work to topologically transformed wavy channel FinFETs is also demonstrated keeping in line with the theme of area efficient high-performance electronics.
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Nadimi, Ebrahim. "Quantum Mechanical and Atomic Level ab initio Calculation of Electron Transport through Ultrathin Gate Dielectrics of Metal-Oxide-Semiconductor Field Effect Transistors." Doctoral thesis, 2007. https://monarch.qucosa.de/id/qucosa%3A18893.
Full textAbstract:
The low dimensions of the state-of-the-art nanoscale transistors exhibit increasing
quantum mechanical effects, which are no longer negligible. Gate tunneling current is
one of such effects, that is responsible for high power consumption and high working
temperature in microprocessors. This in turn put limits on further down scaling of
devices. Therefore modeling and calculation of tunneling current is of a great interest.
This work provides a review of existing models for the calculation of the gate
tunneling current in MOSFETs. The quantum mechanical effects are studied with a
model, based on a self-consistent solution of the Schrödinger and Poisson equations
within the effective mass approximation. The calculation of the tunneling current is
focused on models based on the calculation of carrier’s lifetime on quasi-bound states
(QBSs). A new method for the determination of carrier’s lifetime is suggested and then
the tunneling current is calculated for different samples and compared to measurements.
The model is also applied to the extraction of the “tunneling effective mass” of electrons
in ultrathin oxynitride gate dielectrics.
Ultrathin gate dielectrics (tox<2 nm) consist of only few atomic layers. Therefore,
atomic scale deformations at interfaces and within the dielectric could have great
influences on the performance of the dielectric layer and consequently on the tunneling
current. On the other hand the specific material parameters would be changed due to
atomic level deformations at interfaces. A combination of DFT and NEGF formalisms
has been applied to the tunneling problem in the second part of this work. Such atomic
level ab initio models take atomic level distortions automatically into account. An atomic
scale model interface for the Si/SiO2 interface has been constructed and the tunneling
currents through Si/SiO2/Si stack structures are calculated. The influence of single and
double oxygen vacancies on the tunneling current is investigated. Atomic level
distortions caused by a tensile or compression strains on SiO2 layer as well as their
influence on the tunneling current are also investigated.Die vorliegende Arbeit beschäftigt sich mit der Berechnung von Tunnelströmen in MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Zu diesem Zweck wurde ein quantenmechanisches Modell, das auf der selbstkonsistenten Lösung der Schrödinger- und Poisson-Gleichungen basiert, entwickelt. Die Gleichungen sind im Rahmen der EMA gelöst worden. Die Lösung der Schrödinger-Gleichung unter offenen Randbedingungen führt zur Berechnung von Ladungsverteilung und Lebensdauer der Ladungsträger in den QBSs. Der Tunnelstrom wurde dann aus diesen Informationen ermittelt. Der Tunnelstrom wurde in verschiedenen Proben mit unterschiedlichen Oxynitrid Gatedielektrika berechnet und mit gemessenen Daten verglichen. Der Vergleich zeigte, dass die effektive Masse sich sowohl mit der Schichtdicke als auch mit dem Stickstoffgehalt ändert. Im zweiten Teil der vorliegenden Arbeit wurde ein atomistisches Modell zur Berechnung des Tunnelstroms verwendet, welche auf der DFT und NEGF basiert. Zuerst wurde ein atomistisches Modell für ein Si/SiO2-Schichtsystem konstruiert. Dann wurde der Tunnelstrom für verschiedene Si/SiO2/Si-Schichtsysteme berechnet. Das Modell ermöglicht die Untersuchung atom-skaliger Verzerrungen und ihren Einfluss auf den Tunnelstrom. Außerdem wurde der Einfluss einer einzelnen und zwei unterschiedlich positionierter neutraler Sauerstoffleerstellen auf den Tunnelstrom berechnet. Zug- und Druckspannungen auf SiO2 führen zur Deformationen in den chemischen Bindungen und ändern den Tunnelstrom. Auch solche Einflüsse sind anhand des atomistischen Modells berechnet worden.