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Journal articles on the topic 'Tunable bandpass delta sigma ADC'

Author: Grafiati
Published: 25 May 2024

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1

Cardelli, L., L. Fanucci, V. Kempe, F. Mannozzi, and D. Strle. "Tunable bandpass sigma delta modulator using one input parameter." Electronics Letters 39, no. 2 (2003): 187. http://dx.doi.org/10.1049/el:20030146.

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2

Kim, Jae-Bung, Nam-Hee Yoo, and Seong-Ik Cho. "Tunable Bandpass 4th Order SC Sigma-delta Modulator with Novel Structure." Transactions of The Korean Institute of Electrical Engineers 60, no. 2 (February 1, 2011): 446–50. http://dx.doi.org/10.5370/kiee.2011.60.2.446.

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3

Sobot, R., S. Stapleton, and M. Syrzycki. "Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays." IEEE Transactions on Circuits and Systems I: Regular Papers 53, no. 2 (February 2006): 264–73. http://dx.doi.org/10.1109/tcsi.2005.857085.

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4

Witte, Pascal, John G. Kauffman, Joachim Becker, and Maurits Ortmanns. "A Correlation-Based Background Error Estimation Technique for Bandpass Delta–Sigma ADC DACs." IEEE Transactions on Circuits and Systems II: Express Briefs 58, no. 11 (November 2011): 748–52. http://dx.doi.org/10.1109/tcsii.2011.2168021.

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5

Molina-Salgado, Gerardo, Alonso Morgado, Gordana Jovanovic Dolecek, and Jose M. de la Rosa. "LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 5 (May 2014): 1442–55. http://dx.doi.org/10.1109/tcsi.2013.2289412.

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6

Raghavan, G., J. F. Jensen, J. Laskowski, M. Kardos, M. G. Case, M. Sokolich, and S. Thomas. "Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators." IEEE Journal of Solid-State Circuits 36, no. 1 (2001): 5–13. http://dx.doi.org/10.1109/4.896223.

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7

Maurino, R., and P. Mole. "A 200-MHz IF 11-bit fourth-order bandpass /spl Delta//spl Sigma/ ADC in SiGe." IEEE Journal of Solid-State Circuits 35, no. 7 (July 2000): 959–67. http://dx.doi.org/10.1109/4.848204.

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8

Xu, Yang, Xinwang Zhang, Zhihua Wang, and Baoyong Chi. "A Flexible Continuous-Time $\Delta \Sigma $ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 3 (March 2017): 872–80. http://dx.doi.org/10.1109/tvlsi.2016.2611518.

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9

Kaplan, T. S., J. F. Jensen, C. H. Fields, and M. C. F. Chang. "A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping." IEEE Journal of Solid-State Circuits 40, no. 3 (March 2005): 603–10. http://dx.doi.org/10.1109/jssc.2005.843708.

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10

Afifi, M., Y. Manoli, and M. Keller. "A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators." Analog Integrated Circuits and Signal Processing 79, no. 3 (April 10, 2014): 555–68. http://dx.doi.org/10.1007/s10470-014-0294-0.

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11

Shahein, Ahmed, Mohamed Afifi, Markus Becker, Niklas Lotze, and Yiannos Manoli. "A Power-Efficient Tunable Narrow-Band Digital Front End for Bandpass Sigma–Delta ADCs in Digital FM Receivers." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 11 (November 2010): 883–87. http://dx.doi.org/10.1109/tcsii.2010.2082891.

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12

Schreier, Richard, Nazmy Abaskharoun, Hajime Shibata, Donald Paterson, Steven Rose, Iuri Mehr, and Qui Luu. "A 375-mW Quadrature Bandpass $\Delta\Sigma$ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz." IEEE Journal of Solid-State Circuits 41, no. 12 (December 2006): 2632–40. http://dx.doi.org/10.1109/jssc.2006.884340.

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13

Chalvatzis, Theodoros, Eric Gagnon, Morris Repeta, and Sorin P. Voinigescu. "A Low-Noise 40-GS/s Continuous-Time Bandpass $\Delta\Sigma$ ADC Centered at 2 GHz for Direct Sampling Receivers." IEEE Journal of Solid-State Circuits 42, no. 5 (May 2007): 1065–75. http://dx.doi.org/10.1109/jssc.2007.894794.

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14

Gupta, Subhanshu, Daibashish Gangopadhyay, Hasnain Lakdawala, Jacques C. Rudell, and David J. Allstot. "A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass $\Sigma \Delta$ ADC in 0.13 $\mu$m CMOS." IEEE Journal of Solid-State Circuits 47, no. 5 (May 2012): 1141–53. http://dx.doi.org/10.1109/jssc.2012.2185530.

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15

Huang, Linqing, Jiulong Shen, Qiyun Ma, Hao Wang, Wei-Mong Tsang, Fang Tang, and Miao Wang. "A Low-Noise and Monolithic Array Tactile Sensor Based on Incremental Delta-Sigma Analog-to-Digital Converters." Electronics 11, no. 8 (April 11, 2022): 1206. http://dx.doi.org/10.3390/electronics11081206.

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Abstract:
A low-noise and monolithic array tactile sensor, in which a tactile sensing unit, a low-noise analog front end (AFE), and a high-resolution delta-sigma analog-to-digital converter (ΔΣ ADC) are fully integrated, is presented in this paper. In this proposed system, compared with a discrete-device-based board-level system, the parasitic effect of a long cable connection can be reduced, and results are more accurate. Furthermore, a smaller system area and a lower power consumption can be achieved in this monolithic system. A discrete-continuous mixed mode bandpass AFE is proposed to filter out low-frequency flicker noise and high-frequency white noise. In order to improve the quantization rate of the sensor readout circuit and further suppress the high-frequency noise, a two-way alternate sample-and-hold circuit scheme is adopted in this design. The proposed tactile sensor is designed and fabricated in a 0.5-μm CMOS (Complementary metal oxide semiconductor)mixed-signal process with a 16 × 16 array and a total chip area of 1.9 × 1.9 cm2. This chip consumes 33.5 mW from a 5 V supply. The measurement results showed that the signal-to-noise and distortion rate (SNDR) was 65.2894 dB and that the effective number of bits (ENoB) was 10.553 dB. Moreover, this sensor could achieve a pressure measurement range of 0.002–0.5 N with a resolution of 0.4 mN.
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16

Xu, Yang, Zehong Zhang, Baoyong Chi, Nan Qi, Hualin Cai, and Zhihua Wang. "A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT $\Delta \Sigma $ ADC With AntiPole-Splitting Opamp and Digital $I$ / $Q$ Calibration." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 1 (January 2016): 243–55. http://dx.doi.org/10.1109/tvlsi.2015.2394365.

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17

Sayed, Alhassan, Tamer Badran, Marie-Minerve Louerat, and Hassan Aboushady. "A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 9 (September 2020): 1559–63. http://dx.doi.org/10.1109/tcsii.2020.3013821.

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18

Thandri, Bharath Kumar, and Jose Silva-Martinez. "A 63 dB SNR, 75-mW Bandpass RF $\Sigma\Delta$ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-$\mu{\hbox {m}}$ SiGe BiCMOS Technology." IEEE Journal of Solid-State Circuits 42, no. 2 (February 2007): 269–79. http://dx.doi.org/10.1109/jssc.2006.889389.

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19

Shibata, Hajime, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, and Ping Wing Lai. "A DC-to-1 GHz Tunable RF $\Delta \Sigma$ ADC Achieving DR$ =$ 74 dB and BW$ =$ 150 MHz at $f_{0} =$ 450 MHz Using 550 mW." IEEE Journal of Solid-State Circuits 47, no. 12 (December 2012): 2888–97. http://dx.doi.org/10.1109/jssc.2012.2217860.

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20

Su, Shiyu, and Mike Shuo-Wei Chen. "A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <−67-dBc IM3 Within DC to 6-GHz Tunable Passbands." IEEE Journal of Solid-State Circuits 53, no. 12 (December 2018): 3517–27. http://dx.doi.org/10.1109/jssc.2018.2871143.

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21

Lu, Rundao, and Michael P. Flynn. "A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC." IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 1–11. http://dx.doi.org/10.1109/tcsi.2023.3289189.

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22

Akram, Waqas, and Earl E. Swartzlander. "Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters." Journal of Signal Processing Systems 65, no. 2 (September 4, 2011). http://dx.doi.org/10.1007/s11265-011-0611-0.

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