Dissertations / Theses on the topic 'Tunable bandpass delta sigma ADC'

L'architecture conventionnelle utilisée par toutes les publications précédentes pour le récepteur de balayage de spectre est basée sur le CAN en BB, donc il a une consommation d'énergie élevée, une complexité plus élevée et souffre d'inadéquations de circuits et de non-linéarité. Dans ce travail, nous proposons d'utiliser un récepteur RF basé sur CAN delta-sigma en PB. Les CAN PB DS ajustables précédemment signalés implémentée de manière complexe. Nous présentons une implémentation efficace du CAN PB DS accordable. Un récepteur de détection de spectre, basé sur l'architecture frontale RF à faible consommation d'énergie proposée dans cette thèse, est également proposé. Le récepteur complet proposé ne souffre pas d'un déséquilibre 1/Q. Les résultats de simulation pour montrer l'impact de la non-linéarité du circuit sur les performances sont présentés. Une implémentation de circuit d'un backend numérique du système proposé est présentée. Cette implémentation comprend un mélangeur à conversion descendante efficace, un filtre de décimation, un bloc FFT et un module de détection d'énergie. L'implémentation a été validée à l'aide l'outil SignalTab. Des études, ne présentent que des résultats analytiques ou de simulation, visant à montrer l'impact du déséquilibre 1/Q sur les performances de détection du spectre ont déjà été publiées. Dans ce travail, nous présentons la première mesure matérielle du déséquilibre I/Q sur les performances de détection du spectre. Dans le domaine médical, nous présentons pour la première fois une étude de l'effet de l'exposition aux RF-EMF sur les nouveau-nés via une acquisition simultanée de signaux RF et de paramètres physiologiques
Spectrum sensing applications cover wide variety, such as efficient utilization of frequency spectrum, and in medical applications. The conventional architecture used by all the previous publications for spectrum sensing receiver is based on baseband ADC, hence it has high power consumption, higher complexity, and suffers from circuit mismatches and nonlinearity. In this work, we propose using an RF receiver based on bandpass delta-sigma ADC. It is much more convenient to have a tunable BP ΔΣ ADC to simplify the spectrum sweeping task. The previously reported tunable BP ΔΣ ADC’s are implementing tunability in a complex manner. We present an efficient implementation of tunable BP ΔΣ ADC with fixed ratio between the sampling frequency and center frequency. That fixed ratio further simplifies the implementation of the down conversion mixer and decimation filter which serve as the digital backend of the receiver. A spectrum sensing receiver, based on the power-efficient RF front end architecture proposed in this thesis, is also proposed. The proposed complete receiver does not suffer from I/Q imbalance that highly affect the spectrum sensing performance. Simulation results to show the circuit nonlinearity impact on the performance are presented. A circuit implementation of a digital backend of the proposed system is presented. This implementation comprises an efficient down conversion mixer, decimation filter, custom FFT block, and energy detection module. The implementation was validated on Altera FPGA using the on-chip logic analyzer via the SignalTab tool.Studies to show the impact of I/Q imbalance on spectrum sensing performance were previously published. Nevertheless, those publications presented only either analytical or simulation results. In this work, we present the first hardware measurement of the I/Q imbalance on spectrum sensing performance using a commercial SDR transceiver platform.In the medical field, we also present for the first time a study of the effect of RF-EMF exposure on neonates by performing a simultaneous acquisition of RF signals along with recording the physiological parameters of neonates. Using R-Studio, the stationarity of the signals to be correlated was checked, a transformation was performed on the non-stationary signals. Finally, cross correlation between the acquired RF signal (average of the whole spectrum or in a specific band) and each of the recorded physiological parameters did not show an observable impact of RF-EMF exposure on neonates

An important component in many communication system is the digital to analog converter. The component is needed in order to convert real world analog quantities to digital quantities which are easier to process. As the market for hand held devices with wireless communication with the outer world has increased new approaches for sharing the frequency spectrum are needed. Therefore it would be interesting to look at the possibility to design an analog to digital converter that, in runtime, can change the frequency band converted, and hence the used standard. This thesis study one of the possibilities to design such an ADC, as a Σ∆ modulator, and more precise the structure called Cascade of resonators with distributed feedback and input (CRFB). The order of the modulator in this study is two.

Software radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ± 1.25 V supply. The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA architecture combines both cross coupling and source degeneration in order to obtain good IM3 performance. A system level digital tuning scheme is proposed to tune the ADC performance over process, voltage and temperature variations. The output bit stream of the ADC is captured using an external DSP, where a software tuning algorithm tunes the ADC parameters for best SNR performance. The IF ADC was designed in TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V supply.

Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switch’s speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulator’s power consumption is 302 mW from supply power of ± 1.65V.

La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz
Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz

Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity.
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碩士
淡江大學
電機工程學系碩士班
93
A Bandpass ∆Σ modulators are widely used in inter-mediate frequency (IF) and radio frequency (RF) communication systems. In order to avoid the low frequency noise in zero IF receiver and prevent the mismatch of the circuits from degrading the receiver performance, the single IF architecture is a good candidate. Since the signal, which is received and down-converted, may be varied due to process variations, a tunable bandpass ∆Σ modulator is required to improve the performance of the receiver. There are so many efforts are devoted in tunable continuous-time (CT) ∆Σ modulator by the modifying the transconductance of OTA in the resonator. However, an elaborate tuning scheme and an additional cost are demanded in the tunable continuous-time ∆Σ modulator. Since the mismatch among capacitors is very small, the SC ∆Σ modulators are popular in narrow band data converter. In this paper, a tunable bandpass ∆Σ modulator by one parameter only is adopted to optimize modulator performance. To achieve a tunable resonator in the modulator, a multiple path SC scheme is applied for the adjustments of the center frequency. A wide tuning range from 5MHz to 30MHz is preformed to demonstrate the flexibility of the modulator. Furthermore, a double sampling technique is used to relax the requirements of opamp performance. A tunable switched-capacitor (SC) bandpass delta sigma (∆Σ) modulator using double sampling by one input parameter is proposed. The center frequency of the modulator can be varied from 5MHz to 30MHz at a sampling frequency of 70MHz. Its performance can be hence improved by fine tuning the center frequency. The purposed modulator was implemented in 0.35-µm 2P4M CMOS standard technology with the core area of 2.8×1.5 mm2. The measured dynamic range of 68dB within 200 kHz bandwidth can be achieved. Its power consumption is 58mW under a 3.3-V supply voltage.

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry.

A whole-of-band receiver structure is proposed. In this structure, the whole mobile band (125 channels for GSM) is digitized and channel selection is performed using DSP filters. The ADC is a critical component in this structure, requiring 13bits resolution at sampling rate of 50MHz . A modified ΣΔ ADC converter is proposed for this application. The ΣΔ ADC must be able to null the quantization noise at the frequency of the desired channel. The research considers the feasibility of varying this frequency for tuning different channels. This is a novel concept for ΣΔ systems and so the simplest form of ΣΔ structure was chosen for evaluation to reduce the degrees of freedom in the many variables involved. A second order noise tunable bandpass ΣΔ ADC is studied using pole zero placement techniques in the z-plane. Tuning is performed by moving the zero positions around the unit circle. The optimized pole position is a compromise between noise performance and stability. The signal noise ratio is equivalent to 8bits, indicating a higher order ΣΔ ADC would be required for a practical radio receiver. Sensitivity analysis showed that the quantization noise is sensitive to errors in the system's main tuning coefficient adjustment. Accuracy for this coefficient has to be better than 1%, indicating that some external precision components will be required for any VLSI implementation. The effect of multichannel signals on the performance of the ADC is studied. It is shown that saturation of intermediate nodes dominated the intermodulation performance of the ADC. However, the loss of performance is not great (3dB to 6dB) and can be offset by over designing the ADC to give an appropriate safety margin. The successful implementation of noise4 tunable ΣΔ converter requires accurate setting of the adjustable coefficients. This is seen as the major design obstacle.

碩士
大同大學
電機工程學系(所)
97
In this thesis, a switched-capacitor (SC) double-sampling three-bit fourth-order bandpass delta-sigma modulator with tunable resonators and active adder opamp based on feed-forward topology is proposed. The feed-forward topology can reduce the distortion in the signal path, and efficiently reduce the circuit complexity and physical area, especially when the loop contains a multi-bit quantizer. The tunable resonator can optimize modulator performance for band of interest by adjusting the resonator frequency with selecting switches, and the resonator just needs one operation amplifier to realize that can reduce the power consumption. Additionally, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. An active adder opamp is used before the quantizer to avoid any signal attenuation due to parasitics, and any kick-back noise from the quantizer. In addition, we also presented the self-coupling bandpass noise shaping, and sorting algorithm DEM, and they are verified by the system level simulation. The design procedure is summarized in the following: First, we can use MATLAB and SIMULINK to verify the stability and estimate the performance. Then, Hspice is used for transistor level simulation. The final implementation of the modulator works at 1.5V supply and clock frequency is 40MHz (effective frequency would be 80MHz), the input center frequency is 20MHz in TSMC 0.18�慆 CMOS 1P6M process. Simulation results reveal that the peak SNDR is 47.48dB and 62.42dB with -12dBFS input for bandwidth 5MHz (OSR=8) and bandwidth 0.625MHz (OSR=64), respectively, and power consumption is 46mW.

碩士
大同大學
電機工程學系(所)
96
Bandpass delta-sigma converters have been widely used in RF communication systems and instrumentation filed due to the ability to obtain high resolution in the band of interest compared to the traditional Nyquist-rate converters. As the growing of the wireless communication standards, the demand for a wideband and multi-stand RF/IF receivers has led the design of the modulators to be tunable and flexible. This thesis proposes a tunable double-sampled feedforward multi-stage noise shape (MASH) delta-sigma modulator. It will tune according to the demand bandwith. The advantages of feedforward topology are reducing the non-idea effect of the opamp and decreasing the complexity of the design for the MASH architecture. Additionally, double-sampled switch-capacitor (SC) technique provides a good method of increasing the sampling frequency and relaxes the requirement of the opamp. The design flow corresponding to the CAD tools is as following. Using MATLAB, the optimal parameters are obtained by the system level simulation. Then, the circuit level simulation is implemented by HSPICE. Finally, the layout of the whole circuit is accomplished with Virtuoso of CADENCE. And the modulator is simulated by using the SPICE models of TSMC 0.18μm CMOS 1P6M process.

碩士
大同大學
電機工程學系(所)
98
In this thesis, a switched-capacitor (SC) double-sampling three-bit sixth-order bandpass delta-sigma modulator with tunable resonators is proposed. It achieves sixth-order noise shaping by using tunable SC resonators and quantization noise coupling, and only three opamps are used so that the overall power consumption is lower compared to that of the conventional architecture. The feed-forward topology can reduce the distortion in the signal path, and efficiently reduce the circuit complexity and physical area, especially when the loop contains a multi-bit quantizer. Besides, the tunable resonator can increase the signal-to-noise and distortion ratio (SNDR) in lower oversampling ratio situation by properly adjusting the resonator frequency. In addition, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. An active adder opamp is used before the quantizer to avoid any signal attenuation due to parasitics, and any kick-back noise from the quantizer. This adder is also used for quantization noise coupling to provide further noise shaping. Additionally, we present the filter-based data-weighted averaging (DWA) to modify the nonlinearity problem of the digital-to-analog converter generated by capacitor mismatch errors. The design procedure is summarized in the following: First, we use MATLAB and SIMULINK to verify the stability and estimate the performance. Then, Hspice is used for transistor level simulation. The final implementation of the modulator works at 1.5V supply, clock frequency is 40MHz (effective frequency would be 80MHz), and the input center frequency is 20MHz in TSMC 0.18?慆 CMOS 1P6M process. Simulation results reveal that the peak SNDR is 59.65 dB with -6dBFS input for bandwidth 2.5MHz (OSR=16), and power consumption is 39.28mW.

碩士
大同大學
電機工程學系(所)
100
In this thesis, we propose a double-sampling three-bit fourth-order bandpass noise-coupling delta-sigma modulator. The design is based on a tunable resonator, which requires only one opamp and therefore has low power consumption. The double-sampling switched-capacitor (SC) technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. The active adder with noise coupling could avoid any signal attenuation due to parasitic, and kick-back noise from the quantizer, and improve two bit resolution in this modulator. The tunable resonator increases the resolution by properly adjusting the resonator frequency. In additional, we design a filter-based data-weighted averaging (DWA) to modify the harmonic tones caused by the mismatch errors of the capacitors in the internal DAC. This design is carried out as follows: First, The MATLAB and SIMULINK are used to ensure the stability and performance of the architecture. Then, the transistor level simulation is done by Hspice in TSMC 0.18um CMOS 1P6M process. At last, we implement this modulator at 1.5 voltage supply, 80MHz clock frequency and the center frequency of the input signal is 20MHz. The simulated SNDR is 48.39dB with -4.2dBFS for 5MHz bandwidth and the power consumption is 30.6mW.

碩士
大同大學
電機工程學系(所)
101
In this thesis, a double-sampling three-bit fourth-order bandpass noise-coupling delta-sigma modulator with dynamic element matching (DEM) is proposed. The design is based on a tunable switched-capacitor (SC) resonator, which can be adjusted to obtain the optimum notch frequencies according to the different bandwidth in different application. Besides, the resonator only requires one opamp in one stage, and therefore the overall power consumption is lower than conventional architecture. The double-sampling technique provides a good method of increasing the sampling frequency and relaxes the performance requirement of the opamp. The active adder with noise coupling technique could avoid any signal attenuation due to parasitic effect, and kick-back noise from the quantizer, and increase the order of the noise transfer function by two without extra circuits. In additional, a dynamic element matching with data-directed scrambler structure is implemented to reduce the harmonic tones caused by the mismatch errors of the capacitors in the internal DAC. The design is carried out as follows: First, MATLAB and SIMULINK are used to ensure the stability and performance of the structure. Then, the transistor level simulation is done by HSPICE in TSMC 0.18um CMOS 1P6M process. The final implementation of the modulator works at 1.5V supply, 80MHz clock frequency and the center frequency of the input signal is 20MHz. The simulated SNDR is 46.51dB with -4.2dBFS for 5MHz bandwidth and the power consumption is 38.1mW.

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content.

About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively. This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals. The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2. The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2. The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy.