Relevant bibliographies by topics / Triple gate transistor

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Triple gate transistor'

Author: Grafiati
Published: 25 May 2024

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Triple gate transistor.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Triple gate transistor"

1

Grossl Bade, Tamiris, Hassan Hamad, Adrien Lambert, Hervé Morel, and Dominique Planson. "Threshold Voltage Measurement Protocol “Triple Sense” Applied to GaN HEMTs." Electronics 12, no. 11 (June 3, 2023): 2529. http://dx.doi.org/10.3390/electronics12112529.

Full text
Abstract:
The threshold voltage instability in p-GaN gate high electron mobility transistors (HEMTs) has been brought into evidence in recent years. It can lead to reliability issues in switching applications, and it can be followed by other degradation mechanisms. In this paper, a Vth measurement protocol established for SiC MOSFETs is applied to GaN HEMTs: the triple sense protocol, which uses voltage bias to precondition the transistor gate. It has been experimentally verified that the proposed protocol increased the stability of the Vth measurement, even for measurements following degrading voltage bias stress on both drain and gate.
APA, Harvard, Vancouver, ISO, and other styles
2

Cho, Seong-Kun, and Won-Ju Cho. "Highly Sensitive and Transparent Urea-EnFET Based Point-of-Care Diagnostic Test Sensor with a Triple-Gate a-IGZO TFT." Sensors 21, no. 14 (July 12, 2021): 4748. http://dx.doi.org/10.3390/s21144748.

Full text
Abstract:
In this study, we propose a highly sensitive transparent urea enzymatic field-effect transistor (EnFET) point-of-care (POC) diagnostic test sensor using a triple-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film pH ion-sensitive field-effect transistor (ISFET). The EnFET sensor consists of a urease-immobilized tin-dioxide (SnO2) sensing membrane extended gate (EG) and an a-IGZO thin film transistor (TFT), which acts as the detector and transducer, respectively. To enhance the urea sensitivity, we designed a triple-gate a-IGZO TFT transducer with a top gate (TG) at the top of the channel, a bottom gate (BG) at the bottom of the channel, and a side gate (SG) on the side of the channel. By using capacitive coupling between these gates, an extremely high urea sensitivity of 3632.1 mV/pUrea was accomplished in the range of pUrea 2 to 3.5; this is 50 times greater than the sensitivities observed in prior works. High urea sensitivity and reliability were even obtained in the low pUrea (0.5 to 2) and high pUrea (3.5 to 5) ranges. The proposed urea-EnFET sensor with a triple-gate a-IGZO TFT is therefore expected to be useful for POC diagnostic tests that require high sensitivity and high reliability.
APA, Harvard, Vancouver, ISO, and other styles
3

Conde, Jorge E., Antonio Cereira, and M. Estrada. "Distortion Analysis of Triple-Gate Transistor in Saturation." ECS Transactions 9, no. 1 (December 19, 2019): 67–73. http://dx.doi.org/10.1149/1.2766875.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Gay, R., V. Della Marca, H. Aziza, P. Laine, A. Regnier, S. Niel, and A. Marzaki. "Gate stress reliability of a novel trench-based Triple Gate Transistor." Microelectronics Reliability 126 (November 2021): 114233. http://dx.doi.org/10.1016/j.microrel.2021.114233.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

SHAHHOSEINI, ALI, KAMYAR SAGHAFI, MOHAMMAD KAZEM MORAVVEJ-FARSHI, and RAHIM FAEZ. "TRIPLE-TUNNEL JUNCTION SINGLE ELECTRON TRANSISTOR (TTJ-SET)." Modern Physics Letters B 25, no. 17 (July 10, 2011): 1487–501. http://dx.doi.org/10.1142/s0217984911026346.

Full text
Abstract:
We propose a triple-tunnel junction single electron transistor (TTJ-SET). The proposed structure consists of a metallic quantum-dot island that is capacitive coupled to a gate contact and surrounded by three tunnel junctions. To the best of our knowledge, this is the first instance of introducing this new structure that is suitable for both digital and analog applications. I–V D characteristics of the proposed TTJ-SET, simulated by a HSPICE macro model for various gate voltages, are in excellent agreement with those obtained by SIMON, which is a Monte-Carlo based simulator. We show how one can design a digital inverter by using a single TTJ-SET. We also show that, under suitable conditions, a TTJ-SET can operate as a full- or half-wave analog rectifier.
APA, Harvard, Vancouver, ISO, and other styles
6

Pandey, Neeta, Kirti Gupta, and Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation." VLSI Design 2016 (September 19, 2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.

Full text
Abstract:
This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.
APA, Harvard, Vancouver, ISO, and other styles
7

Manikandan, S., P. Suveetha Dhanaselvam, and M. Karthigai Pandian. "A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor." Journal of Nanoelectronics and Optoelectronics 16, no. 2 (February 1, 2021): 318–23. http://dx.doi.org/10.1166/jno.2021.2951.

Full text
Abstract:
A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along the device channel. Higher drain bias conditions leading to DIBL are reduced in the proposed structure by minimal variation of voltages owing to three different gate materials that maintain a steady field distribution along the channel. This model explicitly shows the impact of various criteria like drain bias voltage, gate bias voltage, thickness of the silicon layer, thickness of the oxide layer, and length of the channel on electrostatic potential and the deterioration of threshold voltage. The proposed analytical model is validated with TCAD simulations and it could be further extended to study the advanced electrical characteristics of the JL Triple Material CSG Silicon Nanowire Transistor.
APA, Harvard, Vancouver, ISO, and other styles
8

de Araujo, Gustavo Vinicius, Joao Martino, and Paula Agopian. "Operational Transconductance Amplifier Designed with Experimental Omega-Gate Nanowire SOI MOSFETs." ECS Meeting Abstracts MA2023-01, no. 33 (August 28, 2023): 1861. http://dx.doi.org/10.1149/ma2023-01331861mtgabs.

Full text
Abstract:
The nanowire omega-gate technology is one of the possible technologies to replace the FinFET one in the semiconductor chip market. The omega-gate nanowire SOI MOSFET is considered a triple plus gate device, near the gate-all-around performance (figure 1) [1]. Due to the omega gate structure this device presents a better gate to channel electrostatic coupling than the FinFET devices, resulting in a greater immunity to short channel effects [1,2]. The Operational Transconductance Amplifier (OTA) is a frequently used analog block in the integrated circuits. The studied OTA consists in a two-stage amplifier, where the first stage is a differential amplifier with active load and the second one is a common source amplifier, as can be seen in figure 2. This analog block is biased through the current source and the bias current is mirrored for each stage. In addition, negative feedback is used between the first and second stages with a compensation capacitor (miller capacitor) in order to stabilize the amplifier response. In this work, an OTA circuit is designed with SOI omega-gate nanowire experimental transistors. In order to find the best device to be used in the project, some measurements were carried out of several nanowire devices with different channel lengths (ranging from 20 nm to 200 nm). The schematic structure of the measured devices is presented in figure 3 [2]. Basic device parameters such as: transconductance (gm), output conductance (gd), Early voltage (VEA), threshold voltage (VT), transistor efficiency (gm/ID) and subthreshold slope (SS) were analyzed. The model of the experimental omega-gate transistors was performed using the Look Up Table (LUT) method. The capacitance measurements of the nanowire transistor were also considered, to simulate the frequency responses more faithfully. The simulator used to design the OTA circuit was Cadence using the Verilog-A language. It was obtained the main figure of merit of this block like voltage gain (Av), gain-bandwidth product (GBW), phase margin and power. A transistor efficiency (gm/ID) near 8 V-1 was chosen in order to compare the performance of OTA designed with omega-gate nanowire devices (NW-OTA) of this work with anothers OTAs designed with triple gate FinFETs (FinFET-OTA) and with nanosheets (NS-OTA) from the literature (Table 1) [3,4]. Table 1 shows that the phase margin is close to 60o in all cases, ensuring the stability of the circuit. The NW-OTA presents higher voltage gain compared to FinFET-OTA due to the better gate to channel coupling. The NS-OTA presents the highest voltage gain of all cases, but it is the more expensive technology [4]. When GBW is analyzed for all 3 designs, the NW-OTA shows better results than the NS-OTA, using the same load capacitance of 200fF, thanks to the lower miller capacitance (Cc) required to keep the frequency behavior. The FinFET-OTA shows the best result in relation to GBW, but the FinFET-OTA project doesn’t consider a load capacitance, making the comparison unfair [3]. Figure 4 shows the gain and phase of the OTA using a SOI omega-gate nanowire transistors. In summary, the OTA designed with SOI omega-gate nanowire technology presents a better performance than FinFET one, can be implemented in a smaller area on the chip (smaller Cc capacitor and smaller number of fins in parallel) and it is a cheaper option compared to nanosheet one. Figure 1
APA, Harvard, Vancouver, ISO, and other styles
9

Müller, M. R., A. Gumprich, F. Schütte, K. Kallis, U. Künzelmann, S. Engels, C. Stampfer, N. Wilck, and J. Knoch. "Buried triple-gate structures for advanced field-effect transistor devices." Microelectronic Engineering 119 (May 2014): 95–99. http://dx.doi.org/10.1016/j.mee.2014.02.001.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Fui, Tan Chun, Ajay Kumar Singh, and Lim Way Soong. "Performance Characterization of Dual-Metal Triple- Gate-Dielectric (DM_TGD) Tunnel Field Effect Transistor (TFET)." International Journal of Robotics and Automation Technology 8 (December 31, 2021): 83–89. http://dx.doi.org/10.31875/2409-9694.2021.08.8.

Full text
Abstract:
Abstract: Since, Dual Metal Gate (DMG) technology alone is not enough to rectify the problem of low ON current and large ambipolar current in the TFET, therefore, a novel TFET structure, known as dual metal triple-gate-dielectric (DM_TGD) TFET, has been proposed. We have combined the dielectric and gate material work function engineering to enhance the performance of the conventional FET. In the proposed structure, the gate region is divided into three dielectric materials: TiO2/Al2O3/SiO2. This approach is chosen because high dielectric material alone near the source cannot improve the performance due to increase in fringing fields. This paper presents the detail processing of the proposed structure. We have evaluated and optimized the dc performance of the proposed N-DM_TGD TFET with the help of 2-D ATLAS simulator. The results were compared with those exhibited by dual metal hetero-gate-dielectric TFET, single metal hetero- gate-dielectric TFET and single metal triple-gate-dielectric TFET of identical dimensions. It has been observed that the DM_TGD device offers better transconductance (gm), lower subthreshold slope, lower ambipolar current and larger ON current.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Triple gate transistor"

1

Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.

Full text
Abstract:
L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture et le mode de fonctionnement d’un nouveau composant, appelé transistor triple grille, ont été présentés. Sur la base de cette nouvelle architecture, composée de grilles de contrôle indépendantes, différents transistors multigrilles ont été fabriqués. Par la même occasion, leur comportement électrique a été analysé. Dans la continuité, des études de fiabilité, portant notamment sur les oxydes de grilles, ont été menées. L’objectif de ces études a été d’étudier l’impact d’une contrainte électrique, appliquée sur une grille du transistor, sur les autres grilles non soumises à cette même contrainte. Des caractérisations électriques ainsi que des simulations TCAD, ont permis d’améliorer la compréhension des résultats obtenus. Finalement, la structure du transistor triple grille a été modélisée à l’aide d’un modèle compact de transistor de type PSP. Cette modélisation a pour objectif de permettre l’évaluation du comportement et des performances électriques de ce transistor au niveau circuit
The aim of this work is to improve the performance, cost and area of a microcontroller manufactured in a 40 nm CMOS embedded memory technology (eNVM), by developing new transistor architectures suitable for the IoT market. The context is first presented with a focus on the technological and economical limitations of the CMOS technology. In a second part, the eNVM manufacturing process as well as the architecture and operation mode of a new component called triple gate transistor are presented. Based on this new architecture which provides independent control gates, various multigate transistors are manufactured and their electrical behaviour is analysed. Reliability studies are then carried out, to assess the reliability of the gate’s oxides. The objective is to study the impact of an electrical stress applied to one transistor gate on the gates not subject to this same stress. Electrical characterizations and TCAD simulations are also conducted to improve the understanding. Finally, the structure of the triple gate transistor is modelled using a compact PSP transistor model. The aim is to evaluate the behaviour but also the electrical performance of this transistor at the circuit level
APA, Harvard, Vancouver, ISO, and other styles
2

Andrade, Maria Glória Caño de. "Estudo de transistores de porta tripla de corpo." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10062013-150025/.

Full text
Abstract:
O objetivo principal deste trabalho é o estudo de transistores MuGFETs de porta tripla de Corpo de canal tipo-n com e sem a aplicação da configuração DTMOS. Este estudo será realizado através de simulações numéricas tridimensionais e por caracterizações elétricas. A corrente de dreno, a transcondutância, a resistência, a tensão de limiar, a inclinação de sublimiar e a Redução da Barreira Induzida pelo Dreno (DIBL) serão analisadas em modo DTMOS e em configuração de polarização convencional. Importantes figuras de mérito para o desempenho analógico como transcondutância-sobre-corrente de dreno, a condutância de saída, a tensão Early e o ganho de tensão intrínseco serão estudados tanto experimentalmente como através de simulações numéricas tridimensionais para diferentes concentrações de dopantes no canal. Os resultados indicam que a configuração DTMOS apresenta as características elétricas superiores (4 e 10 %) e maior eficiência dos transistores. Além disso, os dispositivos DTMOS com alta concentração de dopantes no canal apresentaram um desempenho analógico muito melhor quando comparados ao transistor de porta tripla de Corpo em modo de operação convencional. O ruído de baixa frequência (LF) é pela primeira vez experimentalmente analisado na região linear e saturação. A origem do ruído é analisada de maneira a compreender os mecanismos físicos envolvidos neste tipo de ruído. As medições mostraram que os espectros do sinal dos dispositivos de porta tripla de Corpo e DTMOS são compostos por flutuações referentes ao número de portadores devido ao ruído flicker e por ondas de ruído de geração e recombinação no dielétrico de porta que se torna maior com o aumento da tensão de porta. No entanto, o principal fato desta análise é que o dispositivo DTMOS apresentou praticamente a mesma magnitude do ruído LF na região linear e de saturação que o dispositivo de Corpo. A energia de 60 MeV na fluência de p/1012 cm-2 de radiações de prótons é também estudada experimentalmente em termos das características elétricas, desempenho do analógico e ruído LF nos dispositivos de porta tripla de Corpo e DTMOS. Os resultados indicam que combinado com as suas melhores características elétricas e um ótimo desempenho analógico do DTMOS, faz o transistor de porta tripla de Corpo um candidato muito competitivo para aplicações analógicas em ruído de baixa frequência antes e depois da irradiação. A vantagem da técnica DTMOS em transistores de porta tripla em ambientes onde os dispositivos têm de suportar alta radiação é devido à menor penetração do campo de dreno que reduz o efeito das cargas induzidas pelo óxido de isolação (STI). Finalmente, o transistor de Corpo de porta tripla de canal tipo-n é experimentalmente estudado como célula de memória, isto é, como 1T-DRAM (Memória de Acesso Aleatório Dinâmico com 1 transistor). Para escrever e ler 1 é utilizado um modo de programação que utiliza o efeito do transistor bipolar parasitário (BJT) enquanto a polarização direta da junção do corpo e do dreno é usada para escrever 0. As correntes de leitura e escrita aumentam com o aumento da tensão do corpo (VB) porque as cargas induzidas pelo efeito BJT é armazenada dentro da aleta. Quando o corpo do transistor está flutuante, o dispositivo retém mais cargas dentro da sua aleta. Além disso, transistor de Corpo pode ser utilizado como 1T-DRAM com eletrodo de porta e substrato flutuando. Neste caso, o dispositivo funciona como um biristor (sem porta).
The main goal of this work is to investigate the n-channel MuGFETs (triple-gate) Bulk transistors with and without the application of DTMOS operation. This work will be done through three-dimensional numerical simulation and by electrical characterizations. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DTMOS mode and the standard biasing configuration. Important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional numerical simulations for different channel doping concentrations. The results indicate that the DTMOS configuration has superior electrical characteristics (4 e 10 %) and higher transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode. Low-Frequency (LF) noise is for the first time experimentally investigated in linear and saturation region. The origin of the noise will be analyzed in order to understand the physical mechanisms involved in this type of noise. Measurements showed that the signal spectra for Bulk and DTMOS are composed of number fluctuations related flicker noise with on top generation and recombination noise humps, which become more pronounced at higher gate voltage. However, the most important finding is the fact that DTMOS devices showed practically the same LF noise magnitude in linear and saturation region than standard Bulk device. Proton irradiation with energy of 60 MeV and fluence of p/1012 cm-2 is also experimentally studied in terms of electric characteristic, analog performance and the LF noise in Bulk and DTMOS triple gate devices. The results indicate that the combined of the better electrical characteristics and an excellent analog performance of DTMOS devices, makes it a very competitive candidate for low-noise RF analog applications before and after irradiation. The advantage of dynamic threshold voltage in triple gate transistors in environments where the devices have to withstand high-energy radiation is due to its lower drain electric field penetration that lowers the effect of the radiation-induced charges in the STI (shallow trench isolation) regions adjacent to the fin. Finally, the n-channel triple gate Bulk device is used for memory application, that is, 1T-DRAM (Dynamic Random Access Memory with 1 Transistor). Bipolar junction transistor (BJT) programming mode is used to write and read 1 while the forward biasing of the body-drain junction is used to write 0. The reading and writing current increases with increasing body bias (VB) because the load induced by the BJT effect is stored within the fin. When the body of the transistor is floating, the device retains more charge within its fin. In addition, transistor could also operate as 1T-DRAM with both gate and bulk contacts floating, which is similar to the biristor (gateless) behavior.
APA, Harvard, Vancouver, ISO, and other styles
3

Bertoldo, Marcelo. "Efeitos da radiação de prótons em FinFET\'s de porta tripla de corpo (Bulk-FinFET)." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-24012017-082703/.

Full text
Abstract:
O transistor de efeito de campo por aletas de porta tripla de corpo (Bulk-FinFET) é um dispositivo com aplicações comerciais e possui algumas vantagens sobre os FinFETs de porta tripla SOI (Silício sobre Isolante - Silicon on Insulator). Estas vantagens são devidas ao custo da lâmina mais competitivo e maior quantidade de fabricantes de lâmina de silício, além da compatibilidade com processos de tecnologias convencionais de substrato de silício e melhor dissipação térmica. Aplicações aeroespaciais estão sujeitas à incidência das radiações ionizantes de partículas e eletromagnéticas. Os efeitos permanentes das radiações ionizantes criam cargas positivas nos óxidos dos transistores. São afetados os óxidos de porta e os óxidos de isolação, podendo levar os transistores a degradação e falha. Neste trabalho foi avaliado o impacto das radiações ionizantes de prótons de 60 MeV em FinFETs de porta tripla de corpo. O seu desempenho elétrico em aplicações de CIs CMOS analógicos após as radiações ionizantes comparando-os com dispositivos não radiados. Esta radiação possui de uma energia radiante bem maior que as radiações ionizantes presentes nas regiões do espaço visando o estudo do pior caso. Por isso se estes dispositivos funcionarem com essas radiações ionizantes extremas, acreditamos que irão funcionar nas regiões que contêm as radiações ionizantes naturais. Foram estudados FinFET\'s do tipo-n e do tipo-p. Os dispositivos estudados foram irradiados não polarizados. Foram extraídas curvas da corrente de dreno em função da tensão aplicada na porta em baixos e altos campos elétricos longitudinais e verticais e avaliado o comportamento dos dispositivos nas regiões de corte e condução. Foi medida também a curva da corrente de dreno em função da tensão aplicada no dreno para a obtenção dos principais parâmetros analógicos, como o ganho de tensão intrínseco, a transcondutância máxima em saturação e a condutância de saída. Todas as curvas foram extraídas para FinFETs de porta tripla de corpo com deferentes dimensões de comprimentos de canal (35, 70, 130 e 1000 nm) e diferentes larguras das aletas (20, 130 e 1000 nm). Devido às cargas induzidas no óxido de isolação pelas radiações ionizantes de prótons, os dispositivos com larguras das aletas mais estreitas apresentaram altas correntes de fuga no dreno na região de corte, tanto com campo elétrico longitudinal decorrente de uma polarização de dreno de 50 mV, quanto para campo elétrico longitudinal decorrente de uma tensão de dreno de 800 mV. Foi observado também, reduções nos valores das tensões de limiar nos dispositivos radiados em torno de 50 mV nos dispositivos estudados quando comparado as condições dos dispositivos pré-radiados. Nos parâmetros analógicos, houve redução significativa no ganho intrínseco de tensão nos dispositivos do tipo-n com maior comprimento de canal após as radiações ionizantes, ao comparar com dispositivos não radiados. O ganho intrínseco de tensão nos dispositivos tipo-n não radiado com comprimento de canal de 1000 nm é em torno de 55 dB. Este valor foi reduzido para cerca de 40 dB nos dispositivos com comprimento de canal de 1000 nm após a radiação. A principal influência na degradação do ganho intrínseco de tensão se deve a alteração da condutância de saída nos dispositivos radiados com comprimento de canal de 1000 nm.
The bulk triple gate fin field effect transistor (Bulk-FinFET) is a devie with comercial aplication and have some advantages versus triple gate SOI (silicon on insulator) FinFET. These advantages are due the low cost of wafer and more quantity of manufacturers; also process more compatible with conventional technologies of silicon substrate and better thermal dissipation. Aerospace applications are subject to particles and electromagnetic ionizing radiation. The permanent effects of ionizing radiation create positive charges on transistor oxide. The gate and isolation oxide are affect by ionizing radiation can lead degrade and failures. This work evaluates the influence of 60 MeV proton ionizing radiation in bulk FinFETs. The electrical performance on analogs CMOS ICs application after ionizing radiation when compared with non-radiated devices. This radiation has a radiant energy higher than ionizing radiation present on space regions, so this work looks the worst case. So if these devices work with these extreme ionizing radiations, these devices will work in natural environment. It was studied n type and p type FinFETs. The studied devices were irradiated non polarized. It were extracted figures of drain current in function of gate voltage in low and high, longitudinal and vertical electrical field, was evaluated the devices behavior on off and conduction region. The extracted, also, the figure of drain in function of gate voltage to obtain the main analog parameters, like intrinsic voltage gain, maximum transconductance in saturation and output conductance. All the figures was extracted for tri gate bulk FinFETs with different channel length dimensions (35, 70, 130 and 1000 nm) and different weight fins (20, 130 and 1000 nm). Due induced charges on isolation oxide by proton ionizing radiation, the devices with narrow fins presented high leakage current on off region, in both longitudinal electrical fields, with 50 mV and 800mV polarization in drain voltage. It was observed also, reduction on threshold voltage on radiated devices around 50 mV if compared with non-radiated devices. In the analog parameters has a significant reduction on voltage intrinsic gain on largest channel length n type devices after ionizing radiation when compared with non-radiated devices. The intrinsic voltage gain on non-radiated n type devices with 1000 nm of channel length is around of 55 dB and this value was reduced to 40 dB on 1000 nm of channel length radiated devices. The main influence on voltage intrinsic gain degradation due to change on output conduction on 1000 nm of channel length radiated devices.
APA, Harvard, Vancouver, ISO, and other styles
4

Huang, Ming-Jiu, and 黃明俥. "The Optical Responses of Dual-Gate and Triple-Gate Carbon Nanotube Thin Film Transistors and its Correlation with Electrical Behaviors." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/31221307755751646598.

Full text
Abstract:
碩士
清雲科技大學
電子工程研究所
95
In recent years, carbon nanotube field effect transistors (CNT-FETs) had great advance in emission light. But the mechanism of optical responses and its correlation with the FET’s electrical behavior are still unclear. In this thesis, we design the dual-gate and triple-gate structure in our CNT FETs and then measure their electrical and optical responses. First, the FET is screened by traditional tri-point measurement. Based on their Id-Vds characteristics and on/off current ratio, those devices are classified as metal, semiconductor and ambipolar and unipolar type ones. Then the extra second or third narrow-gates which are located near source, drain or midpoint are biased with different voltage and the electrical curves of multiple-gate devices are collected. Under different gate bias configuration, optical responses of the CNT FETs with single and multiple gate configurations are measured with/without a halogen light illumination. The optical performances of CNTFETs are sorted by their maximum photo-to-dark ratio. As the top-gate electrode of the device is located on the middle region of CNT, the CNTFETs have the higher optical responses then the others. It means that the source-CNT or drain-CNT interfaces are more sensible part than the CNT itself. Next, some devices show that the drain current decreases under illumination and the photo-to dark ratio is less than 1. To verify this problem, the Id-Vg curves are colleted and it is found that as the gate voltage sweeping from -10V to 10V and 10V to -10V, the “hysteresis loop” of curve is shrunk under illumination. In the “on” state of the CNTFETs（Vg > 0 and Vg is sweeping from -10V to +10V）, the drain current decreases under illumination. It means that the extra potential barriers are arisen under illumination and these barrier will retard the drain current flow.
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Triple gate transistor"

1

Dutta, Ritam, and Nitai Paitya. "Effect of Pocket Intrinsic Doping on Double and Triple Gate Tunnel Field Effect Transistors." In Lecture Notes in Electrical Engineering, 249–58. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0829-5_25.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Saraswathi, D., N. B. Balamurugan, G. Lakshmi Priya, and S. Manikandan. "A Compact Analytical Model for 2D Triple Material Surrounding Gate Nanowire Tunnel Field Effect Transistors." In Intelligent Computing and Applications, 325–32. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2268-2_35.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Dutta, Ritam, and Nitai Paitya. "Novel InAs/Si Heterojunction Dual-Gate Triple Metal P-i-N Tunneling Graphene Nanoribbon Field Effect Transistοr (DG-TM-TGNFET) Fοr High-Frequency Applicatiοns." In Lecture Notes in Electrical Engineering, 251–62. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-4947-9_17.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Kandpal, Jyoti, and Ekta Goel. "Transition from Conventional FETs to Novel FETs, SOI, Double Gate, Triple Gate, and GAA FETS." In Nanoscale Field Effect Transistors: Emerging Applications, 25–46. BENTHAM SCIENCE PUBLISHERS, 2023. http://dx.doi.org/10.2174/9789815165647123010005.

Full text
Abstract:
Low-power application devices and inexpensive transistors are essential for today's technological world. A 3 nm MOSFET nanoelectronic device has just been created by researchers. Even though a MOSFET shrinks in size and uses less power, SCEs still cause a few problems, leakage current, including Hot electron, Impact Ionization, threshold voltage roll-off, Drain Induced Barrier Lowering (DIBL), and others. One of the best-proposed structures to replace the MOSFET structure is the FIN FET structure, which overcomes the limitations brought on by the CMOS transistor. For low-power applications, the FIN FET structure is ideal. A FINFET structure achieves an average subthreshold swing of 60 mv/decade at room temperature beyond the boundaries of CMOS. This paper examines the performance of the many FINFET architectures that have been proposed, including the double gate, tri-gate, and Gate All Around FET.
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Triple gate transistor"

1

Bin Kashem, Md Tashfiq, and Samia Subrina. "Characteristics of Triple Material Gate AlGaN/GaN High Electron Mobility Transistor." In 2015 International Conference on Advances in Electrical Engineering (ICAEE). IEEE, 2015. http://dx.doi.org/10.1109/icaee.2015.7506867.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Dewan, Monzurul Islam, Md Tashfiq Bin Kashem, and Samia Subrina. "Characteristic analysis of triple material tri-gate junctionless tunnel field effect transistor." In 2016 9th International Conference on Electrical and Computer Engineering (ICECE). IEEE, 2016. http://dx.doi.org/10.1109/icece.2016.7853924.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Okuyama, Kiyoshi, Koji Yoshikawa, and Hideo Sunami. "Proposal of 3-Dimensional Independent Triple-Gate MOS Transistor with Dynamic Current Control." In 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA). IEEE, 2007. http://dx.doi.org/10.1109/vtsa.2007.378951.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Malik, Gul Faroz Ahmad, Mubashir Ahmad, Farooq Ahmad Khanday, and Nusrat Parveen. "Simulation of Triple Gate Spin Field-Effect Transistor and its Applications to Digital Logic." In 2020 IEEE VLSI Device Circuit and System (VLSI DCS). IEEE, 2020. http://dx.doi.org/10.1109/vlsidcs47293.2020.9179894.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Chatterjee, Soumya, Sreyan Ray, Sovan Kumar Dey, Subhadip Hazra, Soumik Kar, and Sulagna Chatterjee. "Triple gate Field Effect Transistor (TGFET) with voltage control potential wells (VCPWs) along the channel." In 2016 IEEE 7th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON). IEEE, 2016. http://dx.doi.org/10.1109/iemcon.2016.7746348.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Berthollet, F., S. Cremer, G. Bossu, J. P. Carrere, D. Jeanjean, L. Pinzel, R. Pantel, F. Lalanne, C. Plossu, and A. Poncet. "Low cost and high performance p-doped triple-gate access transistor for embedded DRAM memory cell." In 2009 Proceedings of the European Solid State Device Research Conference (ESSDERC). IEEE, 2009. http://dx.doi.org/10.1109/essderc.2009.5331317.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Chang, C. H., C. Y. Chou, C. N. Han, C. T. Peng, and Kuo-Ning Chiang. "Local-strain effect of the SiN/Si stacking and nanoscale triple gate Si/SiGe MOS transistor." In Microelectronics, MEMS, and Nanotechnology, edited by Alex J. Hariz. SPIE, 2005. http://dx.doi.org/10.1117/12.638567.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Lamba, V. K., Derick Engles, and S. S. Malik. "Modeling and Designing a Device Using MuGFETs." In ASME 2008 3rd Energy Nanotechnology International Conference collocated with the Heat Transfer, Fluids Engineering, and Energy Sustainability Conferences. ASMEDC, 2008. http://dx.doi.org/10.1115/enic2008-53015.

Full text
Abstract:
This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.
APA, Harvard, Vancouver, ISO, and other styles
9

Paz, Bruna Cardoso, Marcelo Antonio Pavanello, Mikael Casse, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, Fernando Avila-Herrera, and Antonio Cerdeira. "From double to triple gate: Modeling junctionless nanowire transistors." In 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, 2015. http://dx.doi.org/10.1109/ulis.2015.7063759.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Chen, Chang-Nian, Ji-Tian Han, Wei-Ping Gong, and Tien-Chien Jen. "Heat Transfer and Hydraulic Characteristics of Cooling Water in a Flat Plate Heat Sink for High Heat Flux IGBT." In ASME 2016 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2016. http://dx.doi.org/10.1115/imece2016-66717.

Full text
Abstract:
High heat flux is very dangerous for electronic heat transfer, such as IGBT (Insulated Gate Bipolar Transistor) cooling. In order to explore and master the heat transfer and hydraulic characteristics for IGBT cooling, experiments have been carried out to study the situation mentioned above in a flat plate heat sink, which was designed for high heat flux IGBT cooling. The geometrical parameters of the test section are as follows: outline dimension 229 mm × 124 mm × 30 mm; flow channels of 229 mm × 3 mm × 4 mm in total of 20. The experiments performed at atmospheric pressure and with inlet temperatures of 25–35°C, heat fluxes of 3.5–18.9 kW/m2. The influence of temperatures, heat fluxes on IGBT surface temperature and the cooling effect of the liquid cold plate have been investigated under a range of flow rates of 280–2300 kg/m2s. It was found that the heat transfer enhancement was very obvious using this kind of small sized channel for IGBT cooling, which was tens of times of the effect than air cooling or triple of the effect than that in normal sized channels. And the heat transfer enhancement increases with increasing heat fluxes and flow rates, while it decreases with increasing inlet temperatures. Most of the experimental results show good cooling effect as expected. However, it is dangerous for the cooling system under high heat fluxes when the system starts or stops suddenly, when the Respond Time (RT) is less than 5 seconds to cut off heated power. Also, the cooling performance is bad when the heat fluxes increased greatly, which is considered as abnormal situation in operating. The effect on IGBT surface temperature of heat flux is more obvious when the average Nusselt Number is smaller. For hydraulic characteristics observed, it was found that the flow friction increased with flow rates increasing, but the pressure drops of heated flow channels ahead were slightly larger than those back, especially under large flow rates conditions. That is because the temperatures of flow heated in channels ahead are lower than those back, which causes the fluid viscosity to be higher. At last, this paper suggested a series of method for enhancing heat transfer in flat plate heat sink, and also gave some ways to avoid heat transfer dangerous situations for IGBT cooling, which can provide a basis for thermodynamic and hydraulic calculation of flat plate heat sink design and lectotype.
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Triple gate transistor' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography