Journal articles: 'Transistors'

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Vukic, Vladimir, and Predrag Osmokrovic. "Power lateral pnp transistor operating with high current density in irradiated voltage regulator." Nuclear Technology and Radiation Protection 28, no. 2 (2013): 146–57. http://dx.doi.org/10.2298/ntrp1302146v.

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The operation of power lateral pnp transistors in gamma radiation field was examined by detection of the minimum dropout voltage on heavily loaded low-dropout voltage regulators LM2940CT5, clearly demonstrating their low radiation hardness, with unacceptably low values of output voltage and collector-emitter voltage volatility. In conjunction with previous results on base current and forward emitter current gain of serial transistors, it was possible to determine the positive influence of high load current on a slight improvement of voltage regulator LM2940CT5 radiation hardness. The high-current flow through the wide emitter aluminum contact of the serial transistor above the isolation oxide caused intensive annealing of the positive oxide-trapped charge, leading to decrease of the lateral pnp transistor's current gain, but also a more intensive recovery of the small-signal npn transistors in the control circuit. The high current density in the base area of the lateral pnp transistor immediately below the isolation oxide decreased the concentration of negative interface traps. Consequently, the positive influence of the reduced concentration of the oxide-trapped charge on the negative feedback reaction circuit, together with the favourable effect of reduced interface traps concentration, exceeded negative influence of the annealed oxide-trapped charge on the serial pnp transistor's forward emitter current gain.

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Knyaginin, D. A., E. A. Kulchenkov, S. B. Rybalka, and A. A. Demidov. "Study of characteristics of n-p-n type bipolar power transistor in small-sized metalpolymeric package type SOT-89." Journal of Physics: Conference Series 2086, no. 1 (December 1, 2021): 012057. http://dx.doi.org/10.1088/1742-6596/2086/1/012057.

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Abstract In this study the input, output and current gain characteristics of silicon n-p-n type medium power bipolar junction transistors KT242A91 made by the "GRUPPA KREMNY EL" in modern small-sized metalpolymeric package type (SOT-89) have been obtained. The SPICE model that allows simulating realistic transistor behaviour of n-p-n type transistor KT242A91 has been proposed. It is shown that established experimental characteristics for KT242A91 transistor correspond to similar transistor’s type characteristics.

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Horng. "Thin Film Transistor." Crystals 9, no. 8 (August 9, 2019): 415. http://dx.doi.org/10.3390/cryst9080415.

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The special issue is "Thin Film Transistor". There are eight contributed papers. They focus on organic thin film transistors, fluorinated oligothiophenes transistors, surface treated or hydrogen effect on oxide-semiconductor-based thin film transistors, and their corresponding application in flat panel displays and optical detecting. The present special issue on “Thin Film Transistor” can be considered as a status report reviewing the progress that has been made recently on thin film transistor technology. These papers can provide the readers with more research information and corresponding application potential about Thin Film Transistors.

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BLALOCK, BENJAMIN J., SORIN CRISTOLOVEANU, BRIAN M. DUFRENE, F. ALLIBERT, and MOHAMMAD M. MOJARRADI. "THE MULTIPLE-GATE MOS-JFET TRANSISTOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 511–20. http://dx.doi.org/10.1142/s0129156402001423.

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A new SOI device, the MOS-JFET, has been developed that combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body. A unique attribute of the MOS-JFET is that it can be viewed as a four gate transistor (two side junction-based gates, the top MOS gate, and the back gate activated by SOI substrate biasing). Each of these four gates can control the conduction characteristics of the transistor. This novel transistor's multiple gate inputs give rise to exciting circuit opportunities for analog, RF, mixed-signal, and digital applications. Measured results of MOS-JFET transistors, fabricated in a conventional partially-depleted SOI technology, demonstrate that the device is fully operational. From the experiments and systematic 2-D simulations, typical regions of operation are identified. These results indicate that optimum performance is reached when the MOS and junction field-effects are combined.

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Arunabala, Dr C. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed." International Journal of Innovative Technology and Exploring Engineering 10, no. 5 (March 30, 2021): 87–92. http://dx.doi.org/10.35940/ijitee.e8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor count optimized such that the constraints get optimized results. By using the AND, OR, XOR, 4X1 MUX and full adder modules with reduced transistor count we designed the one bit ALU. With one bit ALU we designed 4 bit ALU and compared the outcomes with conventional 4 bit ALU design so that the proposed 4 bit ALU design has optimized transistor count, area, power, delay and power delay product (PDP). Simulations are verified through 130nm mentor graphics tool.

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Fadil, Dalal, Wlodek Strupinski, Emiliano Pallecchi, and Henri Happy. "Analysis of Local Properties and Performance of Bilayer Epitaxial Graphene Field Effect Transistors on SiC." Materials 17, no. 14 (July 18, 2024): 3553. http://dx.doi.org/10.3390/ma17143553.

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Epitaxial bilayer graphene, grown by chemical vapor deposition on SiC substrates without silicon sublimation, is crucial material for graphene field effect transistors (GFETs). Rigorous characterization methods, such as atomic force microscopy and Raman spectroscopy, confirm the exceptional quality of this graphene. Post-nanofabrication, extensive evaluation of DC and high-frequency properties enable the extraction of critical parameters such as the current gain (fmax) and cut-off frequency (ft) of hundred transistors. The Raman spectra analysis provides insights into material property, which correlate with Hall mobilities, carrier densities, contact resistance and sheet resistance and highlights graphene’s intrinsic properties. The GFETs’ performance displays dispersion, as confirmed through the characterization of multiple transistors. Since the Raman analysis shows relatively homogeneous surface, the variation in Hall mobility, carrier densities and contact resistance cross the wafer suggest that the dispersion of GFET transistor’s performance could be related to the process of fabrication. Such insights are especially critical in integrated circuits, where consistent transistor performance is vital due to the presence of circuit elements like inductance, capacitance and coplanar waveguides often distributed across the same wafer.

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Tappertzhofen, S., L. Nielen, I. Valov, and R. Waser. "Memristively programmable transistors." Nanotechnology 33, no. 4 (November 5, 2021): 045203. http://dx.doi.org/10.1088/1361-6528/ac317f.

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Abstract When designing the gate-dielectric of a floating-gate-transistor, one must make a tradeoff between the necessity of providing an ultra-small leakage current behavior for long state retention, and a moderate to high tunneling-rate for fast programming speed. Here we report on a memristively programmable transistor that overcomes this tradeoff. The operation principle is comparable to floating-gate-transistors, but the advantage of the analyzed concept is that ions instead of electrons are used for programming. Since the mass of ions is significantly larger than the effective mass of electrons, gate-dielectrics with higher leakage current levels can be used. We demonstrate the practical feasibility of the device using a proof-of-concept study based on a micrometer-sized thin-film transistor and LT-Spice simulations of 32 nm transistors. Memristively programmable transistors have the potential of high programming endurance and retention times, fast programming speeds, and high scalability.

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Yarmukhamedov, A., A. Zhabborov, and B. Turimbetov. "EXPERIMENTAL RESEARCH AND COMPUTER SIMULATION OF MULTI-CASCADE COMPOSITE TRANSISTORS FOR STABILIZING THE OPERATING MODE OF OUTPUT CASCADES OF RADIO ENGINEERING DEVICES." Technical science and innovation 2019, no. 1 (June 11, 2019): 33–42. http://dx.doi.org/10.51346/tstu-01.18.2.-77-0009.

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Experimental results and computer simulation of multi-stage composite transistors are presented. To study the volt - ampere characteristics of multistage composite transistors, a dialogue computer simulation program, the Delphi programming environment, has been developed. It is shown that the proposed multistage composite transistors can improve manufacturability in its industrial production. It is shown that multistage homostructure transistors according to the Darlington and Shiklai circuits operate stably at collector-emitter voltages five times higher than in the case of individual transistors. The power dissipated on the collector is 3 times higher than the rated value of the maximum permissible power of the composite transistors. It is established that the efficiency of the method of stabilizing the emitter current of a three-link homostructure transistor is 7 times higher in voltage and three orders of magnitude higher in temperature compared to a conventional composite transistor. The proposed homostructure transistors are designed to operate in terminal stages of power amplifiers, radio transmitting devices, electronic equipment of industrial and automotive electronics

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Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, Daniel Albrecht, Hendrik Hölscher, Jürgen Leuthold, and Thomas Schimmel. "Copper atomic-scale transistors." Beilstein Journal of Nanotechnology 8 (March 1, 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.

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We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

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Hebali, Mourad, Menaouer Bennaoum, Mohammed Berka, Abdelkader Baghdad Bey, Mohammed Benzohra, Djilali Chalabi, and Abdelkader Saidane. "A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model." Journal of Electrical Engineering 70, no. 2 (April 1, 2019): 145–51. http://dx.doi.org/10.2478/jee-2019-0021.

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Abstract In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and gm–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.

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Balti, M., D. Pasquet, and A. Samet. "PROPAGATION EFFECTS ON Z PARAMETERS IN AN FET EQUIVALENT CIRCUIT." SYNCHROINFO JOURNAL 7, no. 5 (2021): 21–25. http://dx.doi.org/10.36724/2664-066x-2021-7-5-21-25.

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The design of microwave circuits needs a good analysis of the performances of the field-effect transistor equivalent circuit. Indeed the small signal equivalent circuit of the field-effect transistors makes it possible to easily determine their performances such as the gain and the noise figure. A field-effect transistor constitutes a propagation structure along its gate width. Telegraphists’ equations are solved for this structure. One deduces from this the effect of the propagation on the transistor Z-parameters which can be taken into account in electric simulations and which may improve the use of long transistors at lower frequencies and of short transistors at higher frequencies.

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Choi, Woo Young. "Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage." Micromachines 11, no. 6 (May 27, 2020): 543. http://dx.doi.org/10.3390/mi11060543.

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This study proposes negative capacitance vacuum channel transistors. The proposed negative capacitance vacuum channel transistors in which a ferroelectric capacitor is connected in series to the gate of the vacuum channel transistors have the following two advantages: first, adding a ferroelectric capacitor in series with a gate capacitor makes the turn-on voltage lower and on–off transition steeper without causing hysteresis effects. Second, the capacitance matching between a ferroelectric capacitor and a vacuum channel transistor becomes simplified because the capacitance of a vacuum channel transistor as seen from a ferroelectric capacitor is constant.

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Lin, Jinhan. "Advancement and Challenges of Field Effect Transistors based on Multi-gate Transistor." Journal of Physics: Conference Series 2370, no. 1 (November 1, 2022): 012004. http://dx.doi.org/10.1088/1742-6596/2370/1/012004.

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The advancement and challenges of field effect transistors are based on multi-gate transistors from the perspective of structure and material. Multi-gate field-effect transistors (Multi-gate FET) have steeper sub-threshold slopes, which can reduce the short channel effect and improve mobility and drive current. A fin field-effect transistor (FinFET) and gate-all-around field-effect transistor (GAAFET) are attractive multi-gate structures most compatible with today’s standard machining technologies. As the future moves towards smaller processes, FinFET and GAAFET processes limit the spacing between n-to-p devices. In order to increase the possibility of transistor miniaturization, innovative structures such as Forksheet FET and Complementary-FET (CFET) have been proposed.

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Bogatyrev, Yu V., D. A. Aharodnikau, S. B. Lastovsky, A. V. Ket’ko, M. M. Krechko, S. V. Shpakovsky, P. V. Rubanov, G. A. Protopopov, and P. A. Chubunov. "Influence of ionizing radiation on the parameters of p-channel MOS transistors." Proceedings of the National Academy of Sciences of Belarus, Physical-Technical Series 67, no. 4 (January 2, 2023): 402–8. http://dx.doi.org/10.29235/1561-8358-2022-67-4-402-408.

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The results of experimental studies of the influence of gamma radiation Co60 on the basic parameters of silicon epitaxial-planar p-channel MOSFET transistors under different electrical modes are presented. Transistors were manufactured according to radiation-resistant DMOS technology with design standards of 1.4 μm. As a result of transistor studies, it was established that the values of all basic parameters after the radiation dose D = 106 rads (SiO2) in active electrical irradiation modes remained within the limits of the performance criteria; the parameter, most sensitive to influence of a dose of irradiation by gamma-quanta is the threshold voltage; in the passive electrical irradiation mode the transistor’s radiations resistance in all parameters corresponds to a dose of 2,8·106 rads (SiO2). A sufficiently high radiation resistance of the studied p-channel MOSFETs makes it possible to recommend them for use in aviation and space equipment. The different degrees of radiation degradation of the studied parameters during irradiation are due to their dependence either on the effects of ionization in the layers of sub-gate and insulating dielectrics, or structural damage in the bulk silicon of the transistor active regions. The high radiation resistance of the studied p-channel MOSFETs allows recommending them for use in aviation and space equipment.

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Cunţan, C. D., I. Baciu, and M. Osaci. "Study of MOS and IGBT transistors at switching with variable duty cycle." Journal of Physics: Conference Series 2714, no. 1 (February 1, 2024): 012010. http://dx.doi.org/10.1088/1742-6596/2714/1/012010.

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Abstract In this paper, the functionality of MOS and IGBT transistors is examined under identical working conditions, both in terms of command frequency and load circuit. A variable duty cycle and variable frequency signal generator is used to control transistors. Various electronic components and Arduino-UNO modules, as well as the 16×2 LCD screen, were used to create the signal generator. The control signal is amplified by a current amplifier to adapt the output voltage to the value required to control the transistors. The operation of MOS and IGBT transistors at various operating frequencies with resistive or inductive loads is compared. Thus, the communication times of the transistor capsules were determined at various operating temperatures. The temperature was determined indirectly by connecting a thermistor to the transistor capsule.

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Maftunzada, S. A. L. "The Structure and Working Principle of a Bipolar Junction Transistor (BJT)." Physical Science International Journal 26, no. 11-12 (December 31, 2022): 35–39. http://dx.doi.org/10.9734/psij/2022/v26i11-12772.

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We studied bipolar junction transistors. We will see that the bipolar junction transistor, often referred to by its short name, transistor, actually functions as a current-controlled current source. We will also see that in the current generation of bipolar junction transistors, both majority and minority carriers are involved. For this reason, they gave this name to this type of transistor. In order to get enough information about this part, in the first two parts we will examine the construction and working method of the transistor. After that, we dedicate sections to how the transistor is placed in different combinations and the characteristics of the transistor in each combination.

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Dallaire, Nicholas J., Samantha Brixi, Martin Claus, Stefan Blawid, and Benoît H. Lessard. "Benchmarking contact quality in N-type organic thin film transistors through an improved virtual-source emission-diffusion model." Applied Physics Reviews 9, no. 1 (March 2022): 011418. http://dx.doi.org/10.1063/5.0078907.

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Due to nonideal behavior, current organic thin film transistor technologies lack the proper models for essential characterization and thus suffer from a poorly estimated parameter extraction critical for circuit design and integration. Organic thin film transistors are often plagued by contact resistance, which is often less problematic in inorganic transistors; consequently, common models used for describing inorganic devices do not properly work with organic thin film transistors. In this work, we fabricate poly{[ N, N′-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)} based organic thin film transistors with reduced contact resistance through the introduction of metallic interlayers between the semiconductor and gold contacts. The addition of 10 nm thick manganese interlayer provides optimal organic thin film transistor device performance with the lowest level of contact resistance. Improved organic thin film transistors were characterized using an improved organic virtual-source emission diffusion model, which provides a simple and effective method to extract the critical device parameters. The organic virtual-source emission diffusion model led to nearly perfect prediction using effective gate voltages and a gate dependant contact resistance, providing a significant improvement over common metal–oxide–semiconductor field-effect transistor models such as the Shichman–Hodges model.

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Kumrey, G. R., and S. K. Mahobia. "STUDY AND PERFORMANCE TESTING OF TRANSISTOR WITH COMMON EMITTER AMPLIFIER CIRCUIT." International Journal of Research -GRANTHAALAYAH 4, no. 8 (August 31, 2016): 100–103. http://dx.doi.org/10.29121/granthaalayah.v4.i8.2016.2567.

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The transistor has ranking in 20th century technology. It is finding the application in all electronic devices as radios, computers. Integrated circuits are containing various transistors, which are made by silicon. The transistors are used to handle large current and/or large voltages. As example, the final audio stage in the stereo system used a power transistors amplifier to drive the various speakers. Transistors are device, which are utilizes a change in current to produce a large change in voltage, current, or power.

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Liou, Juin J., and Frank Schwierz. "Evolution and recent advances in RF/microwave transistors." Journal of Telecommunications and Information Technology, no. 1 (March 30, 2004): 99–105. http://dx.doi.org/10.26636/jtit.2004.1.224.

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Most applications for radio frequency/microwave (thereafter called RF) transistors had been military oriented in the early 1980s. Recently, this has been changed drastically due to the explosive growth of the markets for civil wireless communication systems. This paper gives an overview on the evolution, current status, and future trend of transistors used in RF electronic systems. Important background, development and major milestones leading to modern RF transistors are presented. The concept of heterostructure, a feature frequently used in RF transistors, is discussed. The different transistor types and their figures of merit are then addressed. Finally an outlook of expected future developments and applications of RF transistors is given.

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Hassinen, Tomi, Ari Alastalo, Kim Eiroma, Tiia-Maria Tenhunen, Vesa Kunnari, Timo Kaljunen, Ulla Forsström, and Tekla Tammelin. "All-Printed Transistors on Nano Cellulose Substrate." MRS Advances 1, no. 10 (December 28, 2015): 645–50. http://dx.doi.org/10.1557/adv.2015.31.

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ABSTRACTWe report fully-printed top-gate-bottom-contact organic thin-film transistors using substrates prepared from cellulose nanofibers and commercially available printing inks to fabricate the devices. Gravure printing was used to coat the substrate with a polymer resist to decrease the surface roughness and close the surface. Transistor structures were fabricated using inkjet printing for conductors and gravure printing for the dielectric and semiconducting layers. The obtained transistor performance is compared to that of similar transistors on plastic substrate.

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Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (March 31, 2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.

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For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.

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Sergeev, Vyacheslav A., Alexander M. Hodakov, Ilya V. Frolov, and Alexander A. Kazankov. "Current distribution in comb structures of bipolar and heterobipolar microwave transistors taking into account the metallization tracks resistance." Radioelectronics. Nanosystems. Information Technologies. 16, no. 3 (May 19, 2024): 317–24. http://dx.doi.org/10.17725/j.rensit.2024.16.317.

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A brief analysis of the causes of inhomogeneous and unstable current distribution between elementary transistors in comb structures (CS) of bipolar (BT) and heterobipolar (HBT) microwave transistors is presented. An expression for the current flowing into a CS elementary transistor, taking into account the emitter track metallization resistance, is derived. An estimation of the influence of technological variation of emitter metallization track resistances on the non-uniformity of the transistor total current distribution between elementary transistors is given. It is shown that resistance of emitter tracks of metallization plays a stabilizing role and leads to increase of thermal stability of current distribution in CS, thus the least stable to thermal breakdown will be elementary transistor of CS with the least resistance of emitter track and the greatest thermal resistance. Recommendations on equalization and increase of stability of current distribution in CS of BT and HBT are offered.

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Hashim, Yasir, and Othman Sidek. "Dimensional Effect on DIBL in Silicon Nanowire Transistors." Advanced Materials Research 626 (December 2012): 190–94. http://dx.doi.org/10.4028/www.scientific.net/amr.626.190.

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Drain-induced barrier lowering (DIBL) is crucial in many applications of silicon nanowire transistors. This paper determined the effect of the dimensions of nanowires on DIBL. The MuGFET simulation tool was used to investigate the characteristics of the transistors. The transfer characteristics of transistors with different dimensions were simulated. The results show that longer nanowires with smaller diameters and lower oxide thickness decrease DIBL and tend to possess the best transistor characteristics.

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Nowbahari, Arian, Avisek Roy, and Luca Marchetti. "Junctionless Transistors: State-of-the-Art." Electronics 9, no. 7 (July 19, 2020): 1174. http://dx.doi.org/10.3390/electronics9071174.

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Kapen, Tilegen Abaiuly. "INSULATED-GATE BIPOLAR TRANSISTOR." Chronos 7, no. 8(70) (October 13, 2022): 32–35. http://dx.doi.org/10.52013/2658-7556-70-8-12.

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Insulated-gate bipolar transistor is a cunningly composed hybrid of field-effect and bipolar transistors. At the same time, it has adopted the main advantages of the two main types of transistors and has found wide application in high-power and high-voltage devices.

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Mondzik, Andrzej. "T-NPC Soft-Commutated Inverter Based on Reverse Blocking IGBTs with the Novel Concept of a DESAT Control Circuit in the Gate Driver." Energies 16, no. 12 (June 11, 2023): 4642. http://dx.doi.org/10.3390/en16124642.

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This article presents the concept of switching and conduction loss reduction in a T-NPC inverter based on IGBT transistors. The method of limiting switching losses involves the connection of an LC circuit designed to cause transistors in vertical branches to shut down under zero voltage conditions. In order to reduce conduction losses, it was proposed to use two reverse blocking transistors connected anti-parallel in the horizontal branch of the inverter. To ensure safe operation of the transistors, a gate driver proposal for controlling the IGBT reverse blocking transistor is presented. The solution is characterized by a changed part of the driver, responsible for short-circuit protection. It eliminates excessive, destructive currents that can potentially flow through the driver circuit under the influence of the power supply voltage of the power circuit connected backwards to the controlled transistor. Examples of applications and benefits of the proposed solution are presented and verified with laboratory tests.

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Park, ChangMin, SeHan Lee, MinSu Choi, MyungGil Kang, YoungChai Jung, SungWoo Hwang, Doyeol Ahn, JungHyeon Lee, and ChangRyong Song. "Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates." Journal of Nanoscience and Nanotechnology 7, no. 11 (November 1, 2007): 4150–53. http://dx.doi.org/10.1166/jnn.2007.015.

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We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

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Park, ChangMin, SeHan Lee, MinSu Choi, MyungGil Kang, YoungChai Jung, SungWoo Hwang, Doyeol Ahn, JungHyeon Lee, and ChangRyong Song. "Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates." Journal of Nanoscience and Nanotechnology 7, no. 11 (November 1, 2007): 4150–53. http://dx.doi.org/10.1166/jnn.2007.18093.

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We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

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Hanko, Branislav, Michal Frivaldsky, and Jan Morgos. "Evaluation of the Efficiency Performance of 3-Phase, 6-Switch PFC Circuit Based on the Used 1.2 kV SiC Transistor." Electronics 11, no. 3 (January 25, 2022): 363. http://dx.doi.org/10.3390/electronics11030363.

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This paper evaluates the performance of the high-voltage wide-band gap SiC power transistors equipped within 3-phase bridgeless 3 kW PFC circuit. The main aim of the study is the experimental evaluation of the dynamic properties and driving power requirements of the transistors, for which the parameters are similar. These are competing products from different manufacturers, while the selection criterion was the same type of package technology (7 pin D2PAK). Second, the effect of the transistor type was analysed in terms of the performance efficiency of the PFC circuit. Within the analysis, the driver circuit was constructed first, and adapted to high voltage transistor driving. During individual measurements, the driver remained the same, while gate-driver losses were analysed for individual transistors. The obtained results reveal differences related to requirements on driving power, as well as to the dynamics of transistors themselves. At the end of the paper, the evaluation of efficiency for different operating conditions of a constructed PFC converter is realized. The obtained results provide a more detailed overview of the dynamic properties of transistors and their impact on the resulting efficiency of the main circuit also in terms of driving requirements.

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Suman, Dr J. V., and Nekkali Ramya. "Harnessing Tunnel Field-Effect Transistors for Boolean Function Implementation." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (December 30, 2023): 1–13. http://dx.doi.org/10.55041/ijsrem27821.

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In the pursuit of advancing digital integrated circuits, the exploration of novel transistor technologies has become imperative. It presents a comprehensive exploration of the implementation of Boolean functions utilizing Tunnel Field-Effect Transistors (TFETs). TFETs offer unique advantages over traditional MOSFETs, such as reduced leakage current and lower power consumption, making them a promising candidate for next-generation digital circuitry.The acronym "DGTFET" typically stands for "Double Gate Tunnel Field-Effect Transistor." A Double Gate Tunnel Field-Effect Transistor is a type of transistor that has two gate electrodes instead of one, allowing for better control of the flow of electrical current. This design offers advantages in terms of improved performance, reduced leakage current, and enhanced scalability, making it suitable for advanced semiconductor applications. we also used twin double gate structures when implementing Boolean functions with Tunnel Field-Effect Transistors (TFETs) is like giving TFETs a special setup that makes them work better for making digital circuits. Keywords: Tunnel Field-Effect Transistors (TFETs),Boolean Functions,Digital Circuit Design,Low- Power Implementation,CMOS Integration

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Hähnlein, Bernd, Benjamin Händel, Frank Schwierz, and Jörg Pezoldt. "Properties of Graphene Side Gate Transistors." Materials Science Forum 740-742 (January 2013): 1028–31. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.1028.

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Epitaxial graphene grown on semiinsulating silicon carbide was used to fabricate side gate graphene transistors. The transconductance of the side gate transistors is comparable to top gate designs. The transconductance decreases with increasing gate width independently on the gate to channel distance in agreement with the transconductance reduction in top gate transistor configu¬rations with increasing channel length. The transconductance of the side gate transistors decreases with increasing channel width due to a decreased specific gate capacitance.

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Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (May 20, 2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nanodimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

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Burg, David, and Jesse H. Ausubel. "Moore’s Law revisited through Intel chip density." PLOS ONE 16, no. 8 (August 18, 2021): e0256245. http://dx.doi.org/10.1371/journal.pone.0256245.

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Gordon Moore famously observed that the number of transistors in state-of-the-art integrated circuits (units per chip) increases exponentially, doubling every 12–24 months. Analysts have debated whether simple exponential growth describes the dynamics of computer processor evolution. We note that the increase encompasses two related phenomena, integration of larger numbers of transistors and transistor miniaturization. Growth in the number of transistors per unit area, or chip density, allows examination of the evolution with a single measure. Density of Intel processors between 1959 and 2013 are consistent with a biphasic sigmoidal curve with characteristic times of 9.5 years. During each stage, transistor density increased at least tenfold within approximately six years, followed by at least three years with negligible growth rates. The six waves of transistor density increase account for and give insight into the underlying processes driving advances in processor manufacturing and point to future limits that might be overcome.

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Hasan, Ghanim Thiab, Ali Hlal Mutlaq, and Kamil Jadu Ali. "Comparative evaluation of SiC/GaN “MOSFET” transistors under different switching conditions." Bulletin of Electrical Engineering and Informatics 11, no. 2 (April 1, 2022): 681–90. http://dx.doi.org/10.11591/eei.v11i2.3445.

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The aim of this paper is to conduct a mutual comparison of switching energy losses in cascade gallium nitride (GaN) and silicon "super junction" MOSFET” transistor, in both cases designed for a maximum operating voltage of (650 V). For the analysis of switching characteristics of transistors used double pulse test method by using detailed SPICE simulation model. Data on transient on and off processes were generated using the “LTspice” simulation package in a wide range of drain currents with two different gate resistance values of the tested transistors. The total energy losses in the GaN have been simulated during one transistor at (on and off cycle). The obtained results indicate that the superior switching characteristics of GaN devices for a drain current of (30 A) is five to eight times less than the switching characteristics of silicon “MOSFET” transistor when compared to silicon components, especially during operation of transistors with high drain currents.

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Wang, Yao, Yuedan Wang, Rufeng Zhu, and Dong Wang. "Research progress of fibre-based organic electrochemical transistors." Wearable Technology 2, no. 2 (June 16, 2022): 67. http://dx.doi.org/10.54517/wt.v2i2.1650.

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<p>Organic electrochemical transistors are flexible in design with characteristics such as miniaturisation, biocompatibility and amplification and are one of the rapidly developing research topics in recent years. As an excellent flexible material, fibre has unparalleled advantages in weaving and compatibility with the human body. Combining fibres with organic electrochemical transistors is a promising research direction that has the high sensitivity of organic electrochemical transistor testing and the human body compatibility and flexibility of wearable electronic products. This paper introduces the relevant operating principles, working modes and commonly used channel materials of organic electrochemical transistors. Based on the basic device structure of organic electrochemical transistors, the development and changes of organic electrochemical transistors in recent years are discussed, and the research results of fibre-based electrochemical transistors by researchers focusing on the application of fibre-based organic electrochemical transistors in chemical sensing, bio-sensing and other application explorations are summarized. Finally, this paper visioned the future development trend of fibre-based organic electrochemical transistors.</p>

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Qi, Cheng, Yaswanth Rangineni, Gary Goncher, Raj Solanki, Kurt Langworthy, and Jay Jordan. "SiGe Nanowire Field Effect Transistors." Journal of Nanoscience and Nanotechnology 8, no. 1 (January 1, 2008): 457–60. http://dx.doi.org/10.1166/jnn.2008.083.

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Si0.5Ge0.5 nanowires have been utilized to fabricate source-drain channels of p-type field effect transistors (p-FETs). These transistors were fabricated using two methods, focused ion beam (FIB) and electron beam lithography (EBL). The electrical analyses of these devices show field effect transistor characteristics. The boron-doped SiGe p-FETs with a high-k (HfO2) insulator and Pt electrodes, made via FIB produced devices with effective hole mobilities of about 50 cm2V−1s−1. Similar transistors with Ti/Au electrodes made via EBL had effective hole mobilities of about 350 cm2V−1s−1.

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37

Gadgiev, H. M., Sh T. Ismailova, and P. A. Kurbanova. "Kurbanova. Design of energy-efficient high-speed computer equipment based on cost-effective light transistors." Herald of Dagestan State Technical University. Technical Sciences 47, no. 4 (January 21, 2021): 20–26. http://dx.doi.org/10.21822/2073-6185-2020-47-4-20-26.

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Objective. The article deals with the formation of cost-effective light transistors for creating high-speed energy-efficient computer structures that can solve numerous problems with high speed and accuracy. For this purpose, various types of semiconductor structures are used that can emit and absorb photons for receiving and transmitting digital information.Methods. The use of mirror electrodes allows for repeated re-reflection of the generated photons inside the light transistor to recover all the generated energy into electricity. This increases the energy efficiency of the transistor as a whole and allows implementing computer devices with high efficiency in solving various tasks.Results. Most of the useful energy of the information signal is transferred from one electrode to another, and the movement has a higher speed due to the use of photons, rather than drifting electrons, and this indirectly increases the speed of the light transistor by several orders of magnitude and effectively solves the problem of implementing more powerful and high-speed transistors with greater economic benefits.Conclusion. Prospects for the implementation of high-speed energy-efficient computer structures based on both bipolar transistors and unipolar transistors, as well as thyristors, lasers, and other semiconductor components in light-emitting structures have been developed.

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Андреев, А. А., Ю. В. Грищенко, И. C. Езубченко, М. Я. Черных, Е. М. Колобкова, И. О. Майборода, И. А. Черных, and М. Л. Занавескин. "Изучение характеристик транзисторов на гетероструктурах нитрида галлия, выращенных методом аммиачной молекулярно-лучевой эпитаксии на подложках сапфира и кремния." Письма в журнал технической физики 45, no. 4 (2019): 52. http://dx.doi.org/10.21883/pjtf.2019.04.47340.17567.

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AbstractsAmmonia molecular-beam epitaxy has been used to grow gallium nitride (GaN) transistor heterostructures on sapphire and silicon substrates. GaN transistors with a 1.2-mm periphery fabricated on substrates of both types exhibited similar high static characteristics: saturation current density above 0.75 A/mm, transconductance above 300 mS/mm, and breakdown voltage above 120 V. Measurements of the small-signal parameters showed that transistors based on silicon substrates possessed high gain in a frequency range up to 5 GHz; the specific output power at 1 GHz amounted to 5 W/mm for transistors on sapphire substrate and 2 W/mm for transistors on silicon substrate.

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Zanchin, Vinicius Ramos, Marco Roberto Cavallari, and Fernando Josepetti Fonseca. "Stability of Polythiophene-Based Transistors upon Bending for Gas Sensing Applications." Journal of Integrated Circuits and Systems 16, no. 1 (February 22, 2021): 1–6. http://dx.doi.org/10.29292/jics.v16i1.161.

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It is presented herein a fabrication procedure for organic thin film transistors over flexible substrates, as well as an evaluation of the electrical performance upon bending stresses. Top gate/bottom contact flexible transistors of poly(3-hexylthiophene) (P3HT) were successfully fabricated, by carefully tuning organic films drying temperatures, photolithography solvents and the pattern of electrode pads. The transistors were processed over both rigid and flexible substrates for comparison purposes. A P3HT hole mobility approaching 0.01 cm2/Vs was observed for all devices and even on different substrates. In spite of a current modulation of ca. 10, P3HT over poly(ethylene terephthalate) (PET) featured transistor behavior upon bending down to a curvature radius of 8 mm. Bending direction, however, produced different effects on the transistor characteristics, especially on gold electrodes.

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40

Holloway, Peter R. ""One Transistor, Two Transistors, Three"." IEEE Solid-State Circuits Magazine 5, no. 3 (2013): 21–28. http://dx.doi.org/10.1109/mssc.2013.2266056.

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41

Saman, Bander, P. Gogna, El-Sayed Hasaneen, J. Chandy, E. Heller, and F. C. Jain. "Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation." International Journal of High Speed Electronics and Systems 26, no. 03 (June 27, 2017): 1740009. http://dx.doi.org/10.1142/s0129156417400092.

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This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.

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Тарасова, Е. А., С. В. Оболенский, C. В. Хазанова, Н. Н. Григорьева, О. Л. Голиков, А. Б. Иванов, and А. С. Пузанов. "Компенсация нелинейности сток-затворной вольт-амперной характеристики в полевых транзисторах с длиной затвора ~100 нм." Физика и техника полупроводников 54, no. 9 (2020): 968. http://dx.doi.org/10.21883/ftp.2020.09.49841.35.

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Abstract The nonlinearity of the gate–drain current–voltage characteristics in classical Schottky transistors and two-dimensional electron gas field-effect transistors based on AlGaAs/InGaAs/GaAs and InGaAs/GaAs compounds is analyzed. The carrier velocity-overshoot effect in the transistor channel is analyzed for various doping profiles of the structures under study.

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Jurnal, Redaksi Tim. "PERANCANGAN RANGKAIAN PENGUAT DAYA DENGAN TRANSISTOR." Sutet 7, no. 2 (November 27, 2018): 88–92. http://dx.doi.org/10.33322/sutet.v7i2.81.

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The power amplifier circuit is a circuit used to amplify or magnify input signals. The use of a transistor as an amplifier is that the current on the base is used to control the larger current given to the collector through the transistor. The small current change on the controlling base is what is called a large change in the current flowing from the collector to the emitter. The advantages of the amplifier transistors can not only amplify the signal, but these transistors can also be used as current amplifiers, voltage amplifiers and power amplifiers.

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Litvinov, Nikolay, Maksim Solodilov, Aleksey Plotnikov, Sergey Vital'evich Stoyanov, Artem Lapshin, and Roman Ryazancev. "Simulation of the behavior of field-effect transistors when exposed to radiation." Modeling of systems and processes 15, no. 3 (October 5, 2022): 24–34. http://dx.doi.org/10.12737/2219-0767-2022-15-3-24-34.

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The paper deals with the behavior of field-effect transistors under the influence of radiation. The structure of tunnel field-effect transistors, the principle of operation, various effects from exposure to ionization radiation from outer space, and the results of experimental studies of resistance are presented. Field-effect transistors based on single-layer materials such as graphene and MoS2 are also considered. The behavior of field-effect transistors based on graphene is simulated. The paper presents current-voltage characteristics before and after irradiation, at positive and negative voltage at the transistor gate, etc., the analysis of which showed that there were significant changes in the electrical characteristics of transistors and the surface morphology of a single-layer material. The appearance of defects is associated with the heating of the material in the center of the particle track. Similarly, the simulation of the behavior of transistors based on nanotubes, when exposed to radiation, single events appear, was carried out.

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Nerubatskyi, Volodymyr Pavlovych, Olexandr Andrievych Plakhtii, Denys Anatoliiovych Hordiienko, Hryhorii Anatoliiovych Khoruzhevskyi, and Maryna Vitaliyivna Philipjeva. "RESEARCH THE ACCURACY OF MODELING POWER LOSSES IN POWER DIODES AND TRANSISTORS." Collection of Scientific Works of the Ukrainian State University of Railway Transport, no. 203 (March 27, 2023): 73–87. http://dx.doi.org/10.18664/1994-7852.203.2023.277905.

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The methodology for modeling static and dynamic power losses in power IGBT and MOSFET transistors in the Matlab and Multisim software environments is given. It is shown that when modeling switching processes in power transistors, Matlab / Simulink does not allow determining the dynamic components of power losses, namely, the energy of turning on the transistor, the energy of turning off the transistor, as well as the recovery energy of power diodes. At the same time, the simulation of static power losses of power diodes and transistors in Matlab/Simulink is carried out with a significant error due to incorrect representation of the current-voltage characteristics. It is shown that for a more correct and accurate simulation of the operation of power transistors, including power losses in power switches, it is more appropriate to conduct simulations in the Multisim software environment, which takes into account more than 47 parameters during simulation, including temperature characteristics, parasitic input and output capacitances and inductances, nonlinearities of current-voltage characteristics and others. In Multisim, a circuit of a half-bridge inverter with power MOSFETs controlled by the IR2104PBF driver has been developed. It is shown that the switching of power transistors is significantly influenced by the parameters of the driver microcircuit, namely the size of the storage capacitor of the driver, as well as the value of the active resistance of the gate resistor. It is shown that the simulation in Multisim correctly displays the transient processes of turning on and off power transistors and reverse recovery of diodes, which allows determining the dynamic losses of power transistors and power diodes.

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Zhang, Jiawei, Joshua Wilson, Gregory Auton, Yiming Wang, Mingsheng Xu, Qian Xin, and Aimin Song. "Extremely high-gain source-gated transistors." Proceedings of the National Academy of Sciences 116, no. 11 (February 25, 2019): 4843–48. http://dx.doi.org/10.1073/pnas.1820756116.

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Despite being a fundamental electronic component for over 70 years, it is still possible to develop different transistor designs, including the addition of a diode-like Schottky source electrode to thin-film transistors. The discovery of a dependence of the source barrier height on the semiconductor thickness and derivation of an analytical theory allow us to propose a design rule to achieve extremely high voltage gain, one of the most important figures of merit for a transistor. Using an oxide semiconductor, an intrinsic gain of 29,000 was obtained, which is orders of magnitude higher than a conventional Si transistor. These same devices demonstrate almost total immunity to negative bias illumination temperature stress, the foremost bottleneck to using oxide semiconductors in major applications, such as display drivers. Furthermore, devices fabricated with channel lengths down to 360 nm display no obvious short-channel effects, another critical factor for high-density integrated circuits and display applications. Finally, although the channel material of conventional transistors must be a semiconductor, by demonstrating a high-performance transistor with a semimetal-like indium tin oxide channel, the range and versatility of materials have been significantly broadened.

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Novosyadlyy, S. P., and A. M. Bosats'kyy. "Graded-Gap TechnologyFormattingof High-Speed GaAs – TransistorStructuresastheBasisforModern of Large Integrated Circuits." Фізика і хімія твердого тіла 16, no. 1 (March 15, 2015): 221–29. http://dx.doi.org/10.15330/pcss.16.1.221-229.

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Reducing the size of silicon devices is accompanied by an increase in the effective rate of electrons, decrease transit time and the transition to a ballistic work.Power consumption is reduced too. Formation of large integrated circuits structures onSi-homotransition reduces their frequency range and performance.Nowadaysproposed several new types of devices and technologies forming of large integrated circuits structures that based on high speeds and mobility of electrons in GaAs, and small size structures.These include, for example, the heterostructure field-effect transistors on a segmented doping, bipolar transistors with wide-emitter, transistor with soulful base, vertical ballistic transistors, devices with flat-doped barriers and hot electron transistors as element base of modern high-speed large integrated circuits.In this article we consider graded-gap technology formatting as bipolar and field-effect transistors, which are the basis of modern high-speedof large integrated circuits structures.

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Brtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs." Journal of Electrical Engineering 64, no. 5 (September 1, 2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.

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Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplified if we consider the lossless transistors or if the y21 -parameter of one transistor is alpha multiple of second ones.

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Xu, Wei, Jingxin Wang, Simin Cheng, and Xiaomin Xu. "Flexible organic transistors for neural activity recording." Applied Physics Reviews 9, no. 3 (September 2022): 031308. http://dx.doi.org/10.1063/5.0102401.

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Flexible electronics capable of interacting with biological tissues, and acquiring and processing biological information, are increasingly demanded to capture the dynamic physiological processes, understand the living organisms, and treat human diseases. Neural interfaces with a high spatiotemporal resolution, extreme mechanical compliance, and biocompatibility are essential for precisely recording brain activity and localizing neuronal patterns that generate pathological brain signals. Organic transistors possess unique advantages in detecting low-amplitude signals at the physiologically relevant time scales in biotic environments, given their inherent amplification capabilities for in situ signal processing, designable flexibility, and biocompatibility features. This review summarizes recent progress in neural activity recording and stimulation enabled by flexible and stretchable organic transistors. We introduce underlying mechanisms for multiple transistor building blocks, followed by an explicit discussion on effective design strategies toward flexible and stretchable organic transistor arrays with improved signal transduction capabilities at the transistor/neural interfaces.

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Xu, Hui, and Guo Rui Wu. "Experimental Measurement and Analysis of Pulse Transmission Source of GPR." Advanced Materials Research 503-504 (April 2012): 1365–68. http://dx.doi.org/10.4028/www.scientific.net/amr.503-504.1365.

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According to the transmission pulse requirements of the impulse-GPR which probes the objectives of shallow soil, a transmission circuit is designed and made. On the basis of the transistor avalanche theory, avalanche transistor and RF transistor are used to generate the impulse-GPR transmission pulse as the core transistors. Trigger pulse is the square wave which is produced by FPGA as the trigger of whole system, its duty ratio under 10% and its frequency from 50 kHz to 500 kHz. As the results of simulation and actual measurement shown, single transistor avalanche circuit and four transistors cascade avalanche circuit can produce a narrow pulse with its pulse width from 1.337ns to 42.91ns. The results meet the transmission pulse requirements of impulse-GPR which probes the objectives of shallow soil.

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Journal articles on the topic 'Transistors'

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