Journal articles: 'Transistor scaling'

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Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (March 31, 2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.

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For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.

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Datta, Suman, Wriddhi Chakraborty, and Marko Radosavljevic. "Toward attojoule switching energy in logic transistors." Science 378, no. 6621 (November 18, 2022): 733–40. http://dx.doi.org/10.1126/science.ade7656.

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Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future.

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SARKOZY, S., X. MEI, W. YOSHIDA, P. H. LIU, M. LANGE, J. LEE, Z. ZHOU, et al. "AMPLIFIER GAIN PER STAGE UP TO 0.5 THz USING 35 NM InP HEMT TRANSISTORS." International Journal of High Speed Electronics and Systems 20, no. 03 (September 2011): 399–404. http://dx.doi.org/10.1142/s0129156411006684.

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Pivotal in the design of circuits is the ability to efficiently translate available transistor gain to high gain per stage. Remarkably, for 35-nm InP HEMT transistors, the efficiency of this translation remains high even up to ~0.5 THz. The ever shrinking wavelength correlated with higher frequencies necessitates a scaling of not only the device layout, but also of the passive elements and wafer thickness. Furthermore, to avoid distributed effects, the length of transistor gate fingers must be reduced.

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Reid, Dave, Campbell Millar, Scott Roy, Gareth Roy, Richard Sinnott, Gordon Stewart, Graeme Stewart, and Asen Asenov. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (June 28, 2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.

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The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project and describes the way in which the scientific goals have been reflected in the grid-based e-Infrastructure.

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Fazio, Al. "Flash Memory Scaling." MRS Bulletin 29, no. 11 (November 2004): 814–17. http://dx.doi.org/10.1557/mrs2004.233.

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AbstractIn order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films used today in memory cells. Likewise, planar-based memory cell scaling is approaching the point where scaling constraints force exploration of new materials and nonplanar, three-dimensional scaling alternatives. This article will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor floating-gate-based nonvolatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor-based flash memory cells can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. More complex, structural innovations will be required to achieve further scaling.

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Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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Ieong, Meikei, Vijay Narayanan, Dinkar Singh, Anna Topol, Victor Chan, and Zhibin Ren. "Transistor scaling with novel materials." Materials Today 9, no. 6 (June 2006): 26–31. http://dx.doi.org/10.1016/s1369-7021(06)71540-1.

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Castañer, Luis M., Ramon Alcubilla, and Anna Benavent. "Bipolar transistor vertical scaling framework." Solid-State Electronics 38, no. 7 (July 1995): 1367–71. http://dx.doi.org/10.1016/0038-1101(94)00254-d.

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Jacob, Ajey P., Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee, and Bill Taylor. "Scaling Challenges for Advanced CMOS Devices." International Journal of High Speed Electronics and Systems 26, no. 01n02 (February 17, 2017): 1740001. http://dx.doi.org/10.1142/s0129156417400018.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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Chen, Zhuo, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, et al. "High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale." Nanomaterials 13, no. 12 (June 15, 2023): 1867. http://dx.doi.org/10.3390/nano13121867.

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At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an “exposed top” structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

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Park, Junhyeong, Yuseong Jang, Jinkyu Lee, and Soo-Yeon Lee. "48‐3: In‐Ga‐Zn‐O Synaptic Transistor with 1 µm Channel Length for Neuromorphic Computing." SID Symposium Digest of Technical Papers 54, no. 1 (June 2023): 699–702. http://dx.doi.org/10.1002/sdtp.16655.

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In this paper, indium‐gallium‐zinc‐oxide synaptic transistors with different channel lengths ranging from 2 μm to 1 μm were demonstrated. Channel scaling effect on synaptic behaviors such as long‐term depression and long‐term potentiation was investigated. A spiking neural network simulation was conducted to verify our synaptic transistor with a channel length of 1 μm, achieving high classification accuracy of 98.05%.

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Kumar, MAnil, YNSSai Kiran, U. Jagadeesh, B. Balaram, and M. Durga Prakash. "SCALING CHALLENGES FOR ADVANCED TRANSISTOR DESIGN." International Journal of Advanced Research 5, no. 5 (May 31, 2017): 340–45. http://dx.doi.org/10.21474/ijar01/4118.

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Fitsilis, Michael, Yacoub Mustafa, and Rainer Waser. "Scaling the Ferroelectric Field Effect Transistor." Integrated Ferroelectrics 70, no. 1 (April 13, 2005): 29–44. http://dx.doi.org/10.1080/10584580590926657.

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Chen, Wenbin. "Characterization of new materials for capacitor formation in integrated circuit technology." Boolean: Snapshots of Doctoral Research at University College Cork, no. 2010 (January 1, 2010): 26–31. http://dx.doi.org/10.33178/boolean.2010.7.

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There have been tremendous developments in electronic technology in the last 40 years as evidenced by the widespread availability of computers, mobile phones and electronic entertainment systems and their continued shrinking in size and cost. Much of the improvement in the performance of electronic systems can be traced to developments in Integrated Circuits (ICs) (“microchips”) which form the fundamental building blocks of modern electronics technology. Within an IC, the most important electronic component is the transistor and it is the transistor that is used to implement the operations associated with computer logic. With each generation of technology, the size of the transistors is reduced and more of them can fit on a single IC, which allows more powerful devices to be made that take up the same or even smaller space and draw less power from the battery. This trend regarding the scaling down in size of the transistors was ...

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Cao, Qing, Shu-Jen Han, Jerry Tersoff, Aaron D. Franklin, Yu Zhu, Zhen Zhang, George S. Tulevski, Jianshi Tang, and Wilfried Haensch. "End-bonded contacts for carbon nanotube transistors with low, size-independent resistance." Science 350, no. 6256 (October 1, 2015): 68–72. http://dx.doi.org/10.1126/science.aac8006.

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Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabricated with a sub–10-nanometer contact length, showing a device resistance below 36 kilohms and on-current above 15 microampere per tube. The p-type end-bonded contact, formed through the reaction of molybdenum with the SWNT to form carbide, also exhibited no Schottky barrier. This strategy promises high-performance SWNT transistors, enabling future ultimately scaled device technologies.

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Urteaga, M., S. Krishnan, D. Scott, Y. Wei, M. Dahlstrom, S. Lee, and M. J. W. Rodwell. "Submicron InP-based HBTs for Ultra-high Frequency Amplifiers." International Journal of High Speed Electronics and Systems 13, no. 02 (June 2003): 457–95. http://dx.doi.org/10.1142/s0129156403001806.

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Transistor bandwidths are approaching terahertz frequencies. Paramount to high speed transistor operation is submicron device scaling. High bandwidths are obtained with heterojunction bipolar transistors by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. We have fabricated HBTs with narrow collector junctions using a substrate transfer process. HBTs with submicron collector junctions exhibit extremely high fmax and high gains in mm-wave ICs. Transferred-substrate HBTs have obtained record 21 dB unilateral power gain at 100 GHz. Recently-fabricated devices have shown unbounded unilateral power gain from 40-110 GHz, and fmax cannot be extrapolated from measuremente. However, these devices exhibited high power gains at 220 GHz, the frequency limit of presently available microwave network analyzers. Demonstrated amplifier ICs in the technology include reactively tuned amplifiers at 175 GHz, lumped and distributed amplifiers with bandwidths to 85 GHz, and W-band power amplifiers.

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John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.

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Kumar, Abneesh, Atal Rai, R. K. Saxena, and Suresh Patel. "To Study Effect on Current Due to Channel Length Variation." International Journal of Advance Research and Innovation 2, no. 4 (2014): 30–32. http://dx.doi.org/10.51976/ijari.241406.

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There are two primary device structures that have being widely used. One is the bulk structure, where a transistor is directly fabricated on the semiconductor substrate. The other one is called SOI (silicon-on-insulator), where a transistor is built on a thin silicon layer, which is separated from the substrate by a layer of insulator or device scaling; it is basically try to balance two things: device functionality and device reliability. Both of them have to be maintained at a smaller dimensional size [1]. In this paper, three transistors are proposed having different channel lengths 8 micron, 16 micron and 24 micron. Simulation shows that with a fixed gate length, when channel length is increased, the output characteristics slope is decreased.

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FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

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Mishra, Brijendra, Vivek Singh Kushwah, and Rishi Sharma. "MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR." International Journal of Engineering Technologies and Management Research 5, no. 2 (May 4, 2020): 294–300. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.659.

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In digital integrated circuit architectures, transistors serve as circuit switches to charge and discharge capacitors to the required logic voltage levels. A transistor is a three terminal semiconductor device used to amplify and switch electronic signals and electrical power. It has been observed that the Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metaloxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications. A better device will be formed with the help of new technology, with high operating speed low and power consumption, which can be the future of electronics industry. A methodology for the electric simulation of MOS/SET hybrid circuits will be developed. As a result of this, a functional model for the single-electron transistor will obtain and Implement Switched Capacitor Filter with the help of designed hybrid MOS. The SET model can be easily coded in any hardware description language.

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Kumari, Nibha, and Prof Vandana Niranjan. "Low-Power 6T SRAM Cell using 22nm CMOS Technology." Indian Journal of VLSI Design 2, no. 2 (September 30, 2022): 5–10. http://dx.doi.org/10.54105/ijvlsid.b1210.092222.

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Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.

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Packan, Paul A. "Scaling Transistors into the Deep-Submicron Regime." MRS Bulletin 25, no. 6 (June 2000): 18–21. http://dx.doi.org/10.1557/mrs2000.93.

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The dominant device used in the semiconductor industry today is the silicon-based metal oxide semiconductor (MOS) transistor. The MOS transistor consists of a source, drain, channel, and gate region fabricated in single-crystal silicon (Figure 1). The source region provides a supply of mobile charge when the device is turned “on.” The source is electrically isolated from the drain by the channel region, which is oppositely charged. An insulating oxide layer between the gate and the channel region forms a capacitor. During operation, a voltage is applied to the gate. By applying the appropriate voltage, a conductive layer of charge can be attracted in the channel region at the oxide/silicon interface. This layer of charge acts as a wire that effectively connects the source and drain regions. By changing the voltage on the gate, the conducting layer of charge can be removed. Thus the transistor acts like a switch, with the gate electrode controlling the connection from the source to the drain. These individual switches can be connected to form the basic building blocks for circuit design. These building blocks are used to create the high-performance microprocessors and memory chips in today's computers.

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Patel, Ambresh, and Ritesh Sadiwala. "Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 14, no. 02 (June 30, 2022): 202–5. http://dx.doi.org/10.18090/samriddhi.v14i02.13.

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With the advancement of technology, small and handy electronic devices are built with low supply voltage and lower power dissipation in designing deep submicron static CMOS circuits. Small devices scaling down with burst-mode type integrated circuits have two major challenges: area and power dissipation. This paper presents a method for decreasing dynamic power, area, and leakage of application-specific integrated circuits without sacrificing performance. The High Threshold Leakage Control Transistor, TG-Based Technique, Supply Voltage Scaling, Sleep Transistor approaches are covered, and a dynamic CMOS architecture with stack transistor. With certain area and delay considerations, these strategies are utilized to diminish both types of power dissipation in the CMOS logic designs.

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Lu, Bin Bin, and Jian Ping Hu. "Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques." Applied Mechanics and Materials 39 (November 2010): 55–60. http://dx.doi.org/10.4028/www.scientific.net/amm.39.55.

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With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

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Pan, Y. "A fundamental limitation for bipolar transistor scaling." IEEE Electron Device Letters 11, no. 10 (October 1990): 445–47. http://dx.doi.org/10.1109/55.62991.

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Nagy, Roland, Alex Burenkov, and Jürgen Lorenz. "Numerical evaluation of the ITRS transistor scaling." Journal of Computational Electronics 14, no. 1 (November 4, 2014): 192–202. http://dx.doi.org/10.1007/s10825-014-0638-0.

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Haggag, Amr, William McMahon, Karl Hess, Björn Fischer, and Leonard F. Register. "Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability." VLSI Design 13, no. 1-4 (January 1, 2001): 111–15. http://dx.doi.org/10.1155/2001/90787.

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Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy distribution, as it causes an increased probability of smaller devices having lower activation thresholds and therefore faster activation times. Further, we quantify the voltage shift necessary to overcome the decreased yield due to the increased number of early device failures, and show, for 0.1 μm MOSFET scaling, that this shift can be a considerable fraction of the conventionally designed supply voltage.

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Chen, Zhuo, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, et al. "Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing." Nanomaterials 13, no. 11 (June 1, 2023): 1786. http://dx.doi.org/10.3390/nano13111786.

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Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

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Renukarani, S., Bhavana Godavarthi, SK Bia Roshini, and Mohammad Khadir. "A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 109. http://dx.doi.org/10.14419/ijet.v7i2.20.12185.

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A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to sub-nanometer engineering technology.

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Sri Selvarajan, Reena, Azrul Azlan Hamzah, Norliana Yusof, and Burhanuddin Yeop Majlis. "Channel length scaling and electrical characterization of graphene field effect transistor (GFET)." Indonesian Journal of Electrical Engineering and Computer Science 15, no. 2 (August 1, 2019): 697. http://dx.doi.org/10.11591/ijeecs.v15.i2.pp697-703.

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<p>The exclusive monoatomic framework of graphene makes it as an alluring material to be implemented in electronic devices. Thus, using graphene as charge carrying conducting channel material in Field Effect Transistors (FET) expedites the opportunities for production of ultrasensitive biosensors for future device applications. However, performance of GFET is influenced by various parameters, particularly by the length of conducting channel. Therefore, in this study we have investigated channel length scaling in performance of graphene field effect transistor (GFET) via simulation technique using Lumerical DEVICE software. The performance was analyzed based on electrical characterization of GFET with long and short conducting channels. It proves that conducting channel lengths have vast effect on ambipolar curve where short channel induces asymmetry in transfer characteristics curve where the n-branch is suppressed. Whereas for output characteristics, the performance of GFET heavily degraded as the channel length is reduced in short channels of GFET. Therefore, channel length scaling is a vital parameter in determining the performance of GFET in various fields, particularly in biosensing applications for ultrasensitive detection.</p>

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Zhao, Dongxue, Zhiliang Xia, Tao Yang, Yuancheng Yang, Wenxi Zhou, and Zongliang Huo. "A Novel Capacitorless 1T DRAM with Embedded Oxide Layer." Micromachines 13, no. 10 (October 19, 2022): 1772. http://dx.doi.org/10.3390/mi13101772.

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A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F2 cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.

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Wong, Hei, and Kuniyuki Kakushima. "On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node." Nanomaterials 12, no. 10 (May 19, 2022): 1739. http://dx.doi.org/10.3390/nano12101739.

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This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node.

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Wang, Peng-Fei, Xi Lin, Lei Liu, Qing-Qing Sun, Peng Zhou, Xiao-Yong Liu, Wei Liu, Yi Gong, and David Wei Zhang. "A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation." Science 341, no. 6146 (August 8, 2013): 640–43. http://dx.doi.org/10.1126/science.1240961.

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As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

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Masalsky, Nikolay. "Silicon on isolator ribbon field-effect nanotransistors for high-sensitivity low-power biosensor." Journal of Engineering and Technological Sciences 54, no. 2 (March 31, 2022): 220214. http://dx.doi.org/10.5614/j.eng.technol.sci.2022.54.2.14.

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Silicon nanowire field-effect transistors are discussed as biological sensors due to their excellent sensitivity due to the large surface-to-volume ratio and high selectivity with respect to a large number of analytes. A miniature sensor based on a long-channel fin field-effect transistor as a surface charge detector is being investigated. The three-gate configuration offers undeniable advantages over planar devices, since the edges are about a hundred nanometers wide and are characterized by increased conductivity, which leads to higher sensitivity. The characteristics of the transistor are optimized using 3D modeling performed by the computer-aided design software package TCAD, depending on the topological parameters of the transistor and the level of control voltages. Based on the obtained simulation results, a chip was manufactured on a SOI substrate based on self-aligning CMOS-compatible technological processes from top to bottom. It is established that thin structures with a reduced level of doping and low supply power have promising electrical characteristics for an effective approach to scaling a high-resolution pH sensor, which is of particular interest to integrated pH bioanalytics based on CMOS technology.

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Et. al., Kothamasu Jyothi,. "9T SRAM CELL WITH MT-SVL TECHNIQUE FOR LEAKAGE POWER REDUCTION." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 2 (April 13, 2021): 1139–43. http://dx.doi.org/10.17762/itii.v9i2.465.

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With the technology scaling there is a decrease in transistor size and increase in number of the transistors per a chip. It causes tremendous increase in complexity and the power dissipation of circuits. This paper mainly focuses on reduction of leakage power dissipation in SRAM 9T cells by employing multi threshold self controllable voltage level circuits (LSVL & USVL). The Simulation results show that with the employment of MT-SVL technique, leakage power is being reduced compared to the improved SVL technique. The overall simulation is done with CMOS 180nm technology, using the tool of Cadence Virtuoso.

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Marrakh, R., and A. Bouhdada. "Modeling of the I–V Characteristics for LDD-nMOSFETs in Relation with Defects Induced by Hot-Carrier Injection." Active and Passive Electronic Components 26, no. 4 (2003): 197–204. http://dx.doi.org/10.1080/08827510310001624363.

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The hot-carrier injection is observed increasingly to degrade the I–V characteristics with the scaling of MOS transistors. For the lightly doped drain MOS transistor the injection of the hot-carriers, caused by the high electric field in the MOS structure, is localized in the LDD region. The modeling of the drain current in relation to defects due to the hot-carrier injection allows us to investigate the I–V characteristics and the transconductance of devices. Consequently, we can know the amount of the device degradation caused by these defects in order to find technological solutions to optimize reliability.

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Wulf, Ulrich, and Hans Richter. "Scale-Invariant Drain Current in Nano-FETs." Journal of Nano Research 10 (April 2010): 49–61. http://dx.doi.org/10.4028/www.scientific.net/jnanor.10.49.

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Starting from a three-dimensional transport model in the Landauer-Buttiker formalism we derive a scale-invariant expression for the drain current in a nano-transistor. Apart from dimensionless external parameters representing temperature, gate-, and drain voltage the normalized drain current depends on two dimensionless transistor parameters which are the characteristic length l and -width w of the electron channel. The latter quantities are the physical length and -width of the channel in units of the scaling length = ~(2mF )1=2. Here F is the Fermi energy in the source contact and m is the eective mass in the electron channel. In the limit of wide transistors and low temperatures we evaluate the scale-invariant IDVD characteristics as a function of the characteristic length. In the strong barrier regime, i. e. for l & 20 long-channel behavior is found. At weaker barriers source-drain tunneling leads to increasingly signicant deviations from the long-channel behavior. We compare with experimental results.

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Kumar, Nandhaiahgari Dinesh, Rajendra Prasad Somineni, and CH Raja Kumari. "Design and analysis of different full adder cells using new technologies." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (July 1, 2020): 116. http://dx.doi.org/10.11591/ijres.v9.i2.pp116-124.

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<span>CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.</span>

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Cao, Qing. "Carbon nanotube transistor technology for More-Moore scaling." Nano Research 14, no. 9 (April 26, 2021): 3051–69. http://dx.doi.org/10.1007/s12274-021-3459-z.

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Volcheck, V. S., and V. R. Stempitsky. "Numerical simulation of the sensor for toxic nanoparticles based on the heterostructure field effect transistor." Doklady BGUIR 18, no. 8 (December 27, 2020): 62–68. http://dx.doi.org/10.35596/1729-7648-2020-18-8-62-68.

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A significant rise in the mass production of products that contain nanoparticles is of growing concern due to the detection of their toxic effects on living organisms. The standard method for analyzing the toxicity of substances, including nanomaterials, is toxicological testing, which requires the substantial consumption of time and material resources. An alternative approach is to develop models that predict the effect of nanomaterials on biological systems. In both cases, for the detection of nanoparticles an effective electronic complex consisting of a sensor with high sensitivity and a data reception/processing/transmission system is necessary. In recent times, fundamental and applied research activities aimed at the application of heterostructure field-effect transistors – high electron mobility transistors–as a base for such sensors have been undertaken. The purpose of this work is to develop a technique for modeling a sensor for toxic nanoparticles based on the heterostructure field-effect transistor. The object of the research is a gallium nitride high electron mobility transistor device structure. The subject of the research is the electrical characteristics of the transistor obtained in static mode. The calculation results show that the dependence between the concentration of the toxic nanoparticles in the test medium and the polarization charge surface density could serve as a base for modeling the sensor for toxic nanoparticles based on the heterostructure field-effect transistor. The primary advantage of the proposed technique is the use of the scaling parameter intended directly for calibrating the polarization charge density in accordance with the two-dimensional electron gas concentration. The obtained results can be utilized by the electronics industry of the Republic of Belarus for developing the hardware components of gallium nitride high-frequency electronics.

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Gul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (August 17, 2022): 1332. http://dx.doi.org/10.3390/mi13081332.

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Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.

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Dimoulas, Athanasios, Akira Toriumi, and Suzanne E. Mohney. "Source and Drain Contacts for Germanium and III–V FETs for Digital Logic." MRS Bulletin 34, no. 7 (July 2009): 522–29. http://dx.doi.org/10.1557/mrs2009.140.

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AbstractThe scaling of transistors to smaller dimensions and the exploration of devices with III–V and Ge channels for digital logic places serious demands on the ohmic contacts used in these devices. Contacts with extremely low specific contact resistances are required to take full advantage of the performance promised by alternative semiconductor materials. In addition, device processes and contact morphologies must be compatible with the geometry and feature sizes of the transistors. In this article, we begin by reviewing what is known about contacts to Ge, InGaAs, InAs, and InSb, including the role of Fermi level pinning on the Schottky barrier that is often formed at the metal/semiconductor interface and common strategies for forming ohmic contacts. Then we turn our attention to the additional challenges faced when preparing ohmic contacts for the many types of field-effect transistors now under development for Ge and III–V complementary field-effect transistor technology.

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Wu, C. H., G. Walter, H. W. Then, M. Feng, and N. Holonyak. "Scaling of light emitting transistor for multigigahertz optical bandwidth." Applied Physics Letters 94, no. 17 (April 27, 2009): 171101. http://dx.doi.org/10.1063/1.3126642.

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Zhang, Shubo. "Review of Modern Field Effect Transistor Technologies for Scaling." Journal of Physics: Conference Series 1617 (August 2020): 012054. http://dx.doi.org/10.1088/1742-6596/1617/1/012054.

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Li, Chi-Kang, Po-Chun Yeh, Jeng-Wei Yu, Lung-Han Peng, and Yuh-Renn Wu. "Scaling performance of Ga2O3/GaN nanowire field effect transistor." Journal of Applied Physics 114, no. 16 (October 28, 2013): 163706. http://dx.doi.org/10.1063/1.4827190.

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Muller, D. A., P. M. Voyles, J. L. Grazul, and G. D. Wilk. "Exploring the physical limits of transistor scaling using STEM." Microscopy and Microanalysis 9, S02 (August 2003): 1012–13. http://dx.doi.org/10.1017/s1431927603445066.

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Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.

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The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

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Mertens, Hans. "Nanosheet-Based Transistor Architectures for Advanced CMOS Scaling: Wet Etch and Gas Phase Etch Challenges in Confined Spaces." Solid State Phenomena 346 (August 14, 2023): 8–13. http://dx.doi.org/10.4028/p-tzn0md.

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Nanosheet-based transistor architectures for advanced CMOS have sophisticated 3D geometries and aggressively scaled dimensions imposing new challenges to wet etch and gas phase etch. In this paper, we describe three nanosheet-based transistor architectures (nanosheet, forksheet, and CFET) as well as associated challenges for wet etch and gas phase etch at various stages of the process flow, including channel release, work function metal patterning, and controlled dielectric etchback for stacked source-drain formation. The compatibility of etch processes with confined spaces and high-aspect-ratio structures becomes increasingly important for novel nanosheet-based transistor architectures.

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Birla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (May 29, 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.

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Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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Hu, Jian Ping, and Yu Zhang. "Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction." Advanced Materials Research 159 (December 2010): 180–85. http://dx.doi.org/10.4028/www.scientific.net/amr.159.180.

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Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.

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Journal articles on the topic 'Transistor scaling'

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