Relevant bibliographies by topics / Transistor scaling

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Transistor scaling'

Author: Grafiati
Published: 6 September 2023

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Journal articles on the topic "Transistor scaling"

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Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (March 31, 2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.

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For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.
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Datta, Suman, Wriddhi Chakraborty, and Marko Radosavljevic. "Toward attojoule switching energy in logic transistors." Science 378, no. 6621 (November 18, 2022): 733–40. http://dx.doi.org/10.1126/science.ade7656.

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Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future.
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SARKOZY, S., X. MEI, W. YOSHIDA, P. H. LIU, M. LANGE, J. LEE, Z. ZHOU, et al. "AMPLIFIER GAIN PER STAGE UP TO 0.5 THz USING 35 NM InP HEMT TRANSISTORS." International Journal of High Speed Electronics and Systems 20, no. 03 (September 2011): 399–404. http://dx.doi.org/10.1142/s0129156411006684.

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Pivotal in the design of circuits is the ability to efficiently translate available transistor gain to high gain per stage. Remarkably, for 35-nm InP HEMT transistors, the efficiency of this translation remains high even up to ~0.5 THz. The ever shrinking wavelength correlated with higher frequencies necessitates a scaling of not only the device layout, but also of the passive elements and wafer thickness. Furthermore, to avoid distributed effects, the length of transistor gate fingers must be reduced.
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Reid, Dave, Campbell Millar, Scott Roy, Gareth Roy, Richard Sinnott, Gordon Stewart, Graeme Stewart, and Asen Asenov. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (June 28, 2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.

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The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project and describes the way in which the scientific goals have been reflected in the grid-based e-Infrastructure.
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Fazio, Al. "Flash Memory Scaling." MRS Bulletin 29, no. 11 (November 2004): 814–17. http://dx.doi.org/10.1557/mrs2004.233.

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AbstractIn order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films used today in memory cells. Likewise, planar-based memory cell scaling is approaching the point where scaling constraints force exploration of new materials and nonplanar, three-dimensional scaling alternatives. This article will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor floating-gate-based nonvolatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor-based flash memory cells can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future. More complex, structural innovations will be required to achieve further scaling.
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Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.
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Ieong, Meikei, Vijay Narayanan, Dinkar Singh, Anna Topol, Victor Chan, and Zhibin Ren. "Transistor scaling with novel materials." Materials Today 9, no. 6 (June 2006): 26–31. http://dx.doi.org/10.1016/s1369-7021(06)71540-1.

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Castañer, Luis M., Ramon Alcubilla, and Anna Benavent. "Bipolar transistor vertical scaling framework." Solid-State Electronics 38, no. 7 (July 1995): 1367–71. http://dx.doi.org/10.1016/0038-1101(94)00254-d.

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Jacob, Ajey P., Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee, and Bill Taylor. "Scaling Challenges for Advanced CMOS Devices." International Journal of High Speed Electronics and Systems 26, no. 01n02 (February 17, 2017): 1740001. http://dx.doi.org/10.1142/s0129156417400018.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.
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Chen, Zhuo, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, et al. "High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale." Nanomaterials 13, no. 12 (June 15, 2023): 1867. http://dx.doi.org/10.3390/nano13121867.

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At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an “exposed top” structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.
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Dissertations / Theses on the topic "Transistor scaling"

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Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.

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Deshpande, Veeresh. "Scaling Beyond Moore: Single Electron Transistor and Single Atom Transistor Integration on CMOS." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00813508.

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La r eduction (\scaling") continue des dimensions des transistors MOS- FET nous a conduits a l' ere de la nano electronique. Le transistor a ef- fet de champ multi-grilles (MultiGate FET, MuGFET) avec l'architecture \nano l canal" est consid er e comme un candidat possible pour le scaling des MOSFET jusqu' a la n de la roadmap. Parall element au scaling des CMOS classiques ou scaling suivant la loi de Moore, de nombreuses propo- sitions de nouveaux dispositifs, exploitant des ph enom enes nanom etriques, ont et e faites. Ainsi, le transistor mono electronique (SET), utilisant le ph enom ene de \blocage de Coulomb", et le transistor a atome unique (SAT), en tant que transistors de dimensions ultimes, sont les premiers disposi- tifs nano electroniques visant de nouvelles applications comme la logique a valeurs multiples ou l'informatique quantique. Bien que le SET a et e ini- tialement propos e comme un substitut au CMOS (\Au-del a du dispositif CMOS"), il est maintenant largement consid er e comme un compl ement a la technologie CMOS permettant de nouveaux circuits fonctionnels. Toutefois, la faible temp erature de fonctionnement et la fabrication incompatible avec le proc ed e CMOS ont et e des contraintes majeures pour l'int egration SET avec la technologie FET industrielle. Cette th ese r epond a ce probl eme en combinant les technologies CMOS de dimensions r eduites, SET et SAT par le biais d'un sch ema d'int egration unique a n de fabriquer des transistors \Trigate" nano l. Dans ce travail, pour la premi ere fois, un SET fonction- nant a temp erature ambiante et fabriqu es a partir de technologies CMOS SOI a l' etat de l'art (incluant high-k/grille m etallique) est d emontr e. Le fonctionnement a temp erature ambiante du SET n ecessite une le (ou canal) de dimensions inf erieures a 5 nm. Ce r esultat est obtenu grce a la r eduction du canal nano l "trigate" a environ 5 nm de largeur. Une etude plus ap- profondie des m ecanismes de transport mis en jeu dans le dispositif est r ealis ee au moyen de mesures cryog eniques de conductance. Des simula- tions NEGF tridimensionnelles sont egalement utilis ees pour optimiser la conception du SET. De plus, la coint egration sur la m^eme puce de MOS- FET FDSOI et SET est r ealis ee. Des circuits hybrides SET-FET fonction- nant a temp erature ambiante et permettant l'ampli cation du courant SET jusque dans la gamme des milliamp eres (appel e \dispositif SETMOS" dans la litt erature) sont d emontr es de m^eme que de la r esistance di erentielle n egative (NDR) et de la logique a valeurs multiples. Parall element, sur la m^eme technologie, un transistor a atome unique fonc- tionnant a temp erature cryog enique est egalement d emontr e. Ceci est obtenu par la r eduction de la longueur de canal MOSFET a environ 10 nm, si bien qu'il ne comporte plus qu'un seul atome de dopant dans le canal (dif- fus ee a partir de la source ou de drain). A basse temp erature, le trans- port d' electrons a travers l' etat d' energie de ce dopant unique est etudi e. Ces dispositifs fonctionnent egalement comme MOSFET a temp erature am- biante. Par cons equent, une nouvelle m ethode d'analyse est d evelopp ee en corr elation avec des caract eristiques a 300K et des mesures cryog eniques pour comprendre l'impact du dopant unique sur les caracteristiques du MOSFET a temp erature ambiante.
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Woo, Raymond. "Band-to-band tunneling transistor scaling and design for low-power logic applications /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Yuan, Jiahui. "Cryogenic operation of silicon-germanium heterojunction bipolar transistors and its relation to scaling and optimization." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33837.

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The objective of the proposed work is to study the behavior of SiGe HBTs at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential information for further device scaling. Technology computer aided design (TCAD) and sophisticated on-wafer DC and RF measurements are essential in this research. Drift-diffusion (DD) theory is used to investigate a novel negative differential resistance (NDR) effect and a collector current kink effect in first-generation SiGe HBTs at deep cryogenic temperatures. A theory of positive feedback due to the enhanced heterojunction barrier effect at deep cryogenic temperatures is proposed to explain such effects. Intricate design of the germanium and base doping profiles can greatly suppress both carrier freezeout and the heterojunction barrier effect, leading to a significant improvement in the DC and RF performance for NASA lunar missions. Furthermore, cooling is used as a tuning knob to better understand the performance limits of SiGe HBTs. The consequences of cooling SiGe HBTs are in many ways similar to those of combined vertical and lateral device scaling. A case study of low-temperature DC and RF performance of prototype fourth-generation SiGe HBTs is presented. This study summarizes the performance of all three prototypes of these fourth-generation SiGe HBTs within the temperature range of 4.5 to 300 K. Temperature dependence of a fourth-generation SiGe CML gate delay is also examined, leading to record performance of Si-based IC. This work helps to analyze the key optimization issues associated with device scaling to terahertz speeds at room temperature. As an alternative method, an fT -doubler technique is presented as an attempt to reach half-terahertz speeds. In addition, a roadmap for terahertz device scaling is given, and the potential relevant physics associated with future device scaling are examined. Subsequently, a novel superjunction collector design is proposed for higher breakdown voltages. Hydrodynamic models are used for the TCAD studies that complete this part of the work. Finally, Monte Carlo simulations are explored in the analysis of aggressively-scaled SiGe HBTs.
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Schuette, Michael L. "Advanced processing for scaled depletion and enhancement-mode AlGaN/GaN HEMTs." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1275524410.

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Ahmed, Adnan. "Study of Low-Temperature Effects in Silicon-Germanium Heterojunction Bipolar Transistor Technology." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7227.

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This thesis investigates the effects of low temperatures on Silicon Germanium (SiGe) Hterojunction Bipolar Transistors (HBT) BiCMOS technology. A comprehensive set of dc measurements were taken on first, second, third and fourth generation IBM SiGe technology over a range of temperatures (room temperature to 43K for first generation, and room temperature to 15K for the rest). This work is unique in the sense that this sort of comprehensive study of dc characteristics on four SiGe HBT technology generations over a wide range of temperatures has never been done before to the best of the authors knowledge.
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Connor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.

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Nicoletti, Talitha. "Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10072014-012728/.

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O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL.
The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.
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Murali, Raghunath. "Scaling opportunities for bulk accumulation and inversion MOSFETs for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/submitted/etd-02132004-173432/unrestricted/murali%5FRaghunath%5F405%5F.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.
Hess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).
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Hoppe, Arne [Verfasser]. "Scaling limits and Megahertz operation in thiophene-based field effect transistors / Arne Hoppe." Bremen : IRC-Library, Information Resource Center der Jacobs University Bremen, 2008. http://d-nb.info/1034966928/34.

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Books on the topic "Transistor scaling"

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F, Eastman Lester, Society of Photo-optical Instrumentation Engineers., Society of Vacuum Coaters, and SPIE Symposium on Advances in Semiconductors and Superconductors: Physics Toward Device Applications (1990 : San Diego, Calif.), eds. High-speed electronics and device scaling: 18-19 March 1990, San Diego, California. Bellingham, Wash., USA: SPIE, 1990.

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Thompson, Scott, Faran Nouri, Wen-Chin Lee, and Wilman Tsai. Transistor Scaling : Volume 913: Methods, Materials and Modeling. University of Cambridge ESOL Examinations, 2014.

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Transistor Scaling: Methods, Materials and Modeling: Symposium Held April 18-19, 2006, San Francisco, California, U.S.A. (Materials Research Society Symposium Proceedings). Materials Research Society, 2006.

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Ashraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Springer International Publishing AG, 2016.

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Ashraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Morgan & Claypool Publishers, 2016.

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Ashraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Morgan & Claypool Publishers, 2016.

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Book chapters on the topic "Transistor scaling"

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Julien, Levisse Alexandre Sébastien, Xifan Tang, and Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices." In Emerging Computing: From Devices to Systems, 47–83. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.

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AbstractSince the introduction of the transistor, the semiconductor industry has always been able to propose an increasingly higher level of circuit performance while keeping cost constant by scaling the transistor’s area. This scaling process (named Moore’s law) has been followed since the 80s. However, it has been facing new constraints and challenges since 2012. Standard sub-30nm bulk CMOS technologies cannot provide sufficient performance while remaining industrially profitable. Thereby, various solutions, such as FinFETs (Auth et al. 2012) or Fully Depleted Silicon On Insulator (FDSOI) (Faynot et al. 2010) transistors have therefore been proposed. All these solutions enabled Moore’s law scaling to continue. However, when approaching sub-10nm technology nodes, the story starts again. Again, process costs and electrical issues reduce the profitability of such solutions, and new technologies such as Gate-All-Around (GAA) (Sacchetto et al. 2009) transistors are seen as future FinFET replacement candidates.
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Chaudhry, Amit. "Scaling of a MOS Transistor." In Fundamentals of Nanoscaled Field Effect Transistors, 1–24. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6822-6_1.

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Liu, T. J. K., and L. Chang. "Transistor Scaling to the Limit." In Into the Nano Era, 191–223. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-74559-4_8.

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Skotnicki, T., and F. Boeuf. "Optimal Scaling Methodologies and Transistor Performance." In High Dielectric Constant Materials, 143–94. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/3-540-26462-0_6.

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Tigelaar, Howard. "The Incredible Shrinking IC: Part 2 FEOL Isolation Scaling and Transistor Scaling." In How Transistor Area Shrank by 1 Million Fold, 201–26. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_10.

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Amiri, Iraj Sadegh, and Mahdiar Ghadiry. "Introduction on Scaling Issues of Conventional Semiconductors." In Analytical Modelling of Breakdown Effect in Graphene Nanoribbon Field Effect Transistor, 1–7. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6550-7_1.

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J.M. Veendrick, Harry. "Geometrical-, Physical- and Field-Scaling Impact on MOS Transistor Behaviour." In Nanometer CMOS ICs, 45–72. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-47597-4_2.

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Veendrick, H. J. M. "Geometrical-, physical- and field-scaling impact on MOS transistor behaviour." In Nanometer CMOS ICs, 57–91. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8333-4_2.

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Prasher, Rakesh, Devi Dass, and Rakesh Vaid. "Novel Attributes in Scaling Issues of an InSb-Nanowire Field-Effect Transistor." In Physics of Semiconductor Devices, 677–79. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03002-9_174.

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Ni, Haiyan, Xiaolei Sheng, and Jianping Hu. "Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic." In Lecture Notes in Electrical Engineering, 39–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_6.

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Conference papers on the topic "Transistor scaling"

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Yang, Fu-Liang, Hou-Yu Chen, and Chang-Yun Chang. "SOI Transistor/Power Scaling and Scaling-Strengthened Strain." In 2004 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2004. http://dx.doi.org/10.7567/ssdm.2004.c-7-1.

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Chen, Tianbing, Tzung-Yin Lee, Justin Allum, and Mike McPartlin. "The thermal scaling: From transistor to array." In 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2014. http://dx.doi.org/10.1109/rfic.2014.6851675.

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Tadayon, Saied, Bijan Tadayon, and Lester F. Eastman. "Effect of InAlAs emitter on the microwave performance of InAlAs/InGaAs abrupt npn heterojunction bipolar transistor." In High-Speed Electronics and Device Scaling, edited by Lester F. Eastman. SPIE, 1990. http://dx.doi.org/10.1117/12.20909.

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Kim, Michael E. "GaAs heterojunction bipolar transistor device and IC technology for high-performance analog/microwave, digital, and A/D conversion applications." In High-Speed Electronics and Device Scaling, edited by Lester F. Eastman. SPIE, 1990. http://dx.doi.org/10.1117/12.20903.

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Van Der Bent, G., A. P. De Hek, and F. E. Van Vliet. "EM - Based GaN Transistor Small-Signal Model Scaling." In 2018 13th European Microwave Integrated Circuits Conference (EuMIC). IEEE, 2018. http://dx.doi.org/10.23919/eumic.2018.8539925.

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Kuhn, Kelin J. "CMOS transistor scaling past 32nm and implications on variation." In 2010 21st Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2010. http://dx.doi.org/10.1109/asmc.2010.5551461.

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Woo, Raymond, H. Y. Serene Koh, Caner Onal, P. B. Griffin, and James D. Plummer. "BTBT Transistor Scaling: Can they be Competitive with MOSFETs?" In 2008 66th Annual Device Research Conference (DRC). IEEE, 2008. http://dx.doi.org/10.1109/drc.2008.4800741.

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Tian, H., Asanga H. Perera, D. O'Meara, H. De, C. K. Subramanian, P. Rehmann, James D. Hayden, and Norm Herr. "Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications." In Microelectronic Manufacturing, edited by Mark Rodder, Toshiaki Tsuchiya, David Burnett, and Dirk Wristers. SPIE, 1997. http://dx.doi.org/10.1117/12.284616.

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Cao, Q. "Carbon Nanotube Transistor Technology for Scaling Beyond Si CMOS." In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.j-3-01.

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Shakil, S. M., and Muhammad Sana Ullah. "Analysis of HCD Effects for NMOS Transistor with Technology Scaling." In SoutheastCon 2023. IEEE, 2023. http://dx.doi.org/10.1109/southeastcon51012.2023.10115193.

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