Dissertations / Theses on the topic 'Transformer Architecture'
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Ogunnika, Olumuyiwa Temitope 1978. "A simple transformer-based resonator architecture for low phase noise LC oscillators." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/28338.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2004.Includes bibliographical references (leaves 86-87).
This thesis investigates the use of a simple transformer-coupled resonator to increase the loaded Q of a LC resonant tank. The windings of the integrated transformer replace the simple inductors as the inductive elements of the resonator. The resonator topology considered in this project is a simpler alternative to another proposed by Straayer et al [5] because it just requires a single varactor. A prime objective of this project is to prove that a transformer-coupled resonator which is simpler than that proposed by Straayer in [5] produces the same reduction in phase noise. The use of this type of resonator topology is a valuable technique which can be employed by RF engineers to reduce the phase noise generated by oscillators in high speed RF systems. Such techniques which increase the loaded Q of the resonator are very useful in practice because of the inverse squared relationship between resonator Q and the phase noise in the output signals of LC oscillators. The important aspect of this technique is that magnetic coupling between the windings of an integrated transformer increases their effective inductance while leaving their series resistance relatively unchanged. As a result, the Q of these inductive elements is increased and the phase noise generated by the oscillator is reduced. SpectreRF simulations of an LC oscillator with a center frequency of 5GHz were used to verify the performance of the proposed transformer-coupled resonator.
by Olumuyiwa Temitope Ogunnika.
S.M.
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Maneikis, Andrius. "Distribution On Load Tap Changer Control Using IEC61850 Client/Server Architecture." Thesis, KTH, Skolan för elektro- och systemteknik (EES), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-193673.
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Distributed generation is transforming the power system grid to decentralized system where separate units like wind power generators or solar panel shall coexist and operate in tandem in order to supplement each other and make one extensive system as a whole so called smart grid. It is utmost important to have a control ability over such units not only on a field level but on a system level as well. To be able to communicate with numerous devices and maintain interoperability universal standard is a must. Therefore, one of the core standards relevant to smart grids is IEC 61850 – Power Utility Automation which comes into assistance and tackles aforementioned challenges. This project uses IEC61850 architecture to implement client/server windows applications for on-load tap changer remote control. The proposed solution and designed applications are tested together with a real time simulator where simple power system is modelled to emulate the system response to control signals in a real time. In this way, the implemented applications can be tried and assessed as if performing in real environment. Consequently, a user of the client application is able to remotely control voltage on the power transformer's secondary side and manipulate the switching equipment simulated in the model.Distribuerad generation håller på att förändra transmissionsnätet till decentraliserat system där separata enheter som vindkraftverk eller solpanel skall samexistera och fungera tillsammans för att komplettera varandra och att göra ett omfattande system som helhet så kallade smarta elnät. Det är ytterst viktigt att ha en kontroll förmåga över sådana enheter inte bara på ett fältnivå utan även på systemnivå. För att kunna kommunicera med många enheter och bibehålla interoperabiliten som universell standard är ett måste. En av de grundläggande normer som är relevanta för smarta nät är IEC 61850 - Skydd & Automation, som kommer in i bistånd och möter ovan nämnda utmaningar. Detta projekt använder IEC61850-struktur för att implementera klient/server windows applikation för lindningskopplarens fjärrkontroll. Den föreslagna lösningen och utformade applikationer testas tillsammans med en realtidssimulator där enkelt kraftsystem modelleras för att emulera systemets svar på de givna styrsignalerna i realtid. På detta sätt kan de implementerade programmen prövas och bedömas hur de utföras i verklig miljö. Följaktligen kan användare av klientapplikationen fjärrstyra spänningen på transformatorns sekundärsida och manipulera ställverk som simuleras i modellen.
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Policarpi, Andrea. "Transformers architectures for time series forecasting." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2022. http://amslaurea.unibo.it/25005/.
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Time series forecasting is an important task related to countless applications, spacing from anomaly detection to healthcare problems. The ability to predict future values of a given time series is a nontrivial operation, whose complexity heavily depends on the number and the quality of data available. Historically, the problem has been addressed by statistical models and simple deep learning architectures such as CNNs and RNNs; recently many Transformer-based models have also been used, with excellent results.
This thesis work aims to evaluate the performances of two transformer-based models, namely a TransformerT2V and an Informer, when applied to time series forecasting problems, and compare them with non-transformer architectures.
Furthermore, a second contribution resides in the exploration of the Informer's Probsparse mechanism, and the suggestion of improvements to increase the model performances.
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Grzeszczak, Aleksander. "VLSI architecture for Discrete Wavelet Transform." Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/9908.
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In this thesis, we present a new simple and efficient VLSI architecture (DWT-SA) for computing the Discrete Wavelet Transform. The proposed architecture is systolic in nature, modular and extendible to 1-D or 2-D DWT transform of any size. The DWT-SA has been designed, simulated and implemented in silicon. The following are the features of the DWT-SA architecture: (1) It has an efficient (close to 100%) hardware utilization. (2) It works with data streams of arbitrary size. (3) The design is cascadable, for computation of one, two or three dimensional DWT. (4) It requires a minimum interface circuitry on the chip for purposes of interconnecting to a standard communication bus. The DWT-SA design has been implemented using CMOS 1.2 um technology.
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Ferreira, Costa Levy [Verfasser]. "Modular Power Converters for Smart Transformer Architectures / Levy Ferreira Costa." Kiel : Universitätsbibliothek Kiel, 2019. http://d-nb.info/1197055312/34.
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Skerry, Nathaniel S. (Nathaniel Standish) 1971. "Transformed materials : a material research center in Milan, Italy." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/70358.
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Thesis (M. Arch.)--Massachusetts Institute of Technology, Dept. of Architecture, 2002.Includes bibliographical references (p. 74-75).
[Transformed Materials] is an exploration into today's design methodologies of architecture production. The emergence of architectural form is questioned in relation to the temporal state of design intent and the physical material construct. At a time when there is an increased awareness of the current state of technology, material innovation and methods of fabrication, there are new speculations of what materiality is and can be. This thesis will propose an architecture that emerges through an exploration of the material concept that directly informs and expresses the fundamental ideas of the project. Building methods have changed widely over time, and are co-responsible for creating a dialog between functional requirements, technological invention, and material implication that reflects the current cultural state. Today's architectural products have in a sense reverted back to thin surfaces. Current cultural issues such as socioeconomic, environmental impact, transportability, efficiency, lightness, storability, technology, and mass production, have over time created a state of "thinness ". This project tries to offset the current trend of building by accepting the norms of architectural products, and reinventing their role within a contemporary language that explores more deeply the material qualities and properties associates with it. This thesis will use steel as the primary building material. Steel is a material that has become standardized in how it is shaped and formed, thus its ability to produce an architecture has been reduced purely to a dogmatiC approach of engineered solutions or preconceived results. Steel, is artificial by nature; if we suspend our preconceptions of steel, could the material be designed such that its role is critical in defining space, structure and program in a tectonic system? The area of research and examination will be focused on the design of a Material Research Center (mRC). located in Milan, Italy.
by Nathaniel S. Skerry.
M.Arch.
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Mandly, Clayton E. "Push Pull - Compulsory Interactions in Architecture." University of Cincinnati / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1428065491.
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Palmer, Joseph McRae. "The Hybrid Architecture Parallel Fast Fourier Transform (HAPFFT) /." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd855.pdf.
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Palmer, Joseph M. "The Hybrid Architecture Parallel Fast Fourier Transform (HAPFFT)." BYU ScholarsArchive, 2005. https://scholarsarchive.byu.edu/etd/555.
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The FFT is an efficient algorithm for computing the DFT. It drastically reduces the cost of implementing the DFT on digital computing systems. Nevertheless, the FFT is still computationally intensive, and continued technological advances of computers demand larger and faster implementations of this algorithm. Past attempts at producing high-performance, and small FFT implementations, have focused on custom hardware (ASICs and FPGAs). Ultimately, the most efficient have been single-chipped, streaming I/O, pipelined FFT architectures. These architectures increase computational concurrency through the use of hardware pipelining. Streaming I/O, pipelined FFT architectures are capable of accepting a single data sample every clock cycle. In principle, the maximum clock frequency of such a circuit is limited only by its critical delay path. The delay of the critical path may be decreased by the addition of pipeline registers. Nevertheless this solution gives diminishing returns. Thus, the streaming I/O, pipelined FFT is ultimately limited in the maximum performance it can provide. Attempts have been made to map the Parallel FFT algorithm to custom hardware. Yet, the Parallel FFT was formulated and optimized to execute on a machine with multiple, identical, processing elements. When executed on such a machine, the FFT requires a large expense on communications. Therefore, a direct mapping of the Parallel FFT to custom hardware results in a circuit with complex control and global data movement. This thesis proposes the Hybrid Architecture Parallel FFT (HAPFFT) as an alternative. The HAPFFT is an improved formulation for building Parallel FFT custom hardware modules. It provides improved performance, efficient resource utilization, and reduced design time. The HAPFFT is modular in nature. It includes a custom front-end parallel processing unit which produces intermediate results. The intermediate results are sent to multiple, independent FFT modules. These independent modules form the back-end of the HAPFFT, and are generic, meaning that any prexisting FFT architecture may be used. With P back-end modules a speedup of P will be achieved, in comparison to an FFT module composed solely of a single module. Furthermore, the HAPFFT defines the front-end processing unit as a function of P. It hides the high communication costs typically seen in Parallel FFTs. Reductions in control complexity, memory demands, and logical resources, are achieved. An extraordinary result of the HAPFFT formulation is a sublinear area-time growth. This phenomenon is often also called superlinear speedup. Sublinear area-time growth and superlinear speedup are equivalent terms. This thesis will subsequently use the term superlinear speedup to refer to the HAPFFT's outstanding speedup behavior. A further benefit resulting from the HAPFFT formulation is reduced design time. Because the HAPFFT defines only the front-end module, and because the back-end parallel modules may be composed of any preexisting FFT modules, total design time for a HAPFFT is greatly reduced
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Camarda, Florent. "Développement d'une architecture reconfigurable pour transformée de Fourier rapide." Rennes, INSA, 2012. http://www.theses.fr/2012ISAR0036.
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Ce rapport traite du développement d'une architecture de Transformée de Fourier Rapide (TFR) reconfigurable pouvant répondre à la plupart des besoins nécessaires aux systèmes de communications numériques employant les modulations multiporteuses de type OFDM. Le premier chapitre rappelle la théorie du signal OFDM de base implique l'utilisation d'une Transformée de Fourier Discrète Inverse (TFDI) à l'émission et d'une Transformée de Fourier Discrète Directe (TFD) en réception. Cette opération constitue alors la plus importante complexité de réalisation matérielle donnant ainsi une importance évidente à son optimisation. Ce chapitre met également en avant le fait que bon nombre d'évolutions de ce type de modulation impliquent l'utilisation de TFD supplémentaires. Le second chapitre a pour but d'apporter une exploration non exhaustive des architectures existantes capable de traiter ces opérations. Des généralités sur les concepts architecturaux sont alors présentées ainsi que les différentes possibilités en matière de reconfiguration de ces dernières. Ainsi différentes architectures existantes sont classifiées selon le type d'algorithme de TFR qu'elles sont capables de traiter mais également selon leur possibilité de reconfiguration. Le troisième chapitre traite quant à lui des deux algorithmes de TFR qui sont exploitables par l'architecture proposée. Après des généralités sur quelques principaux algorithmes et leur classification, les deux algorithmes du Radix et de Winograd (Winograd Fourier Transform Algorithm WFTA) sont étudiés en profondeur. Cette étude montre alors qu'une combinaison astucieuse de ces deux algorithmes permet de traiter un grand ensemble possible de tailles de TFR. Le chapitre quatre présente l'architecture proposée, principale contribution de cette thèse. Cette architecture s'articule autour de trois principaux éléments : le papillon reconfigurable, l'application des coefficients de rotation et les mémoires nécessaires au stockage des données. Deux propositions de configuration sont proposées permettant d'optimiser l'architecture en termes de débit ou de ressources utilisées. Le contrôle de ces éléments est également présenté afin de permettre son implantation matérielle. Le chapitre suivant traite de la représentation des nombres au sein de l'architecture proposée. Après avoir présenté les représentations les plus courantes que sont la représentation en virgule fixe et celle en virgule flottante, l'étude de la représentation des nombres au sein de l'architecture est présentée en virgule fixe. Cette étude conduit alors à des résultats de simulation sur les performances atteignables par l'architecture en termes de Rapport Signal sur Bruit de Quantification (RSBQ). Le dernier chapitre traite de l'application de cette architecture dans le contexte de Télévision Numérique Terrestre (TNT). On rappelle pour les trois standards de diffusion de la TNT que sont DMB-T, ISDB-T et DVB-T les décompositions possibles conduisant à l'estimation des ressources nécessaires. Après quoi une étude des contraintes temporelles liées au contexte de diffusion (donc temps réel) permettra de définir la fréquence minimale nécessaire au bon fonctionnement de l'architecture. Enfin une conclusion générale résumera les avantages et inconvénients de la solution proposée. Elle permettra également de recenser quelques ouvertures possibles à ces travauxThis manuscript deals with the implementation of a reconfigurable Fast Fourier Transform architecture. The architecture is suitable for almost all the digital communication systems h using OFDM modulation. The first chapter starts with a reminder of the OFDM signal theories for which an Inverse Discrete Fourier Transform (lOFT) is required on the transmitter side as well as a Direct Discrete Fourier Transform (DFT) on the receiver side. This operation involves one of the greatest complexities of hardware implementation so that its optimization has a great importance. This chapter also presents the multiple ways in which the DFT and its inverse can be used in advanced OFDM modulations and demodulations. The goal of the second chapter is to explore the different ways of implementing the FFT. First, some general principles of the digital architectures are presented as well as the reconfiguration possibilities. Then, several FFT architectures are compared and classified depending on the way the operation is computed and whether the architecture is reconfigurable or not. The third chapter presents two algorithms of Fast Fourier Transform (FFT) which are computable via the proposed architecture. After a quick presentation and classification of the main different FFT algorithms, both the Radix algorithm and the Winograd Fourier Transform Algorithm (WFTA) are studied in depth. This study leads to the possibility of a clever combination of these two algorithms allowing then to compute a larger group of FFT sizes. Chapter four presents the proposed architecture, which is the major contribution of this PhD thesis. This architecture involves three main elements: the reconfigurable butterfly, the twiddle factors computation and data storage in memories. Two configurations of the architecture are proposed. The first allows high throughput for the results of the operation while the second one is optimized in resources use and power consumption. A control architecture for the computation units is also presented. The following chapter introduces the issue of number representations in hardware descriptions. The two most important data representation forms (fixed point and floating point) are presented. As the fixed-point representation is retained in order to reduce the hardware complexity, a study presents the impact of the imperfect representation of real values. Results are given in order to choose the best compromises between the computing precision and the resources needs. These results are given in terms of Signal to Quantization Noise Ratio for several given data widths. The last chapter provides results of the implementation of the architecture for the Digital Terrestrial Television Broadcasting (DTIB) application. Lt first evokes the main features of the three DTIB standards that are considered (DVB, DMB and ISDB). Then the implementations parameters are presented for the two configurations presented in the fourth chapter. Results are then given in terms of resources use for many data widths as well as for time performances. A general conclusion sums up all the results and lists all the advantages and drawbacks of the proposed architecture. Some perspectives are given in order to lead to many optimizations as well as an implementation on an Application Specifie lntegrated Circuit (ASIC) target
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Huluta, Emanuil. "Discrete wavelet transform architecture for image coding and decoding." Thesis, University of Ottawa (Canada), 2003. http://hdl.handle.net/10393/26491.
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This thesis analyses and implements a Discrete Wavelet Transform (DWT) architecture for image processing. The architecture comprises two modules, one for image coding and the other for image decoding. Each module is implemented using a novel Modified Forward-Backward Register Allocation (MFBRA) method and accommodates two Fast Processing Elements (FPE). The resulting architecture minimizes the hardware required to perform the task together with reduced processing time, rendering the whole structure suitable for real time applications. The whole architecture is implemented and simulated using the Verilog Hardware Description Language.
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Chen, Long. "Optimizing the Fast Fourier Transform on a many-core architecture." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 66 p, 2008. http://proquest.umi.com/pqdweb?did=1459924761&sid=28&Fmt=2&clientId=8331&RQT=309&VName=PQD.
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Pajayakrit, A. "VLSI architecture and design for the Fermat Number Transform implementation." Thesis, University of Newcastle Upon Tyne, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.379767.
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Sazish, Abdul Naser. "Efficient architectures and power modelling of multiresolution analysis algorithms on FPGA." Thesis, Brunel University, 2011. http://bura.brunel.ac.uk/handle/2438/6290.
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In the past two decades, there has been huge amount of interest in Multiresolution Analysis Algorithms (MAAs) and their applications. Processing some of their applications such as medical imaging are computationally intensive, power hungry and requires large amount of memory which cause a high demand for efficient algorithm implementation, low power architecture and acceleration. Recently, some MAAs such as Finite Ridgelet Transform (FRIT) Haar Wavelet Transform (HWT) are became very popular and they are suitable for a number of image processing applications such as detection of line singularities and contiguous edges, edge detection (useful for compression and feature detection), medical image denoising and segmentation. Efficient hardware implementation and acceleration of these algorithms particularly when addressing large problems are becoming very chal-lenging and consume lot of power which leads to a number of issues including mobility, reliability concerns. To overcome the computation problems, Field Programmable Gate Arrays (FPGAs) are the technology of choice for accelerating computationally intensive applications due to their high performance. Addressing the power issue requires optimi- sation and awareness at all level of abstractions in the design flow. The most important achievements of the work presented in this thesis are summarised here. Two factorisation methodologies for HWT which are called HWT Factorisation Method1 and (HWTFM1) and HWT Factorasation Method2 (HWTFM2) have been explored to increase number of zeros and reduce hardware resources. In addition, two novel efficient and optimised architectures for proposed methodologies based on Distributed Arithmetic (DA) principles have been proposed. The evaluation of the architectural results have shown that the proposed architectures results have reduced the arithmetics calculation (additions/subtractions) by 33% and 25% respectively compared to direct implementa-tion of HWT and outperformed existing results in place. The proposed HWTFM2 is implemented on advanced and low power FPGA devices using Handel-C language. The FPGAs implementation results have outperformed other existing results in terms of area and maximum frequency. In addition, a novel efficient architecture for Finite Radon Trans-form (FRAT) has also been proposed. The proposed architecture is integrated with the developed HWT architecture to build an optimised architecture for FRIT. Strategies such as parallelism and pipelining have been deployed at the architectural level for efficient im-plementation on different FPGA devices. The proposed FRIT architecture performance has been evaluated and the results outperformed some other existing architecture in place. Both FRAT and FRIT architectures have been implemented on FPGAs using Handel-C language. The evaluation of both architectures have shown that the obtained results out-performed existing results in place by almost 10% in terms of frequency and area. The proposed architectures are also applied on image data (256 £ 256) and their Peak Signal to Noise Ratio (PSNR) is evaluated for quality purposes. Two architectures for cyclic convolution based on systolic array using parallelism and pipelining which can be used as the main building block for the proposed FRIT architec-ture have been proposed. The first proposed architecture is a linear systolic array with pipelining process and the second architecture is a systolic array with parallel process. The second architecture reduces the number of registers by 42% compare to first architec-ture and both architectures outperformed other existing results in place. The proposed pipelined architecture has been implemented on different FPGA devices with vector size (N) 4,8,16,32 and word-length (W=8). The implementation results have shown a signifi-cant improvement and outperformed other existing results in place. Ultimately, an in-depth evaluation of a high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called func-tional level power modelling approach have been presented. The mathematical techniques that form the basis of the proposed power modeling has been validated by a range of custom IP cores. The proposed power modelling is scalable, platform independent and compares favorably with existing approaches. A hybrid, top-down design flow paradigm integrating functional level power modelling with commercially available design tools for systematic optimisation of IP cores has also been developed. The in-depth evaluation of this tool enables us to observe the behavior of different custom IP cores in terms of power consumption and accuracy using different design methodologies and arithmetic techniques on virous FPGA platforms. Based on the results achieved, the proposed model accuracy is almost 99% true for all IP core's Dynamic Power (DP) components.
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Tan, Kay-Chuan Benny. "Low power JPEG2000 5/3 discrete wavelet transform algorithm and architecture." Thesis, University of Edinburgh, 2004. http://hdl.handle.net/1842/14517.
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With the advance in VLSI digital technology, many high throughput and performance imaging and video application had emerged and increased in usage. At the core of these imaging and video applications is the image and video compression technology. Image and video compression processes are by nature very computational and power consuming. Such high power consumption will shorten the operating time of a portable imaging and video device and can also cause overheating. As such, ways of making image and video compression processes inherently low power is needed. The lifting based Discrete Wavelet Transform (DWT) is increasingly used for compression digital image data and is the basis for the JPEG2000 standard (ISO/IEC 15444). Even though the lifting based DWT had aroused considerable implementation of this algorithm, there is no work on the low power realisation of such algorithm. Recent JPEG20O0 DWT implementations are pipelined data-path centric designs and do not consider the issue of power. This thesis therefore sets out to realise a low power JPEG2000 5/3 lifting based DWT hardware architecture and investigates whether optimising at both algorithmic and architectural level will yield a lower power hardware. Besides these, this research also ascertain whether the accumulating Arithmetic Logic Unit (ALU) centric processor architecture is more low power than the feed-through pipelined data-path centric processor architecture. A number of novel implementation schemes of the realisation of a low power JPEG2000 5/3 lifting based DWT hardware are proposed and presented in this thesis. These schemes target to reduce the switched capacitance by reducing the number of computational steps and data-path/arithmetic hardware through the manipulation of the lifting-based 5/3 DWT algorithm, operation scheduling and alteration to the traditional processor architecture. These resulted in a novel SA-ALU centric JPEG2000 5/3 lifting based DWT hardware architecture that saves about 25% of hardware with respect to the two presented existing 5/3 DWT lifting-based architecture.
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Bandyopadhyay, Abhishek. "Matrix transform imager architecture for on-chip low-power image processing." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-08192004-133909/unrestricted/bandyopadhyay%5Fabhishek%5F200412%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.Smith, Mark, Committee Member ; DeWeerth, Steve, Committee Member ; Jackson, Joel, Committee Member ; David Anderson, Committee Member ; Hasler, Paul, Committee Chair. Includes bibliographical references.
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McCanny, P. "Generic silicon architectures for the two-dimensional discrete wavelet transform." Thesis, Queen's University Belfast, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.403167.
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Benaissa, Mohammed. "VLSI algorithms, architectures and design for the Fermat Number Transform." Thesis, University of Newcastle Upon Tyne, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.254020.
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Ahmed, Mohamed Hassan Abouelella. "Power Architectures and Design for Next Generation Microprocessors." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/103175.
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With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements, but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. Recently, data centers have replaced the 12V DC server rack distribution with a 48V DC distribution, producing a significant overall system efficiency improvement. However, 48V rack architecture raises significant challenges for the voltage regulator modules (VRMs) required for powering the processor. The 48V VRM in the vicinity of the CPU needs to be designed with very high efficiency, high power density, high light-load efficiency, as well as meet all transient requirements by the CPU and GPU.
Transferring the well-developed multi-phase buck converter used in the 12V VRM to the 48V distribution platform is not that simple. The buck converter operating with 48V, stepping down to sub 2V, will be subjected to significant switching related loss, resulting in lower overall system efficiency. These challenges drive the need to look for more efficient architectures for 48V VRM solutions.
Two-stage conversions can help solve the design challenges for 48V VRMs. A first-stage unregulated converter is used to step-down the 48V to a specific intermediate bus voltage. This voltage will feed a multi-phase buck converter that powers the CPU. An unregulated LLC converter is used for the first-stage converter, with zero voltage switching (ZVS) operation for the primary side switches, and zero current switching (ZCS) along with ZVS operation, for the secondary side synchronous rectifiers (SRs). The LLC converter can operate at high frequency, in order to reduce the magnetic components size, while achieving high-efficiency. The high-efficiency first-stage, along with the scalability and high bandwidth control of the second-stage, allows this architecture to achieve high-efficiency and power density. This architecture is simpler to adopt by industry, by plugging the unregulated converter before the existing multi-phase buck converters on today's platforms.
The first challenge for this architecture is the transformer design of the first-stage LLC converter. It must avoid all of the loss associated with high frequency operations, and still achieve high power density without scarifying efficiency. In this thesis, the integrated matrix transformer structure is optimized by SR integration with windings, interleaved primary side termination, and a better PCB winding arrangement to achieve high-efficiency and power density, and minimize the losses associated with high-frequency operations.
The second challenge is the light load efficiency improvement. In this thesis a light load efficiency improvement is proposed by a dynamic change of the intermediate bus voltage, resulting in more than 8 % light load efficiency improvements. The third challenge is the selection of the optimal bus voltage for the two-stage architecture. The impact of different bus voltages was analyzed in order to maximize the overall conversion efficiency. Multiple 48V unregulated converters were designed with maximum efficiency >98 %, and power densities >1000 W/in3, with different output voltages, to select the optimal bus voltage for the two-stage VRM.
Although the two-stage VRM is more scalable and simpler to design and adopt by current industry, the efficiency will reduce as full power flows in two cascaded DC/DC converters. Single-stage conversion can achieve higher-efficiency and power-density. In this thesis, a quasi-parallel Sigma converter is proposed for the 48V VRM application. In this structure, the power is shared between two converters, resulting in higher conversion efficiency. With the aid of an optimized integrated magnetic design, a Sigma converter suitable for narrow voltage range applications was designed with 420 W/in3 and a maximum efficiency of 94 %. Later, another Sigma converter suitable for wide voltage range applications was designed with 700W/in3 and a maximum efficiency of 95 %. Both designs can achieve higher efficiency than the two-stage VRM and all other state-of-art solutions. The challenges associated with the Sigma converter, such as startup and closed loop control were addressed, in order to make it a viable solution for the VRM application.
The 48V rack architecture requires regulated 12V output converters for various loads. In this thesis, a regulated LLC is used to design a high-efficiency and power-density 48V bus converter. A novel integration method of the inductor and transformer helps the LLC achieve the required regulation capability with minimum losses, resulting in a converter that can provide 1KW of continuous power with efficiency of 97.8 % and 700 W/in3 power density.
This dissertation discusses new power architectures with an optimized design for the 48V rack architectures. With the academic contributions in this dissertation, different conversion architectures can be utilized for 48V VRM solutions that solve all of the challenges associated with it, such as scalability, high-efficiency, high density, and high BW control.Doctor of Philosophy
With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. The data center manufacturers have recently adopted a more efficient architecture that supplies a 48V DC server rack distribution instead of a 12V DC distribution to the server motherboard. This helped reduce costs and losses, but as a consequence, raised a challenge in the design of the DC/DC voltage regulator modules (VRM) supplied by the 48V, in order to power the CPU and GPU. In this work, different architectures will be explored for the 48V VRM, and the trade-off between them will be evaluated. The main target is to design the VRM with very high-efficiency and high-power density to reduce the cost and size of the CPU/GPU motherboards. First, a two-stage power conversion structure will be used. The benefit of this structure is that it relies on existing technology using the 12V VRM for powering the CPU. The only modification required is the addition of another converter to step the 48V to the 12V level. This architecture can be easily adopted by industry, with only small modifications required on the system design level. Secondly, a single-stage power conversion structure is proposed that achieves higher efficiency and power density compared to the two-stage approach; however, the structure is very challenging to design and to meet all requirements by the CPU/GPU applications. All of these challenges will be addressed and solved in this work. The proposed architectures will be designed using an optimized magnetic structure. These structures achieve very high efficiency and power density in their designed architectures, compared to state-of-art solutions. In addition, they can be easily manufactured using automated manufacturing processes.
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Beraldin, Jean-Angelo. "VLSI systolic array architecture for the computation of the discrete fourier transform." Thesis, University of Ottawa (Canada), 1986. http://hdl.handle.net/10393/5042.
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Xue, Liping. "Efficient mapping of fast Fourier transform on the Cyclops-64 multithreaded architecture." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 88 p, 2007. http://proquest.umi.com/pqdweb?did=1397913041&sid=16&Fmt=2&clientId=8331&RQT=309&VName=PQD.
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Lawanghare, Amit Rajiv. "EXTRACT TRANSFORM AND LOADING TOOL FOR EMAIL." CSUSB ScholarWorks, 2019. https://scholarworks.lib.csusb.edu/etd/935.
Full textAbstract:
This project focuses on applying Extract, Transform and Load (ETL) operations on the relational data exchanged via emails. An Email is an important form of communication by both personal and corporate means as it enables reliable and quick exchange. Many useful files are shared as a form of attachments which contains transactional/ relational data. This tool allows a user to write the filter conditions and lookup conditions on attachments; define the attribute map for attachments to the database table. The Data Cleansing for each attribute can be performed writing rules and their matching state. A user can add custom functions for the data transformation. The aggregation of the data is done in the form of reports after the operation of data loading into the database is complete. The tool needs one-time setup per file template and its automated from that point.
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Martin, Jérémy. "Caractérisation en commutation douce d'IGBT 6,5 kV pour l'application transformateur moyenne fréquence en traction ferroviaire." Thesis, Toulouse, INPT, 2010. http://www.theses.fr/2010INPT0037/document.
Full textAbstract:
Ce travail concerne l’étude et la réalisation d’une architecture multicellulaire de conversion d’énergie électrique haute tension avec étage intermédiaire alternatif moyenne fréquence destinée à la traction électrique ferroviaire. L’objectif de ce travail est de diminuer la masse et le volume de l’étage de conversion alternatif-continu que l’on retrouve dans les engins de traction conçus pour circuler sur les réseaux alternatifs 25kV-50Hz ou 15kV-16Hz2/3. La recherche de gains sur l’étage de conversion alternatif-continu s’applique aussi bien sur les automotrices où l’on cherche à gagner de la place disponible pour y placer des passagers que sur les locomotives ou encore sur les motrices de TGV où l’on recherche un gain de masse étant donné que ces engins sont en limite de charge à l’essieu. Le contexte de la haute tension implique l’utilisation d’interrupteurs de forts calibres en tension pour limiter au maximum le nombre de cellules de conversions utilisées. D’un autre côté, la recherche de gains sur le transformateur nécessite une fréquence de découpage élevée, génératrice de pertes en commutation dans les interrupteurs. L’architecture de conversion retenue permet par l’association de structures duales d’obtenir des conditions de commutation douce, ce qui est favorable à une montée en fréquence avec des interrupteurs de forts calibres en tension. Le convertisseur élémentaire associe un onduleur de tension commandé au blocage et un commutateur de courant commandé à l’amorçage. Afin d’évaluer le rendement de l’architecture considérée, un prototype d’un bloc de conversion élémentaire, d’une puissance de 280 kVA, a été réalisé au laboratoire PEARL. Les interrupteurs sont réalisés sur la base de modules IGBT 6,5kV/200A. Les essais en commutation douce ont permis d’évaluer, dans des conditions de fonctionnement réelles, les pertes dans les modules IGBT. Compte tenu de ces résultats, il est possible de déterminer les limites de fonctionnement de la structure de conversion et d’effectuer un dimensionnement en considérant le compromis rendement-poids-volume pour un engin de traction donnéThis thesis concerns the study and the rating of a high voltage multicellular converter with an intermediate medium frequency stage dedicated to railway traction. The objective is to reduce the weight and the volume of the AC-DC conversion stage which is implemented in railway engines running on 25kV-50Hz or 15kV-16Hz2/3 railways. Reduction on weight and size of the AC-DC converter may be applied on multiple unit trains where the transformer causes room loss for passengers and on locomotives and high speed trains where the axle load is limited. On one hand high voltage switches are required in order to minimize the number of cells used to build the converter. On the other hand, reducing the size and the weight of the transformer requires a high switching frequency, causing high commutation losses. To achieve soft switching conditions with high voltage semiconductors, the proposed topology is based on an association of dual structures. Each elementary converter combines a controlled turn-off voltage source inverter and a controlled turn-on current source inverter. In order to estimate the efficiency of the new topology, a prototype of one elementary cell working at 280 kVA, was built at the Power Electronics Associated Research Laboratory (PEARL). The switches are standard 6.5 kV/200A IGBTs modules. Soft-switching tests, in real operating conditions, allow evaluating IGBTs and diodes switching losses. Thanks to these results, it is possible to find the structure operating limits and to size the transformer considering the trade-off between the system efficiency and the transformer weight
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Vargas, Ana Cristina S. M. Massachusetts Institute of Technology. "Tracing public space : a participatory approach to transform public spaces in low-income communities." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91418.
Full textAbstract:
Thesis: S.M., Massachusetts Institute of Technology, Department of Architecture, 2014.Cataloged from PDF version of thesis. Vita.
Includes bibliographical references (pages 133-135).
Rapid urban growth has challenged our traditional planning methods. It has been a driver for the increase of overcrowded informal settlements in major cities of the developing world, which shelter one third of the world population. Lack of infrastructure, open spaces, and unsafe structures challenge the livelihoods of their citizens. Consequently, over the last fifty years, governments have addressed this issue in different ways, from eradicating informal settlements and building new housing, to retrofitting the existing conditions with infrastructure and public spaces through slum rehabilitation. Accepting the idea of working with existing developments to improve the status quo, architects, planners, artists and activists in general have relied on participatory planning and community engagement to improve urban conditions by addressing underlying local needs through small-scale interventions. This thesis introduces a new methodology to study, create awareness and inspire future leaders, children, to take action to transform public spaces in high-density informal settlements. It proposes a multi scalar bottom-up analysis, with innovative tools of representation and design to address the challenges of community public spaces. The 'Tracing Public Space' method has been developed through fieldwork in India, Venezuela and the USA. The method is based in observation, representation and design using a 'toolkit' that enables a two-way learning process between the designer as an 'outsider' and children as 'insiders'. The thesis is focused on fieldwork done in the Malvani Transit Camp in Mumbai where over forty years of informal and permanent growth the existence of open shared courtyards is threatened. These small-scale open spaces are crucial for communities, and particularly for the women and children who are their main users. Tracing Public Space becomes a vehicle to sensitize the community to protect courtyards from encroachments and promote an inclusive and adaptive use of shared space.
by Ana Cristina Vargas.
S.M.
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Al-Azawi, Saad Mohammed Saleh. "Efficient architectures for multidimensional discrete transforms in image and video processing applications." Thesis, University of Newcastle upon Tyne, 2013. http://hdl.handle.net/10443/2131.
Full textAbstract:
This thesis introduces new image compression algorithms, their related architectures and data transforms architectures. The proposed architectures consider the current hardware architectures concerns, such as power consumption, hardware usage, memory requirement, computation time and output accuracy. These concerns and problems are crucial in multidimensional image and video processing applications. This research is divided into three image and video processing related topics: low complexity non-transform-based image compression algorithms and their architectures, architectures for multidimensional Discrete Cosine Transform (DCT); and architectures for multidimensional Discrete Wavelet Transform (DWT). The proposed architectures are parameterised in terms of wordlength, pipelining and input data size. Taking such parameterisation into account, efficient non-transform based and low complexity image compression algorithms for better rate distortion performance are proposed. The proposed algorithms are based on the Adaptive Quantisation Coding (AQC) algorithm, and they achieve a controllable output bit rate and accuracy by considering the intensity variation of each image block. Their high speed, low hardware usage and low power consumption architectures are also introduced and implemented on Xilinx devices. Furthermore, efficient hardware architectures for multidimensional DCT based on the 1-D DCT Radix-2 and 3-D DCT Vector Radix (3-D DCT VR) fast algorithms have been proposed. These architectures attain fast and accurate 3-D DCT computation and provide high processing speed and power consumption reduction. In addition, this research also introduces two low hardware usage 3-D DCT VR architectures. Such architectures perform the computation of butterfly and post addition stages without using block memory for data transposition, which in turn reduces the hardware usage and improves the performance of the proposed architectures. Moreover, parallel and multiplierless lifting-based architectures for the 1-D, 2-D and 3-D Cohen-Daubechies-Feauveau 9/7 (CDF 9/7) DWT computation are also introduced. The presented architectures represent an efficient multiplierless and low memory requirement CDF 9/7 DWT computation scheme using the separable approach. Furthermore, the proposed architectures have been implemented and tested using Xilinx FPGA devices. The evaluation results have revealed that a speed of up to 315 MHz can be achieved in the proposed AQC-based architectures. Further, a speed of up to 330 MHz and low utilisation rate of 722 to 1235 can be achieved in the proposed 3-D DCT VR architectures. In addition, in the proposed 3-D DWT architecture, the computation time of 3-D DWT for data size of 144×176×8-pixel is less than 0.33 ms. Also, a power consumption of 102 mW at 50 MHz clock frequency using 256×256-pixel frame size is achieved. The accuracy tests for all architectures have revealed that a PSNR of infinite can be attained.
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Lu, I.-Hung, and 呂毅鴻. "A New Architecture and Its Implementation of a Discrete Cosine Transformer." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/43314484003941545817.
Full textAbstract:
碩士國立成功大學
電機工程學系
85
The discrete cosine transform (DCT) has been widely recognized as the most effective technique in the area of speech and image/video data compression. It also has been considered as the standard transform coding algorithm for image compression in JPEG (Joint Photographic Experts), MPEG (Motion Picture Experts Group). In this thesis, we purpose a new architecture for the fast computation of a DCT. A new systolic array is proposed to compute the two-dimensional (2-D) DCT based on row-column decomposition. This architecture uses N2 multipliers to evaluate N×N-point DCT at a rate of one complete transform per N clock cycle. It processes the feature of regularity and modularity, and is thus well suited to VLSI implementation. Compared to existing regular architectures for the 2-D DCT, our method has better throughout performance, smaller area-time, and low communication complexity. The simulation results demonstrate that our architecture have good fixed-point error performance for real image. So the architecture is useful for applications required high throughput rates. The chip uses 25 MHz image sampling signal frequency. It was design by using cell-based methodology and fabricated with 0.6 μm SPDM technology. The gate count of the chip is about 70000 and the die area is 6150 μm×6150μm.
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Luo, Shih-Jyun, and 羅士竣. "Research of Watt-Level Parallel-Parallel Transformer Combined CMOS Power Amplifier with 3-D Architecture." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/37432317683103674474.
Full textAbstract:
碩士國立臺灣大學
電信工程學研究所
104
With the development of wireless communication and the evolution of semiconductor process, the radio frequency integrated circuit implemented in CMOS technology become the focal point in the industry with cost advantage. The power amplifier is the most critical component in the transceiver design. Thus the main focus of this thesis is on the design and analysis of power amplifier in CMOS. The chapter 2 describes a 24 GHz three series-connected (stacked) power amplifier implemented in 90 nm CMOS process. Increasing the supply voltage by stacking FETs to increase the power density per area without sacrificing reliability, and choosing the gate capacitance to generate the proper load impedance of each stacked-transistor by actual simulation. Adopting transformer in input and output terminals to achieve impedance matching, power combining and single to differential ended simultaneously in push-pull topology. The chip size is 0.27 mm2 and output power is 21.7 dBm. The chapter 3 describes a 77 GHz transformer combined power amplifier with 3-D architecture implemented in 90 nm CMOS process. The radial power combiner and splitter achieve the 8-ways power combination to increase output power. The radial power combiner with the function of impedance transformation reduces the impedance transformation ratio of output matching networks and alleviates the loss caused by large impedance transformation ratio. Sharing the center area of the chip to form a 3-D structure and thus the area occupied by the power combiner and power splitter can be reduced. The power cell adopts the transformer to realize power combining, impedance matching and single to differential ended simultaneously. The chapter 4 describes a 5 GHz high output power transformer combined power amplifier implemented in LDMOS process. By parallel-parallel combining transformer technique, the multiple transformers realize in the same area to reduce the area of multiple transformers in multi-way power combination. Thus it can maintain the area as 1-way transformer and function of multi-way power combination simultaneously. And using the 3-D radial architecture described in chapter 3 to further reduce the chip area.
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Hsiao, Yu-Feng, and 蕭淯方. "Research of K-band CMOS Transformer Combined Power Amplifier With 3-D Architecture and Efficiency Enhancement Technique." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/15253413046392828272.
Full textAbstract:
碩士國立臺灣大學
電信工程學研究所
101
With the development of wireless communication, the radial frequency integrated circuit with CMOS technology is valued gradually in the industry. Among the transceiver, power amplifier is the most critical component. As the reasons, the design and analysis of CMOS power amplifier is focused in this thesis. In chapter 2, an ultra-compact 24-GHz power amplifier implemented in 180-nm CMOS process. For compact chip size design, transformers are adopted to accomplish the functions of power combining, impedance matching and single-to-differential ended simultaneously. A virtual ground is generated at the symmetry of circuit by push-pull topology. DC bias can be fed directly without large value bypass capacitors, and the chip size is further reduced. The power amplifier achieves the smallest chip size 0.26 mm2 and the highest area efficiency around 24-GHz. In chapter 3, a K-band high output power transformer combined power amplifier with 3-D architecture implemented in 65-nm CMOS process. In order to achieve high output power, 8-ways power combining is realized by the radial splitter and radial combiner. The radial networks with the function of impedance transformation to alleviate the loss of input and output matching networks caused by large impedance transformation ratio. Thanks to the radial structure, the power splitter and power combiner can share the center area of the circuit by a 3-D architecture, therefore the area occupied by power splitter and power combiner can be reduced significantly. The power amplifier achieves the highest saturated output power 26.1 dBm with excellent area efficiency at K-band. In chapter 4, a 2-GHz Doherty power amplifier implemented in 180-nm CMOS process. All passive elements with λ/4 topology are fabricated off-chip on FR-4 board to diminish the chip size and mitigate the loss caused by elements to improve efficiency. The power amplifier performs 20% PAE and maintains 19% PAE at 6 dB power back-off.
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Vasanta, Lakshmi Kommineni. "Integrating A New Cluster Assignment And Scheduling Algorithm Into An Experimental Retargetable Code Generation Framework." Thesis, 2006. http://hdl.handle.net/2005/414.
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This thesis presents a new unified algorithm for cluster assignment and acyclic region
scheduling in a partitioned architecture, and preliminary results on its integration into an experimental retargetable code generation framework. The object of this work is twofold. Firstly, to validate for the first time, and evaluate the framework which is almost automatic, so as to gain insights into possibilities for improvement. This was done by using as a baseline for comparison, highly optimized code generated by the handcrafted compiler of Texas Instruments, the TI Code Composer Studio V2. The second objective is to compare the integrated scheduling algorithm with another well known algorithm which performs scheduling and cluster allocation in the same phase, the Unified Assign and Schedule (UAS) algorithm. The computational complexity of the two algorithms is
comparable.
The components of the framework experimented with here are (a) a tree transformer generator, which takes as input, a description of the instruction set of the target architecture in the form of a regular tree grammar augmented with actions and attributes, and outputs a data dependency directed acyclic graph, (b) the well known public domain IMPACT front end for C, (c)a microarchitecture description module which uses a modification of the HMDES architecture description language of the TRIMARAN project, to include cluster information, and (d) a combined cluster allocator and acyclic region scheduler and a register allocator designed and implemented by us. Experiments have been carried out on creating the proper interfaces for all the modules to work together, and the targeting of the tool to the Texas Instruments TMS320c62x architecture to establish the feasibility of this approach. We present the results of our implementation on a set of benchmarks and some sorting programs and compare them with those obtained from the state-of-the-art TI compiler. The performance without software pipelining shows that our executables take on the average 1.4 times the execution time as that of those generated by the TI compiler. The integrated scheduling algorithm proposed in this thesis performs
at least as well as the UAS algorithm and sometimes better by as much as 9 % in terms
of the parallelism obtained.
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Chen, Chien-Ting, and 陳建廷. "Efficient VLSI Architecture for Fresnel Transform." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/71005980707713104776.
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Kuo, Wei-de, and 郭德威. "IMPROVED ARCHITECTURE OF FAST FOURIER TRANSFORM PROCESSOR." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/45048953410850131465.
Full textAbstract:
碩士大同大學
電機工程學系(所)
96
In this thesis, the proposed design adopts SDF architecture. Moreover, we propose a new variable-length FFT processor with a novel algorithm, radix-2/4/8/16, for OFDM communication system. Due to the regularity and lowest hardware circuit complexity, radix-2/4/8/16 can efficiently minimize the number of complex multiplications and be implemented in VLSI design, especially in pipeline-based architecture. The proposed FFT processor can be used for the required length of IEEE 802.16 (WiMAX) standard. We have introduced some FFT algorithms. Due to implement more different length, we need a algorithm that can suit all 2n-point systems. In contrast, mixed-radix 4/2 FFT algorithm is capable of producing hardware with structure regularity, and it is more efficient than radix-2 FFT algorithm. It is therefore selected for improving adaptability and facilitation, and this FFT processor has been implemented by using VerilogHDL, ModelSim and Xilinx ISE for circuit design and simulation, respectively.
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CHEN, MING-YANG, and 陳明陽. "Systolic architectures for discrete fourier transform." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/20937983895892504372.
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Poplin, Dwight. "Distributed arithmetic architecture for the discrete cosine transform." Thesis, 1997. http://hdl.handle.net/1957/34243.
Full textAbstract:
The Discrete Cosine Transform is used in many image and video compression
standards. Many methods have been developed for efficiently computing the Discrete
Cosine Transform including flowgraph algorithms, distributed arithmetic and
two-dimensional decompositions.
A new architecture based on distributed arithmetic is presented for computing
the Discrete Cosine Transform and it's inverse. The main objective of the design is
to minimize the area of the VLSI implementation while maintaining the throughput
necessary for video and image compression standards such as MPEG and JPEG.
Several improvements have been made compared to previously published distributed
arithmetic architectures. These include elimination of four lookup tables and implementation
of the lookup tables using logic instead of ROM.
A model of the proposed architecture was written in C. The model was used to
verify the accuracy of the architecture and to do JPEG compression on a series of
test images. Behavioral simulations were performed with a hardware model written
in the Verilog hardware description language. These behavioral simulations verify
that the hardware implementation matches the C model. The model was synthesized
using the Synopsis synthesis tool. The gate count and clock rate of the design were
estimated using the synthesis results.Graduation date: 1997
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Wu, Po-Cheng, and 吳柏成. "Discrete Wavelet Transform and Its Efficient Architecture Design." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/89964529057777637917.
Full textAbstract:
博士國立臺灣大學
電機工程學研究所
87
In this thesis, we propose an efficient architecture for the two-Dimensional Forward and Inverse Discrete Wavelet Transform (2-D DWT and IDWT). The proposed 2-D DWT architecture includes a transform module, a RAM module, and a multiplexer. In the transform module, we employ the polyphase decomposition technique and the coefficient folding technique to the decimation filters of stages 1 and 2, respectively. The RAM size is N/2 * N/2. The design scheme of the proposed 2-D IDWT architecture is employing the reverse manner. In comparison with other 2-D DWT and IDWT architectures, the advantages of the proposed architecture are the 100% hardware utilization, fast computing time, regular data flow, and low control complexity, making this architecture suitable for next generation image coding/decoding systems. In addition, we also apply wavelet coding to image compression, including 2-D wavelet image coding and 3-D wavelet video coding. From the simulation results, we find that wavelet coding is one of the most potential coding schemes for the high quality visual communications and the broadband integrated services digital network (BISDN) environment in the future. After that, by use of the block shifting technique, we propose a new method for reduction of blocking effects in very low bit-rate coding. The experiment results also demonstrate the feasibility of our proposed method. Finally, to minimize the requirement of delay elements, we investigate the best permutation strategy for temporal, vertical, and horizontal filtering in 3-D wavelet video coding.
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蘇國安. "Novel Recursive Discrete Fourier Transform with Compact Architecture." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/43716922900545517750.
Full textAbstract:
碩士國立中興大學
電機工程學系
92
In this paper, we propose the novel recursive method to compute discrete Fourier transforms (DFT). The advantages of proposed recursive structure are the reduction of the loop numbers and the signal to quantization noise ratio (SQNR) is greater than the well-known Goertzel’s method which requires the numbers of N2 multiplications and the numbers 2N2 additions. The Goertzel’s method is more efficient than the direct method, but the amounts of computations are still proportional to N2. The others algorithms of the recursive DFT, such as DFR-DFT and FFR-DFT, require 2N2 and N2 loop numbers to evaluate the all DFT outputs X[k]. For simplicity, the compact recursive DFT applied the grouped frequency indices to accelerate the computation of the DFT transformation. So we need less loop numbers than the others DFT transform, shown as Table I. The proposed recursive DFT transforms first separate the transform base into the two parts of the DCT and DST. During the computations of the DCT and DST, we require the amounts of the N transform bases. By the property of the period, we find the transform base to be repeated for the evaluating all DCT and DST. So we categorize the outputs of the DCT and DST into the same group which are required the same transform base. By using the shared coefficients, we can achieve to reduce the computation of the DCT and DST. We use the mathematical conceptions of the number theorem in order to group the transform outputs of the DCT and DST. By evaluating the factors of the input length N, we can first obtain the base set, shown as ={0,1,2,..., },then we can obtain the kernel number by the definition . Therefore we can achieve the grouped frequency indices in order to group the transform of the DCT and DST. Finally, the outputs of the DFT transform can be achieved by the combinations of the outputs of the DCT and DST. By sharing the loop coefficients and output coefficients, we can implement the recursive DFT with hardware sharing architectures.
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朱延陵. "Architecture and Chip Design for Discrete Wavelet Transform." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/16405372678935168422.
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Chiu, Chun-Hao, and 邱浚豪. "Architecture Design for Image Segmentation Discrete Wavelet Transform." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/78925454969911297923.
Full textAbstract:
碩士南台科技大學
電子工程系
94
In the last decade, discrete wavelet transform (DWT) has proven to be a useful technique for a wide rage of application including signals analysis, signal compression, pattern recognition, biomedicine, and numerical analysis. Since DWT has excellent features of energy compaction and inherent scalability, it has been applied extensively in the field of image and video compression. The traditional DWT needs extensive computation complexity. In 1996, Lifting-Based Discrete Wavelet Transform (LDWT), is proposed. With some advantages, such as lower implementation complexity and easy VLSI implementation, LDWT has received considerable attention recently and been adopted in some image compression standards. The memory will be increased, when we process large images in DWT. In order to reduce the required memory, a new method will be discussed in this paper. Before image doing DWT process, we have to cut the image into n blocks. Then we accord the block’s sequence to do DWT. Because the new image size after cutting is only 1/N of the original. Therefore our necessary memory of DWT is reduced. On the side, an architecture will purposed to process the boundary effect problem in this paper.
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Chang, Sin-Hau, and 張信豪. "Low Area Cost VLSI Architecture for Fresnel Transform." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/38803596036245077675.
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Xu, Jing-Jun, and 許靖浚. "Theory and architecture of super discrete fourier transform." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/00958992818587341476.
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LIN, CHING-CHUNG, and 林正中. "An Efficient VLSI Architecture of 2DDiscrete Wavelet Transform." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/56265587604933485422.
Full textAbstract:
碩士中華科技大學
電子工程研究所在職專班
100
The discrete wavelet transform (DWT) attaches great importance on signal analysis and data compression. The signal is divided into low-frequency and high-frequency subbands after the wavelet transform. It achieves signal processing goals in accordance with the different properties of each subband. When DWT is applied to real-time multimedia processing, the speed benefit of hardware implementation must be considered. Traditionally, DWT architecture was convolution-based and needs extra large computations. In 1996, lifting-based DWT was proposed by Sweldens. This scheme has the advantages of high-computation and memory savings. This makes it an important research issue. In recent years, there are many one-dimensional and two-dimensional DWT hardware architecture based on this proposed scheme. It also needs external memory to store temporary results for two-dimension processing. In this thesis, an efficient architecture for the implementation of two-dimension, lifting-based DWT has been proposed .The folded and the pipelined schemes were also applied. They support greater hardware utilization and sped up clock rates. The reuse of internal registers is applied for the removal of external memory. The proposed architecture was coded using Verilog-HDL initially, simulated by Modelsim, and verified by Matlab. Finally, it was implemented in an FPGA for an outcome in DWT VLSI architecture for real-time processing applications. Keywords: discrete wavelet transform, lifting
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Hsieh, Yen-Long, and 謝顏隆. "Architecture Design of H.264 Discrete Cosine Transform." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/74024470056539167481.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
97
This thesis proposes a Discrete Cosine Transform architecture with high throughput and low area. This architecture can be applied in H.264 High Definition (HD) resolution video products. In H.264, the block sizes of the Discrete Cosine Transform are 4×4 and 8×8. The 8×8 block size transform is mainly used in Standard Definition resolution, High Definition resolution, and above Definition resolution. This thesis implements an 8×8 transform architecture. For application in HD resolution video products, the proposed architecture supplies enough high throughput, but a big area should also be associated with a high throughput. Through some property of the DCT, this thesis shows that the area can be reduced and then a high throughput and small area architecture can be implemented. In the proposed architecture, the specification of proposed architecture is 1080p and 60 frames per second. The proposed architecture is synthesized with TSMC 0.18 μm technology cell library and the operating speed is 81 MHz. In this operation speed, the proposed architecture has smaller area when compared with other architectures which also implement H.264 8×8 DCT architecture recently.
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Xiao, Ru Xuan, and 蕭如宣. "CORDIC-based architecture design for discrete transforms in DSP." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/41546174074294992765.
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Yen, Chung Yi, and 顏仲毅. "A Unified Low-Power Architecture for Various Orthogonal Transforms." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/37434905949064411484.
Full textAbstract:
碩士國立中山大學
資訊工程研究所
84
We compare and improve many word-level Discrete Fourier Transform (DFT) architectures in order to save area and power while still maintain reasonable speed performance. A new arbitrary 2n-point constant-geometry Fast Fourier Transform (FFT) architecture is proposed which requires at most only one complex multiplier, four complex add/subtract elements, buffers and a control unit. Furthermore, other popular transforms, such as Walsh-Hadamard Transform (WHT), Complex Hadamard Transform (CHT), Discrete Cosine Transform (DCT), Discrete Sine Transform (DST), Fast Hartley Transform (FHT) and their inverse transforms can also be realized on the above constant-geometry architecture by adding suitable pre-processing and post- processing units. The final goal is to design a unified low- hardware cost, low-power architecture which provides fast computation of various transforms. A proto- type was implemented by Field-Programmable Gates Array (FPGA) to obtain a rough area, speed and power estimation at architecture level.
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Tsai, Hsing-Juan, and 蔡幸娟. "A Parameterizable Architecture for Two-Dimensional Discrete Cosine Transform and Inverse Discrete Cosine Transform." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/66341916946119230484.
Full textAbstract:
碩士逢甲大學
資訊工程所
93
The Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transforms (IDCT) are widely used in various audio and image processing applications. Because of the computation complexity of these algorithms, the dedicated hardware is usually required to achieve the performance of real-time applications. This thesis presents an efficient implementation of a two-dimensional DCT/IDCT processor using a serial-parallel systolic array architecture. The data transfer between processing elements is propagated serially in order to reduce the data communication cost. The data within the processing element is computed in a parallel manner to make the architecture high-speed. By carefully collocating the propagate data in the register of processing element, the transposition operation can be eliminated in this architecture. The block size of 2-D DCT/IDCT and the bit-width of computation data are extracted as parameters that can easily and systematically be adapted to conform to the various imaging coding standard. The behavior and structure model in C language is used to verify the correctness of the 2-D DCT/IDCT computation and the parameterizable implementation. The precision analysis of the 2-D DCT/IDCT implementation was performed by MatLab. The DCT design cost about 14K gate counts when block size is 8 and bit width is 6. The numbers of gate count increase 4 times when block size increases 2 times and those increase about 1.5 times when bit width increases 2 times.
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Zheng, Shun Fa, and 鄭順發. "Efficient VLSI architecture realization for fast discrete wavelet transform." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/03691633655797860622.
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Chan, Sung-Yu, and 詹松諭. "Design of Reconfigurable Architecture of Fast Fourier Transform Algorithm." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/65384517192528038477.
Full textAbstract:
碩士元智大學
資訊工程學系
94
Fast Fourier transform is an important to implement a digital signal processing system. In the operation of FFT, it need to do complicated calculation. In each two-point butterfly computation, it need to read the correct data and twiddle factor from the memory address, then do the computation of multiplication and addition, and store the result in the memory, and provide the data for the next stage butterfly computation. For a fix length sequence butterfly computation, the address sequence of data and twiddle factor, depend on the data''s number and Different processing stages. So we provide an address generator using the arithmetic logic unit to simplify the computation of the memory address. It can also support various length N-Point FFT, and configure the address generator for the N-Point FFT. Because of the hardware complexity of the butterfly computation, we use the shift-add device to simply hardware implement, and share between multipliers. We can change the data sequences to decrease the numbers of the multipliers and ahift-add device and reduce the hardware complexity. In implementation, we use Xilinx ISE Foundation to build this structure with Verilog syntax, and to simulate the function with Modelsim. We implement N-Point FFT on Xilinx VirtexII-XC2V1000 FPGA, and verify the design of reconfigurable architecture with fast Fourier transform algorithm.
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Lin, Tzu-yang, and 林子揚. "Ｂit-width Tradeoffs in Hardware Discrete Wavelet Transform Architecture." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/79629371605516007911.
Full textAbstract:
碩士國立中正大學
電機工程所
94
Abstract Discrete Wavelet Transform is an efficient signal analysis technique. The newly announced image compressing technique JPEG2000 is adopting DWT as the core technology. DWT is performed by convoluting the image with designed filter banks in order decompose the digital signals into the signals in the subbands. The hardware implementation for DWT has progressed in recent year. An important progress in DWT architecture is called Lifting-based DWT. This architecture has the same performance with only half the area of the original DWT architecture. At 2002, C. Huang, P. Tseng, and L. Chen proposed a “Flipping” structure for the Lifting-based DWT, in which the multiplication positions were changed to reduce the number of registers. With this structure, the same performance can be reached with even less area. The aim is comparison of the Peaks Signal of Noise Ratio under the difference between the Bit-width of the Flipping structure and the Lifting-based structure. Implementing Flipping structure and Lifting-based structure is the way to compare the difference in the different floating bits. The PSNR of the Flipping in our experiment is 60.64dB under the 7 bits of the floating. The PSNR of the Lifting-based structure is 62.27dB under the 7 bits of the floating. The optimum floating Bit-width of the Flipping structure’s PSNR is 7 Bits. The PSNR of the Lifting-based structure’s PSNR is better with the longer Bit-width. The outcome of PSNR is enough for us under the 7 Bits of two kind’s DWT structures. Under the 7 floating Bits, the total Bit-width of Flipping structure is shorter than them of the Lifting-based structure and lack 1.6dB in the PSNR. The outcome of the Flipping structure is better than the Lifting-based structure.
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Lee, Yung-Pin, and 李永斌. "Architecture Design for Video Deccoder and Discrete Cosine Transform." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/67437645166483116122.
Full textAbstract:
博士國立臺灣大學
電機工程學系
85
In this dissertation, both architectures for a 2-D DCT/IDCT using direct approach and an MPEG-2 MP@ML video decoder are proposed. Firstly, a novel 8x8 2-D DCT/IDCT architecture based on the direct 2-Dapproach and the rotation technique is developed. The computational complexity is reduced by taking advantage of the special attribute of complex number. Both the parallel and the folded architectures is proposed. Unlike other approach, the proposed architecture is regular, and economically-allowable for VLSI implementation. Compared to the row-column method, less internal wordlength is needed in order to meet the error requirement of IDCT, and the throughput of the proposed architecture can achieve two times that of the row- column method with 30% hardware increased.The folded 8x8 IDCT architecture is also implemented as a VLSI chip. Secondly, in the MPEG-2 video decoder, the bitstream isfirst surveyed, and, accroding to the bitstream, a suitable variable length decoder (VLD) for such application is designed. Based on the proposedarchitecture for the MPEG-2 decoder, the off-chip memory configuration and the decoding process are analyzed, and the decoding process, which includes VLD,inverse scan, inverse quantization, inverse DCT, and motion compensation, is implemented by VLSI with 27 MHz to satisfy the requirement of the MP@ML.
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Cheng, Chia-Hsien, and 鄭嘉賢. "Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/83775688571244778033.
Full textAbstract:
碩士南台科技大學
電子工程系
90
In the last decade, discrete wavelet transform (DWT) has proven to be a useful technique for a wide range of applications including signal analysis, signal compression, pattern recognition, biomedicine, and numerical analysis. Since DWT has excellent features of energy compaction and inherent scalability, it has been applied extensively in the field of image and video compression. In 1996, lifting-based discrete wavelet transform (LDWT) is proposed. With some advantages, such as lower implementation complexity and easy VLSI implementation, LDWT has received considerable attention recently. In this paper, we propose an efficient VLSI architecture for 1-D LDWT, and its FPGA implementation. The architecture folds the computations of all resolution levels into the same low-pass and high-pass units to achieve higher hardware utilization. Because of its modular, regular and flexible structure, the design is scalable for different resolution levels. The number of registers in the folded architecture is minimized by using time scheduling and register allocation. Since the architecture has the similar topology of a scan chain, we can modify it easily to become a testable scan path design by adding very few hardware resources. In the first part, we present two different 1-D multi-level LDWT architectures by using 5/3 and 9/7 filters, respectively. Those architectures are suitable for 1-D DWT processing, such as speech compression. In the second part, we present a low-cost and high-utilization folded architecture for 2-D 3-level LDWT. The architecture can be used in 2-D digital image processing, such as JPEG2000 image compression standard. All proposed VLSI architectures are realized with verilog HDL, synthesized by the synopsys Design Compiler. Finally, the layouts for those designs are generated with the Avant! Apollo Tools in a 0.35um 1P4M CMOS technology.
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Syue, Cheng-Yuan, and 薛承元. "A Low-Cost 2-D Multi-standard Transform Architecture." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/09077983202304757040.
Full textAbstract:
碩士國立清華大學
電機工程學系
101
In this thesis, a row share strategy, that combined factor share and distributed arithmetic are proposed to build low-cost DCT (Discrete Cosine Transform) and IDCT (Inverse Discrete Cosine Transform) transforms. The proposed architecture can support multi-standard transform, such as MPEG-4, H.264, and VC-1 including 8 x 8、8 x 4、4 x 8 and 4 x 4 transforms. Besides, based on the similarities of DCT and IDCT transforms, we reuse the same circuits to manipulate DCT and IDCT by interlaced sorting methods. Not only the cost of area is saved, but 1D DCT(IDCT) and 2D DCT(IDCT) are also operated continuously to reach the high throughput rate and meet the demands of real-time system. A new parallel structure core circuit is proposed to have the advantages of high-throughput rate and low-cost area compared with previous works. The proposed core requires 68 cycles in latency for 128 data consisted of 2 8x8 blocks. The proposed design uses a TSMC 0.18-um 1P6M CMOS process to implement this chip. In simulation, the operating frequency is 125MHz in slow model and achieves 500MHz throughput rate with 39.5K gate counts. The proposed core can support HDTV(1920 x 1080P@60Hz) in real-time video encoder.