Journal articles: 'Threshold circuits'

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Uchizawa, Kei, Rodney Douglas, and Wolfgang Maass. "On the Computational Power of Threshold Circuits with Sparse Activity." Neural Computation 18, no. 12 (December 2006): 2994–3008. http://dx.doi.org/10.1162/neco.2006.18.12.2994.

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Circuits composed of threshold gates (McCulloch-Pitts neurons, or perceptrons) are simplified models of neural circuits with the advantage that they are theoretically more tractable than their biological counterparts. However, when such threshold circuits are designed to perform a specific computational task, they usually differ in one important respect from computations in the brain: they require very high activity. On average every second threshold gate fires (sets a 1 as output) during a computation. By contrast, the activity of neurons in the brain is much sparser, with only about 1% of neurons firing. This mismatch between threshold and neuronal circuits is due to the particular complexity measures (circuit size and circuit depth) that have been minimized in previous threshold circuit constructions. In this letter, we investigate a new complexity measure for threshold circuits, energy complexity, whose minimization yields computations with sparse activity. We prove that all computations by threshold circuits of polynomial size with entropy O(log n) can be restructured so that their energy complexity is reduced to a level near the entropy of circuit states. This entropy of circuit states is a novel circuit complexity measure, which is of interest not only in the context of threshold circuits but for circuit complexity in general. As an example of how this measure can be applied, we show that any polynomial size threshold circuit with entropy O(log n) can be simulated by a polynomial size threshold circuit of depth 3. Our results demonstrate that the structure of circuits that result from a minimization of their energy complexity is quite different from the structure that results from a minimization of previously considered complexity measures, and potentially closer to the structure of neural circuits in the nervous system. In particular, different pathways are activated in these circuits for different classes of inputs. This letter shows that such circuits with sparse activity have a surprisingly large computational power.

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Goldmann, Mikael, and Marek Karpinski. "Simulating Threshold Circuits by Majority Circuits." SIAM Journal on Computing 27, no. 1 (February 1998): 230–46. http://dx.doi.org/10.1137/s0097539794274519.

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LAPPAS, G., R. J. FRANK, and A. A. ALBRECHT. "A COMPUTATIONAL STUDY ON CIRCUIT SIZE VERSUS CIRCUIT DEPTH." International Journal on Artificial Intelligence Tools 15, no. 02 (April 2006): 143–61. http://dx.doi.org/10.1142/s0218213006002606.

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We investigate the circuit complexity of classification problems in a machine learning setting, i.e. we attempt to find some rule that allows us to calculate a priori the number of threshold gates that is sufficient to achieve a small error rate after training a circuit on sample data [Formula: see text]. The particular threshold gates are computed by a combination of the classical perceptron algorithm with a specific type of stochastic local search. The circuit complexity is analysed for depth-two and depth-four threshold circuits, where we introduce a novel approach to compute depth-four circuits. For the problems from the UCI Machine Learning Repository we selected and investigated, we obtain approximately the same size of depth-two and depth-four circuits for the best classification rates on test samples, where the rates differ only marginally for the two types of circuits. Based on classical results from threshold circuit theory and our experimental observations on problems that are not linearly separable, we suggest an upper bound of [Formula: see text] threshold gates as sufficient for a small error rate, where [Formula: see text].

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Hansen, Kristoffer Arnsfelt, and Vladimir V. Podolskii. "Polynomial threshold functions and Boolean threshold circuits." Information and Computation 240 (February 2015): 56–73. http://dx.doi.org/10.1016/j.ic.2014.09.008.

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Mahajan, Meena. "Depth-2 Threshold Circuits." Resonance 24, no. 3 (March 2019): 371–80. http://dx.doi.org/10.1007/s12045-019-0786-4.

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WANG, YU, HUAZHONG YANG, and HUI WANG. "SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION." Journal of Circuits, Systems and Computers 15, no. 02 (April 2006): 197–216. http://dx.doi.org/10.1142/s021812660600299x.

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Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

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Thakral, Bindu, Arti Vaish, and Rama Koteswara Rao Alla. "Design of Squarer Circuit in Sub-threshold Mode." International Journal of Engineering & Technology 7, no. 2.11 (April 3, 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.11.11004.

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Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator.

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SUZUKI, AKIRA, KEI UCHIZAWA, and XIAO ZHOU. "ENERGY-EFFICIENT THRESHOLD CIRCUITS COMPUTING MOD FUNCTIONS." International Journal of Foundations of Computer Science 24, no. 01 (January 2013): 15–29. http://dx.doi.org/10.1142/s0129054113400029.

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We prove that the modulus function MODm of n variables can be computed by a threshold circuit C of energy e and size s = O(e(n/m)1/(e − 1)) for any integer e ≥ 2, where the energy e is defined to be the maximum number of gates outputting "1" over all inputs to C, and the size s to be the number of gates in C. Our upper bound on the size s almost matches the known lower bound s = Ω(e(n/m)1/e). We also consider an extreme case where threshold circuits have energy 1, and prove that such circuits need at least 2(n − m)/2 gates to compute MODm of n variables.

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Ghavami, Behnam. "Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no. 3 (May 8, 2018): 1189–203. http://dx.doi.org/10.1108/compel-03-2016-0118.

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Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

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Heo, Jae, Kyung-Tae Kim, Seok-Gyu Ban, Yoon-Jeong Kim, Daesik Kim, Taehoon Kim, Yongtaek Hong, In-Soo Kim, and Sung Park. "Stable Logic Operation of Fiber-Based Single-Walled Carbon Nanotube Transistor Circuits Toward Thread-Like CMOS Circuitry." Materials 11, no. 10 (October 1, 2018): 1878. http://dx.doi.org/10.3390/ma11101878.

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A fiber-based single-walled carbon nanotube (SWCNT) thin-film-transistor (TFT) has been proposed. We designed complementary SWCNT TFT circuit based on SPICE simulations, with device parameters extracted from the fabricated fiber-based SWCNT TFTs, such as threshold voltage, contact resistance, and off-/gate-leakage current. We fabricated the SWCNTs CMOS inverter circuits using the selective passivation and n-doping processes on a fiber substrate. By comparing the simulation and experimental results, we could enhance the circuit’s performance by tuning the threshold voltage between p-type and n-type TFTs, reducing the source/drain contact resistance and off current level, and maintaining a low output capacitance of the TFTs. Importantly, it was found that the voltage gain, output swing range, and frequency response of the fiber-based inverter circuits can be dramatically improved.

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11

Jukna, Stasys. "Computing threshold functions by depth-3 threshold circuits with smaller thresholds of their gates." Information Processing Letters 56, no. 3 (November 1995): 147–50. http://dx.doi.org/10.1016/0020-0190(95)00137-2.

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Merrill, William, Ashish Sabharwal, and Noah A. Smith. "Saturated Transformers are Constant-Depth Threshold Circuits." Transactions of the Association for Computational Linguistics 10 (2022): 843–56. http://dx.doi.org/10.1162/tacl_a_00493.

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Abstract Transformers have become a standard neural network architecture for many NLP problems, motivating theoretical analysis of their power in terms of formal languages. Recent work has shown that transformers with hard attention are quite limited in power (Hahn, 2020), as they can be simulated by constant-depth AND/OR circuits (Hao et al., 2022). However, hard attention is a strong assumption, which may complicate the relevance of these results in practice. In this work, we analyze the circuit complexity of transformers with saturated attention: a generalization of hard attention that more closely captures the attention patterns learnable in practical transformers. We first show that saturated transformers transcend the known limitations of hard-attention transformers. We then prove saturated transformers with floating-point values can be simulated by constant-depth threshold circuits, giving the class TC0 as an upper bound on the formal languages they recognize.

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13

Kumar, Pawan, Anshul Avasthi, Shreyans Jain, Tanu Singla, and P. Parmananda. "Resonance Induced Rhythmogenesis in Chua’s Circuits Using Conjugate Variables." International Journal of Bifurcation and Chaos 26, no. 13 (December 15, 2016): 1650214. http://dx.doi.org/10.1142/s021812741650214x.

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Interactions involving conjugate coupling and feedback have been known to induce rhythmogenesis in Chua’s circuits exhibiting fixed point behavior [Singla et al., 2011; Mandal et al., 2013]. It was reported, in these works, that beyond a threshold value of coupling/feedback strength, interaction term involving difference of conjugate variables can induce oscillations in Chua’s circuit. Furthermore, it has been observed that the parametric thresholds, in nonlinear oscillators, can be regulated by suitable forcing techniques [Parmananda et al., 2001; Mahara et al., 2005]. In the present work, a conjunction of these two ideas has been entertained i.e. we study the rhythmogenesis in Chua’s circuit when the conjugate coupling/feedback terms are modulated sinusoidally. It was noted that, when the forcing frequency lies in the vicinity of the natural frequency of Chua’s circuit, maximum lowering of the threshold coupling/feedback constant occurred. Appearance of Arnold’s tongue was also observed as a result of these perturbations. Numerical results have been complimented with the experimental observations.

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14

Ni, Haiyan, Jianping Hu, Xuqiang Zhang, and Haotian Zhu. "The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs." Journal of Circuits, Systems and Computers 29, no. 07 (September 23, 2019): 2050114. http://dx.doi.org/10.1142/s0218126620501145.

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In this paper, a method of optimizing dual-threshold independent-gate FinFET devices is discussed, and the optimal circuit design is carried out by using these optimized devices. Dual-threshold independent-gate FinFETs include low threshold devices and high threshold devices. The low threshold device is equivalent to two merging parallel short-gate devices and high threshold device is equivalent to two merging series SG devices. We optimize the device mainly by selecting the appropriate gate work function, gate oxide thickness, silicon body thickness and so on. Our optimization is based on the Berkeley BSIMIMG model and verified by TCAD tool. Based on these optimized devices, we designed the compact basic logic gates and two new compact D-type flip-flops. Additionally, we developed a circuit synthesis method based on Binary Decision Diagram (BDD) and the optimized compact basic logic gates. Hspice simulations show that the circuits using the proposed dual-threshold IG FinFETs have better performance than the circuits directly using the short-gate devices.

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15

Jeřábek, Emil. "Root finding with threshold circuits." Theoretical Computer Science 462 (November 2012): 59–69. http://dx.doi.org/10.1016/j.tcs.2012.09.001.

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Hajnal, András, Wolfgang Maass, Pavel Pudlák, Márió Szegedy, and György Turán. "Threshold circuits of bounded depth." Journal of Computer and System Sciences 46, no. 2 (April 1993): 129–54. http://dx.doi.org/10.1016/0022-0000(93)90001-d.

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17

Kalinowski, Thomas. "Optimization of Multi-Threshold Circuits." Electronic Notes in Discrete Mathematics 27 (October 2006): 53–54. http://dx.doi.org/10.1016/j.endm.2006.08.052.

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Cao, Ruiping, and Jianping Hu. "Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits." Journal of Electrical and Computer Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/836019.

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In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

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Wada, Kazuyuki, Shinsuke Hara, Satoru Tanoi, Akifumi Kasamatsu, Yuta Otsuka, Kawori Sekine, Atsushi Uchida, and Makoto Naruse. "Ultrafast silicon threshold circuitry for chaotic laser time series." AIP Advances 12, no. 12 (December 1, 2022): 125225. http://dx.doi.org/10.1063/5.0127470.

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Photonic computing has been intensively studied to explore the ultrahigh bandwidth of lightwaves. However, electronic support is indispensable for the post-processing and control of photonic systems owing to the difficulties encountered in all-optical processing. Herein, we demonstrate an ultrafast silicon circuitry capable of conducting thresholding operations on incoming chaotically oscillating high-bandwidth signals. Such circuits are critical elements in ultrafast random-number generators and photonic reinforcement learning that exploit chaotically oscillating time series. The circuit design, including active inductors for bandwidth expansion, and proof-of-principle fabricated device operations are demonstrated using a 180 nm silicon complementary metal–oxide–semiconductor technology node.

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JIAO, HAILONG, and VOLKAN KURSUN. "NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 125–45. http://dx.doi.org/10.1142/s0218126611007116.

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Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.

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Zhang, Chao Jie, and Guang Hui Chang. "Analog Circuits Test by Using Principal Component Analysis." Applied Mechanics and Materials 278-280 (January 2013): 709–13. http://dx.doi.org/10.4028/www.scientific.net/amm.278-280.709.

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In view of the difficulties caused by determining threshold for analog circuits test, a method based on principal component analysis (PCA) of node voltages was proposed to overcome these difficulties. At first, the principal component model of fault-free circuits was constructed. Then the circuits-under-test was compared with the principal component model to calculate the statistic for fault detection. The proposed method was used to test the output signal amplifying circuit, which is used in the ultrasonic liquid sensor. The testing results show that the PCA based method has a higher sensitivity than other test methods. And the proposed method can overcome the difficulties in determining threshold by the expert’s empirical knowledge. These make it a suitable candidate for analog circuits test.

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G S, Nisarga, Dr Punith Kumar M B, Dr Mahesh, and M. Subramanyam. "Comparative Research of Neuron Circuits." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (July 31, 2022): 4121–26. http://dx.doi.org/10.22214/ijraset.2022.45944.

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Abstract: Spiking neurons can be implemented in hardware, for example, to model large neural systems, simulate real-time behaviour, and interface bi-directionally between brains and machines. Circuit solutions used to implement silicon neuron circuits depend on the application requirements. Various neuron circuits are presented in this thesis, including spike-event generators (Axon Hillock neuron circuits), above-threshold neuron circuits (Quadratic Integrate and Fire neuron circuits), and differential pair integrator circuits. Cadence's tool simulates these circuits using 180nm technology. Comparing these circuits is based on their working properties and simulation results, and their features are demonstrated with experiments.

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He, Guo, Chao Jie Zhang, Guang Hui Chang, and Shu Hai Liang. "Testing Analog Circuits by PCA of Power Supply Current." Applied Mechanics and Materials 157-158 (February 2012): 641–45. http://dx.doi.org/10.4028/www.scientific.net/amm.157-158.641.

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A method using principal component analysis (PCA) of dynamic power supply current was proposed for testing of analog circuits in this paper. The basic model of the proposed method and the general rule for analog fault detection were described in detail. At first, the principal component model of fault-free circuits was constructed. Then the circuits-under-test was compared with the principal component model to calculate the statistic for fault detection. The features of power supply current in both time and frequency domain were combined by PCA, and it could overcome the difficulty to determine threshold by empirical knowledge. The proposed method was applied to detect faults of the signal filtering and amplifying circuit, which is used in the ultrasonic liquid-level sensor. The results show that the power supply current contains information about the circuit’s faults, and can be used for fault detection of analog circuits by analyzing this signal.

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Azimi, Mohammad, Mehdi Habibi, and Hamidreza Karimi-Alavijeh. "An organic, threshold voltage based, all PMOS, voltage reference generator for flexible sensor tags." Flexible and Printed Electronics 6, no. 4 (December 1, 2021): 045015. http://dx.doi.org/10.1088/2058-8585/ac43f9.

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Abstract The developments and advances achieved in organic semiconductors have promised lower costs for integrated circuit production and also fabrication of electronic circuits using printed technology on unconventional substrates such as plastic, clothing, and even skin. An important building block essential to most electronic circuits is a voltage, process, and temperature independent potential generator which can be used to bias amplifiers and produce a fixed reference for sensor devices. The generation of a voltage reference is also important for voltage regulators. Currently, most reported organic integrated circuits use only p-type OFETs in their circuits due to simpler fabrication procedures. Furthermore, air stable p-type organic semiconductors such as pentacene and CuPc are well characterized. In this paper, a low power two stage all PMOS voltage reference generator is proposed. Since properties such as threshold voltage value and device aging are dependent on the OFET structure, the type of device chosen for this purpose will have a direct impact on the circuit performance. Three different types of OFETs with silver, copper, and gold drain/source electrodes are studied in this work. Performance factors such as line sensitivity (LS), temperature coefficient (TC), power consumption, time constant, and output drifts of the fabricated integrated circuits are measured and reported to verify the characteristics of the proposed circuits. It is shown that the drain/source metal choice affects the threshold voltage dependent output potential of the reference generators.

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Singh, N. S. S., N. H. Hamid, and V. S. Asirvadam. "Reliability Programmed Tool and its Application for Fault Tolerance Computation." Advanced Materials Research 909 (March 2014): 397–404. http://dx.doi.org/10.4028/www.scientific.net/amr.909.397.

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With the continuous scaling of CMOS technology, reliability of nanobased electronic circuits is endlessly becoming a major concern. Due to this phenomenon, several computational approaches have been developed for the reliability assessment of modern logic integrated circuits. However, these analytical methodologies have a computational complexity that increases exponentially with the circuit dimension, making the whole reliability assessment process of large circuits becoming very time consuming and intractable. Therefore, to speed up the reliability assessment of large circuits, this paper firstly looks into the development of a programmed reliability tool. The Matlab-based tool is developed based on the generalization of Probabilistic Transfer Matrix (PTM) model as one of the existing reliability assessment approaches. Users have to provide description of the desired circuit in the form of Netlist that becomes the input to the programmed tool. For illustration purpose, in this paper, C17 has been used as the benchmark test circuit for its reliability computation. Secondly, reliability of a desired circuit does not only depend on its faulty gates, but it also depends on the maximum error threshold of these faulty gates above which no reliable computation is possible. For this purpose, the developed tool is employed again to find the exact error thresholds for faulty gates.

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Vasudeva Reddy, T., and Dr B.K. Madhavi. "Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 205. http://dx.doi.org/10.14419/ijet.v7i2.12.11280.

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Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay.

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Impagliazzo, Russell, Ramamohan Paturi, and Michael E. Saks. "Size--Depth Tradeoffs for Threshold Circuits." SIAM Journal on Computing 26, no. 3 (June 1997): 693–707. http://dx.doi.org/10.1137/s0097539792282965.

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Kochol, Martin. "Efficient monotone circuits for threshold functions." Information Processing Letters 32, no. 3 (August 1989): 121–22. http://dx.doi.org/10.1016/0020-0190(89)90011-2.

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Uchizawa, Kei, Takao Nishizeki, and Eiji Takimoto. "Energy and depth of threshold circuits." Theoretical Computer Science 411, no. 44-46 (October 2010): 3938–46. http://dx.doi.org/10.1016/j.tcs.2010.08.006.

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Tawfik, Sher, and Volkan Kursun. "Multi-Threshold Voltage FinFET Sequential Circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 1 (January 2011): 151–56. http://dx.doi.org/10.1109/tvlsi.2009.2028028.

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Reif, John H., and Stephen R. Tate. "On Threshold Circuits and Polynomial Computation." SIAM Journal on Computing 21, no. 5 (October 1992): 896–908. http://dx.doi.org/10.1137/0221053.

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P. Carter, Nicholas, and Steve P. Ferrera. "Reconfigurable magnetoelectronic circuits for threshold logic." International Journal of Circuit Theory and Applications 32, no. 5 (September 2004): 363–82. http://dx.doi.org/10.1002/cta.286.

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Paturi, R., and M. E. Saks. "Approximating Threshold Circuits by Rational Functions." Information and Computation 112, no. 2 (August 1994): 257–72. http://dx.doi.org/10.1006/inco.1994.1059.

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Maciel, Alexis, and Denis Thérien. "Threshold Circuits of Small Majority-Depth." Information and Computation 146, no. 1 (October 1998): 55–83. http://dx.doi.org/10.1006/inco.1998.2732.

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Maciel, Alexis, and Denis Thérien. "Efficient Threshold Circuits for Power Series." Information and Computation 152, no. 1 (June 1999): 62–73. http://dx.doi.org/10.1006/inco.1998.2783.

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Gupta, T. K., A. K. Pandey, and O. P. Meena. "Analysis and design of lector-based dual-Vt domino logic with reduced leakage current." Circuit World 43, no. 3 (August 7, 2017): 97–104. http://dx.doi.org/10.1108/cw-03-2017-0013.

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Purpose This paper aims to propose a new lector-based domino and examine it with inputs and clock signal combination in a 45-nm dual-threshold footerless domino circuit for reduced leakage current. Design/methodology/approach In this technique, p-type and n-type leakage control transistors (LCTs) are introduced between pull-up and pull-down networks, and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current, which becomes dominant in nanometre technology. Simulations were based on a 45-nm BISM 4 model using an HSPICE simulator for proposed domino circuits. Findings The result shows that CHIL (clock high and input low) state is ineffective for lowering leakage current and the conventional CHIH (clock high and input high) state is only effective to suppress the leakage at low temperature for wide fan-in domino circuits. At high temperature, CLIL (clock low and input low) state is preferable to reduce the leakage current for low fan-in domino, but for high fan-in domino, CHIH state is preferred. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 50.94 to 75.68 per cent and by 64.85 to 86.57 per cent at low and high die temperatures, respectively, when compared to the standard dual-threshold voltage domino logic circuits. Originality/value The research proposes a new leakage reduction technique used in domino circuits and also evaluates the state for leakage reduction which can be used for low-power dynamic circuits.

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Rastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (November 11, 2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.

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Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

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Kushwaha, Dinesh, and D. K. Mishra. "Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits." Circulation in Computer Science 2, no. 1 (January 24, 2017): 1–4. http://dx.doi.org/10.22632/ccs-2016-251-36.

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This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration

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KUMAR, RANJITH, and VOLKAN KURSUN. "TEMPERATURE-ADAPTIVE ENERGY REDUCTION TECHNIQUES FOR NANO-CMOS CIRCUITS DISPLAYING REVERSED TEMPERATURE DEPENDENCE." Journal of Circuits, Systems and Computers 17, no. 03 (June 2008): 423–38. http://dx.doi.org/10.1142/s0218126608004393.

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Temperature dependent propagation delay characteristics of CMOS circuits will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 32nm CMOS technology is enhanced when the temperature is increased at the nominal supply and threshold voltages. The enhancement of circuit speed provides new opportunities to lower the energy consumed by active circuits at elevated temperatures. Temperature-adaptive supply and threshold voltage tuning techniques are proposed in this paper to reduce the high temperature energy consumption without degrading the clock frequency in the active mode. Results indicate that the energy consumption can be lowered by up to 21% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body-bias exponentially reduces the leakage currents as well as the parasitic junction capacitances of the MOSFETs. The temperature-adaptive threshold voltage tuning through reverse body-bias yields an active mode energy reduction by up to 29.8% as compared to the standard zero-body-biased circuits at high temperatures.

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Ni, Hai Yan, and Jian Ping Hu. "Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes." Key Engineering Materials 460-461 (January 2011): 837–42. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.837.

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This paper presents adiabatic flip-flops operating on near-threshold supply voltages. The near-threshold adiabatic flip-flops and sequential circuits are realized with improved CAL (Clocked Adiabatic Logic) circuits using a single-phase power clock. An auxiliary clock generator is used to obtain the non-overlap sinusoidal auxiliary signal pair. A near-threshold mode-10 counter is implemented. All circuits are simulated using Predictive Technology Model (PTM) 45nm process. The near-threshold adiabatic circuits attain large energy savings over a wide range of frequencies, as compared with conventional static CMOS logic circuits.

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YUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (March 2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.

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Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 output during its precharge phase without affecting circuits operation in its evaluation and standby phase. The required process for dual threshold voltage circuit configuration involves only one additional ion implant step to provide an extra threshold voltage. SPICE simulation for our proposed circuits is made using a 0.18 μm CMOS processes from TSMC, with 10 fF capacitive loads in all output nodes, and parameters for typical process corner at 25°C. Layout is designed, wafer is fabricate and measured. The measurement results of fabricated chips are listed and verify that our designed 8-bit carry look-ahead adders (CLAs) reduced power consumption and propagation delay time by more than 15% and around 20%, respectively, when compared with the prior work.

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Li, Shuo, Nan Pan, Sen Gao, and Lei Li. "Three State Output Module and Digital Switch Circuit Based on Threshold Memristor." Journal of Physics: Conference Series 2395, no. 1 (December 1, 2022): 012021. http://dx.doi.org/10.1088/1742-6596/2395/1/012021.

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Abstract A memristor is a new electronic device with small volumes and small fluctuations. As a two-terminal device, it is mainly characterized by non-volatility and nanoscale characteristic size. Memristors can also calculate and store at the same time, which has a broad application prospect in logic circuits. Traditional integrated circuit technology has been very mature. And CMOS technology has almost reached the limit of physical size. Compared with traditional circuit components, memristor devices are compatible with CMOS circuits with their fast computing speed, low power consumption, and small layout area. A three-state output module based on a threshold memristor is proposed. The structure includes an inverter, a PMOS tube, two NMOS tubes, and two threshold memristors. Compared with the traditional three-state gate which only uses CMOS technology, the circuit area required by the module is smaller and the overall power consumption is lower, which caters to the development trend of portable and low-power electronic devices. Then the digital switch circuit using this module is introduced, which provides a new idea for the data transmission circuit. The circuit and module are simulated and verified by LTspice software.

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N, Vengadeswari, and Priscilla Whitin. "Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 27. http://dx.doi.org/10.14419/ijet.v7i3.1.16790.

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In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools.

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Srinivas, M., and K. V. Daya Sagar. "Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)." Journal of Physics: Conference Series 2089, no. 1 (November 1, 2021): 012080. http://dx.doi.org/10.1088/1742-6596/2089/1/012080.

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Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

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Xu, Xiao Li, and Qiu Shuang Liu. "Signal Conditioning Circuit Design Method Based on Case-Based Reasoning." Advanced Materials Research 171-172 (December 2010): 719–22. http://dx.doi.org/10.4028/www.scientific.net/amr.171-172.719.

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In order to improve the R&D speed of instrument and to reduce the R&D cycle, this paper presents a signal conditioning circuit design method based on case-based reasoning (CBR). The case base stores a number of case circuits, and each circuit’s feature information is described by a set containing at least one information entity; the description methods include: according to the user’s description information on the to-be-generated circuit, generate the first information entity set of to-be-generated circuit; take the first information entity set as the search keywords, search from the case base the case circuit of all or partial information entities of the circuit to be generated; according to the degree of correlation between the preset information entity and the case circuit, obtain the degree of correlation between the first information entity set and the searched case circuit; from the said case circuits searched, select the case circuit whose correlation degree is larger than the correlation threshold value as the target circuit; output the target circuit; through accepting the users’ modification of target circuit, obtain the circuit to be generated. Experimental results show: signal conditioning circuit image generation method, which is based on case reasoning, can effectively improve the efficiency of research and development.

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Dokic, B. L. "A Review on Energy Efficient CMOS Digital Logic." Engineering, Technology & Applied Science Research 3, no. 6 (December 18, 2013): 552–61. http://dx.doi.org/10.48084/etasr.389.

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Autonomy of power supply used in portable devices directly depends on energy efficiency of digital logic. This means that digital systems, beside high processing power and very complex functionality, must also have very low power consumption. Power consumption depends on many factors: system architecture, technology, basic cells topology-speed, and accuracy of assigned tasks. In this paper, a review and comparison of CMOS topologies techniques and operating modes is given, as CMOS technology is expected to be the optimum choice in the near future. It is shown that there is a full analogy in the behavior of digital circuits in sub-threshold and strong inversion. Therefore, synthesis of digital circuits is the same for both strong and weak operating modes. Analysis of the influence of the technology, MOS transistor threshold voltage (Vt) and power supply voltage (Vdd) on digital circuit power consumption and speed for both operating modes is given. It is shown that optimal power consumption (minimum power consumption for given speed) depends on optimal choice of threshold, and power supply voltage. Multi Vdd /Vt techniques are analyzed as well. A review and analysis of alternative logical circuit's topologies – pass logic (PL), complementary pass logic (CPL), push-pull pass logic (PPL) and adiabatic logic – is also given. As shown, adiabatic logic is the optimum choice regarding energy efficiency.

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Maralani, A., Michael S. Mazzola, David C. Sheridan, Igor Sankin, and Volodymyr Bondarenko. "Characterization and Modeling of SiC LTJFET for Analog Integrated Circuit Simulation and Design." Materials Science Forum 615-617 (March 2009): 915–18. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.915.

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The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal parameters are reported, (3) gain performance and small signal parameters of the basic analog circuit block, Common Source (CS) amplifier, based on the variation of the load transistors threshold voltage (Vth) are studied and analyzed, and (4) frequency and transient response of the cascoded CS amplifier (CS-Cas) are reported.

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SERNA, MARIA, and FATOS XHAFA. "THE PARALLEL APPROXIMABILITY OF THE FALSE AND TRUE GATES PROBLEMS FOR NOR-CIRCUITS." Parallel Processing Letters 12, no. 01 (March 2002): 127–36. http://dx.doi.org/10.1142/s0129626402000872.

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We study the parallel approximability of computing the number of true gates and false gates for circuits with only NOR gates, we refer to these problems as Nor-False Gates and Nor-True Gates Problems, respectively. We show that the parallel approximability of these problems depends on restrictions on the topology of the circuit. More precisely, for circuits with fan-in and fan-out bounded by a constant and having a constant number of output gates both problems exhibit a threshold behavior in their parllel approximability. Bounding only the number of outputs gives threshold results for the Nor-False Gates Problem but non-approximability (for any constant) for the Nor-True Gates Problem. For the case of unbounded number of outputs we show that none of the two problems can be approximated in parallel within any constant. We use the threshold result of False Gates Problem to identify a subclass of linear programming that also presents a threshold behavior in its parallel approximability.

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CARD, HOWARD C., DEAN K. McNEILL, CHRISTIAN R. SCHNEIDER, ROLAND S. SCHNEIDER, and BRION K. DOLENKO. "TOLERANCE OF ON-CHIP LEARNING TO VARIOUS CIRCUIT INACCURACIES." Journal of Circuits, Systems and Computers 08, no. 02 (April 1998): 315–27. http://dx.doi.org/10.1142/s0218126698000146.

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An investigation is made of the tolerance of various in-circuit learning algorithms to component imprecision and other circuit limitations in artificial neural networks. In contrast with most previous work, the various circuit limitations are treated separately for their effects on learning. Supervised learning mechanisms including backpropagation and contrastive Hebbian learning, and unsupervised soft competitive learning were found to be sufficiently tolerant of those levels of arithmetic inaccuracy, noise, nonlinearity, weight decay, and statistical variation from fabrication that we have experienced in 1.2 μm analog CMOS circuits employing Gilbert multipliers as the primary computational element. These learning circuits also function properly in the presence of offset errors in analog multipliers and adders, provided that the computed weight updates are constrained by the circuitry to be made only when they exceed certain minimum or threshold values. These results may also be relevant for other analog circuit approaches and for compact (low bit rate) digital implementations, although in this case, the minimum weight increment defined by the bit precision could necessitate stochastic updating.

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UCHIZAWA, Kei, and Xiao ZHOU. "Energy-Efficient Threshold Circuits for Comparison Functions." Interdisciplinary Information Sciences 18, no. 2 (2012): 161–66. http://dx.doi.org/10.4036/iis.2012.161.

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Journal articles on the topic 'Threshold circuits'

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