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LEPORATI, ALBERTO OTTAVIO. "Threshold Circuits and Quantum Gates." Doctoral thesis, Università degli Studi di Milano, 2003. http://hdl.handle.net/10281/43616.
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Maciel, Alexis. "Threshold circuits of small majority-depth." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=28830.
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We investigate the complexity of computations with constant-depth threshold circuits. Such circuits are composed of gates that determine if the sum of their inputs is greater than a certain threshold. When restricted to polynomial size, these circuits compute exactly the functions in the class TC$ sp0$.These circuits are usually studied by measuring their efficiency in terms of their total depth. Using this point of view, the best division and iterated multiplication circuits have depth three and four, respectively.
In this thesis, we propose a different approach. Since threshold gates are much more powerful than AND-OR gates, we allow the explicit use of AND-OR gates and consider the main measure of complexity to be the majority-depth of the circuit, i.e. the maximum number of threshold gates on any path in the circuit. Using this approach, we obtain division and iterated multiplication circuits of total depth four and five, but of majority-depth two and three.
The technique used is called Chinese remaindering. We present this technique as a general tool for computing functions with integer values and use it to obtain depth-four threshold circuits of majority-depth two for other arithmetic problems such as the logarithm and power series approximation. We also consider the iterated multiplication problem for integers modulo q and for finite fields.
The notion of majority-depth naturally leads to a hierarchy of subclasses of TC$ sp0$. We investigate this hierarchy and show that it is closely related to the usual depth hierarchy.
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PALANISWAMY, ASHOK KUMAR. "SYNTHESIS AND TESTING OF THRESHOLD LOGIC CIRCUITS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/963.
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Threshold logic gates gaining more importance in recent years due to the significant development in the switching devices. This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to represent the given boolean circuit description. A fast method to identify the given Boolean function as a threshold logic function with weight assignment is introduced. It characterizes the threshold logic function based on the modified chows parameters which results in drastic reduction in time and complexity. Experiment results shown that the proposed method is at least 10 times faster for each input and around 20 times faster for 7 and 8 input, when comparing with the algorithmic based methods. Similarly, it is 100 times faster for 8 input, when comparing with asummable method. Existing threshold logic synthesis methods decompose the larger input functions into smaller input functions and perform synthesis for them. This results in increase in the number of threshold logic gates required to represent the given circuit description. The proposed implicit synthesis methods increase the size of the functions that can be handled by the synthesis algorithm, thus the number of threshold logic gates required to implement very large input function decreases. Experiment results shown that the reduction in the TLG count is 24% in the best case and 18% on average. An automatic test pattern generation approach for transition faults on a circuit consisting of current mode threshold logic gates is introduced. The generated pattern for each fault excites the maximum propagation delay at the gate (the fault site). This is a high quality ATPG. Since current mode threshold logic gate circuits are pipelined and the combinational depth at each pipeline stage is practically one. It is experimentally shown that the fault coverage for all benchmark circuits is approximately 97%. It is also shown that the proposed method is time efficient.
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Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.
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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Narendra, Siva G. (Siva Gurusami) 1971. "Effect of MOSFET threshold voltage variation on high-performance circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8341.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 95-101).
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in threshold voltage variation due to worsening short channel effect. This thesis will address three specific circuit design challenges arising from increased threshold voltage variation and present prospective solutions. First, with supply voltage scaling, control of die-to-die threshold voltage variation becomes critical for maintaining high yield. An analytical model will be developed for existing circuit technique that adaptively biases the body terminal of MOSFET devices to control this threshold voltage variation. Based on this model, recommendations on how to effectively use the technique in future technologies will be presented. Second, with threshold voltage scaling, sub-threshold leakage power is expected to be a significant portion of total power in future CMOS systems. Therefore, it becomes imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and a circuit technique to reduce system leakage without reducing system performance will be discussed.
(cont.) Finally, due to different processing steps and short channel effects, threshold voltage of devices of same or different polarities in the same neighborhood may not be matched. This will introduce mismatch in the device drive currents that will not be acceptable in some high performance circuits. In the last part of the thesis, voltage and current biasing schemes that minimize the impact of neighborhood threshold voltage mismatch will be introduced.
by Siva G. Narendra.
Ph.D.
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Silva, Augusto Neutzling. "Syhthesis of thereshold logic based circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.
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Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento ressonante (RTD), autômatos celulares quânticos (QCA) e dispositivos de tunelamento de elétron único (SET). Para o desenvolvimento de um fluxo de projeto de circuitos integrados baseados em lógica threshold, duas etapas são fundamentais: (1) identificar se uma dada função Booleana corresponde a uma função lógica threshold (TLF), isto é, pode ser implementada em um único TLG e computar os pesos desse TLG; (2) se uma função não é identificada como TLF, outro método de síntese lógica deve construir uma rede de TLGs otimizada que implemente a função. Este trabalho propõe métodos para atacar cada um desses dois problemas, e os resultados superam os métodos do estado-da-arte. O método proposto para realizar a identificação de TLFs é o primeiro método heurístico capaz de identificar todas as funções de cinco e seis variáveis, além de identificar mais funções que os demais métodos existentes quando o número de variáveis aumenta. O método de síntese de redes de TLGs é capaz de sintetizar circuitos reduzindo o número de portas TLG utilizadas, bem como a profundidade lógica e o número de interconexões. Essa redução é demonstrada através da síntese dos circuitos de avaliação da MCNC em comparação com os métodos já propostos na literatura. Tais resultados devem impactar diretamente na área e desempenho do circuito.In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
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Ting, Darwin Ta-Yueh. "Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.
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Dhillon, Yuvraj Singh. "Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6935.
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Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables.
A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption.
To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed.
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Parthasarathy, Krupa. "Aging Analysis and Aging-Resistant Design for Low-Power Circuits." University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1415615574.
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Gopalakrishnan, Harish. "Energy Reduction for Asynchronous Circuits in SoC Applications." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1324264498.
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Wienke, James Patrick. "The impact of interface states on sub-threshold leakage and power management in CMOS devices and circuits." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7235.
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Thesis (M.S.) -- University of Maryland, College Park, 2007.Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Gutierrez, Arguedas Mauricio. "Accurate modeling of noise in quantum error correcting circuits." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54443.
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A universal, scalable quantum computer will require the use of quantum error correction in order to achieve fault tolerance. The assessment and comparison of error-correcting strategies is performed by classical simulation. However, due to the prohibitive exponential scaling of general quantum circuits, simulations are restrained to specific subsets of quantum operations. This creates a gap between accuracy and efficiency which is particularly problematic when modeling noise, because most realistic noise models are not efficiently simulable on a classical computer. We have introduced extensions to the Pauli channel, the traditional error channel employed to model noise in simulations of quantum circuits. These expanded error channels are still computationally tractable to simulate, but result in more accurate approximations to realistic error channels at the single qubit level. Using the Steane [[7,1,3]] code, we have also investigated the behavior of these expanded channels at the logical error-corrected level. We have found that it depends strongly on whether the error is incoherent or coherent. In general, the Pauli channel will be an excellent approximation to incoherent channels, but an unsatisfactory one for coherent channels, especially because it severely underestimates the magnitude of the error. Finally, we also studied the honesty and accuracy of the expanded channels at the logical level. Our results suggest that these measures can be employed to generate lower and upper bounds to a quantum code's threshold under the influence of a specific error channel.
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Hossain, Mousam. "Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification." Thesis, North Dakota State University, 2019. https://hdl.handle.net/10365/31574.
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Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive (QDI) asynchronous design paradigm with enormous potential for industrial applications. Design validation is a critical concern before commercialization. Unlike other QDI paradigms, such as NULL Convention Logic (NCL) and Pre-Charge Half Buffers (PCHB), there exists no formal verification methods for SCL. In this thesis, a unified formal verification scheme for combinational as well as sequential SCL circuits is proposed based on equivalence checking, which verifies both safety and liveness. The method is demonstrated using several multipliers, MACs, and ISCAS benchmarks.
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Mozaffari, Mojaveri Seyed Nima. "DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES." OpenSIUC, 2018. https://opensiuc.lib.siu.edu/dissertations/1526.
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The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible.
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Stangherlin, Kleber Hugo. "Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/96974.
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Esta tese avalia os benefícios e desafios associados com a operação em uma ampla faixa de frequências e tensões próximas ao limiar do transistor. A diminuição da tensão de alimentação em circuitos digitais CMOS apresenta grandes vantagens em termos de potência consumida pelo circuito. Esta diminuição da potência é acompanhada por uma redução da performance, reflexo da diminuição na tensão de alimentação. A operação de circuitos digitais no ponto de energia mínima é comumente associada ao regime de operação abaixo do limiar do transistor, trazendo enormes penalidades em performance e variabilidade. Esta dissertação mostra que é possível obter 8X mais eficiência energética com uma ampla faixa dinâmica de tensão e frequência, da tensão nominal até o limite inferior da operação próximo ao limiar do transistor. Como parte deste estudo, uma biblioteca de células digitais CMOS para esta ampla faixa de frequências foi desenvolvida. A biblioteca de células lógicas foi exercitada em um PDK comercial de 65nm para operação próximo ao limiar do transistor, reduzindo os efeitos da variabilidade sem comprometer o projeto em termos de área e energia quando operando em inversão forte. Para operar próximo e abaixo do limiar do transistor as células devem ser desenvolvidas com um número limitado de transistores em série. Nosso estudo mostra que uma performance aceitável em termos de margens de ruído estático é obtida para um conjunto restrito de células, onde são empregados no máximo dois transistores em série. Reportamos resultados para projetos de média complexidade que incluem um filtro notch de 25kgates, um microcontrolador 8051 de 20kgates, e 4 circuitos combinacionais/ sequenciais do conjunto de avaliação ISCAS. Neste trabalho, é estudada a máxima frequência atingida em cada tensão de alimentação, desde 0.15V até 1.2V. O ponto de mínima energia é demonstrado em operação abaixo do limiar do transistor, aproximadamente 0.29V, oque representa um ganho de 2X em eficiência energética comparado ao regime de operação próximo ao limiar do transistor. Embora o pico de eficiência energética ocorra abaixo do limiar do transistor para os circuitos estudados, nós também demonstramos que nesta tensão de alimentação ultra-baixa o atraso e a potência sofrem um impacto substancial devido ao aumento na variabilidade, atigindo uma degradação em performance de 30X, com respeito à operação próxima ao limiar do transistor.This thesis assesses the benefits and drawbacks associated with a very wide range of frequency when operation at near-threshold is considered. Scaling down the supply voltage in digital CMOS circuits presents great benefits in terms of power reduction. Such scaling comes with a performance penalty, hence in digital synchronous circuits the reduction in frequency of operation follows, for a given circuit layout, the VDD reduction. Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This thesis shows that it is possible to achieve 8X higher energy-efficiency with a very-wide range of dynamic voltage-frequency scaling, from nominal voltages down to the lower boundary of near-VT operation. As part of this study, a CMOS digital cell-library for such wide range of frequencies was developed. The cell-library is exercised in a 65nm commercial PDK and targets near-VT operation, mitigating the variability effects without compromising the design in terms of area and energy at strong inversion. For near-VT or sub-VT operation the cells have to be designed with few stacked transistors. Our study shows that acceptable performance in terms of static-noise margins is obtained for a constrained set of cells, for which a maximum of 2-stacked transistors are allowed. In this set we include master-slave registers. We report results for medium complexity designs which include a 25kgates notch filter, a 20kgates 8051 compatible core, and 4-combinational/4-sequential ISCAS benchmark circuits. In this work the maximum frequency attainable at each supply for a wide variation of voltage is studied from 150mV up to nominal voltage (1.2V). The sub-VT operation is shown to hold the minimum energy-point at roughly 0.29V, which represents a 2X energy-saving compared to the near-VT regime. Although energy-efficiency peaks in sub-VT for the circuits studied, we also show that in this ultra-low VDD the circuit timing and power suffer from substantially increased variability impact and a 30X performance drawback, with respect to near-VT.
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Colombo, Dalton Martini. "Design of analog integrated circuits aiming characterization of radiation and noise." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/133731.
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Esta tese de doutorado trata de dois desafios que projetistas de circuitos integrados analógicos enfrentam quando estimando a confiabilidade de transistores fabricados em modernos processos CMOS: radiação e ruído flicker. Em relação a radiação, o foco desde trabalho é a Dose Total Ionizante (TID): acumulação de dose ionizante (elétrons e prótons) durante um longo período de tempo nas camadas isolantes dos dispositivos, então resultando na degradação dos parâmetros elétricos (por exemplo, a tensão de limiar e as correntes de fuga). Este trabalho apresenta um caso de estudo composto por circuitos referência tensões de baseados na tensão de bandgap e na tensão de limiar dos transistores. Esses circuitos foram fabricados em uma tecnologia comercial CMOS de 130 nm. Um chip contendo os circuitos foi irradiado usando raio gama de uma fonte de cobalto (60 Co), e o impacto dos efeitos da radiação até uma dose de 490 krad nas tensões de saída é apresentado. Foi verificado que o impacto da radiação foi similar ou até mesmo mais severo que os efeitos causados pelo processo de fabricação para a maior parte dos circuitos projetados. Para as referências baseadas na tensão de bandgap implementadas com transistores de óxido fino e grosso, a variação na tensão de saída causada pela radiação foi de 5.5% e 15%, respectivamente. Para as referências baseadas na tensão de limiar, a variação da tensão de saída foi de 2% a 15% dependendo da topologia do circuito. Em relação ao ruído, o foco desta tese é no ruído flicker do transitor MOS quando este está em operação ciclo-estacionária. Nesta condição, a tensão no terminal da porta está constantemente variando durante a operação e o ruído flicker se torna uma função da tensão porta-fonte e não é precisamente estimado pelos tradicionais modelos de ruído flicker dos transistores MOS. Esta tese apresenta um caso de estudo composto por osciladores de tensão (topologia baseada em anel e no tanque LC) projetados em processos 45 e 130 nm. A frequência de oscilação e sua dependência em relação à polarização do substrato dos transistores foi investigada. Considerando o oscilador em anel, a média da variação da frequência de oscilação causada pela variação da tensão de alimentação e da polarização do substrato foi 495 kHz/mV e 81 kHz/mV, respectivamente. A média da frequência de oscilação é de 103,4 MHz e a média do jitter medido para 4 amostras é de 7.6 ps. Para o tanque LC, a frequência de oscilação medida é de 2,419 GHz e sua variação considerando 1 V de variação na tensão de substrato foi de aproximadamente 0,4 %.This thesis is focused on two challenges faced by analog integrated circuit designers when predicting the reliability of transistors implemented in modern CMOS processes: radiation and noise. Regarding radiation, the concern of this work is the Total Ionizing Dose (TID): accumulation of ionizing dose deposited (electrons and protons) over a long time in insulators leading to degradation of electrical parameters of transistors (e.g. threshold voltage and leakage). This work presents a case-study composed by bandgap-based and threshold voltagebased voltage reference circuits implemented in a commercial 130 nm CMOS process. A chip containing the designed circuits was irradiated through γ-ray Cobalt source (60 Co) and the impact of TID effects up to 490 krad on the output voltages is presented. It was found that the impact of radiation on the output voltage accuracy was similar or more severe than the variation caused by the process variability for most of the case-study circuits. For the bandgap-based reference implemented using thin-oxide and thick-oxide transistors, TID effects result in a variation of the output voltage of 5.5 % and 12%, respectively. For the threshold voltage references, the output variation was between 2% and 15% depending on the circuit topology. Regarding noise, the concern of this work is the transistor flicker noise under cyclostationary operation, that is, when the voltage at transistor gate terminal is constantly varying over time. Under these conditions, the flicker noise becomes a function of VGS; and its is not accurately predicted by traditional transistor flicker noise models. This thesis presents a case-study composed by voltage oscillators (inverter-based ring and LC-tank topologies) implemented in 45 and 130 nm CMOS processes. The oscillation frequency and its dependency on the bulk bias were investigated. Considering the ring-oscillator, the average oscillation frequency variation caused by supply voltage and bulk bias variation are 495 kHz/mV and 81 kHz/mV, respectively. The average oscillation frequency is 103.4 MHz for a supply voltage of 700 mV, and the measured averaged period jitter for 4 measured samples is 7.6 ps. For the LC-tank, the measured oscillation frequency was 2.419 GHz and the total frequency variation considering 1 V of bulk bias voltage was only ~ 0.4 %.
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Saligane, Mehdi. "Adaptive body biasing system for margins reduction using delay and temperature monitoring at near threshold operation." Thesis, Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4716.
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La conception de circuit à très faible tension d'alimentation est un moyen depuis longtemps connu pour diminuer la consommation d'énergie des circuits pour un même service rendu [VITTOZ weak inversion]. La faible tension permet de gagner à la fois en courant de fuite [K ROY leakage] et surtout en courant dynamique qui reste la partie de l'énergie consommée la plus ardue a maîtriser. Elle s'accompagne d'un délai multiplié par plusieurs ordres de grandeur et une sensibilité accrue aux variations de paramètres des dispositifs. Cette variation étant plus grande dans les technologies récentes, la conception à très faible tension était jusqu'à récemment limitée aux nœuds technologiques en deçà de 40nm, mais des avancées récentes en technologie 32nm ont été publiés [TI ISSCC2011]. Un premier travail de thèse [ABOUZEID PhD], a permis de confirmer la faisabilité de la conception de circuit ULV. Plus précisément ont été démontrées : · une méthodologie de conception de cellules logiques en technologie 90nm, 65nm, 45nm et 40nm · une adaptation des flots automatiques d'implémentation et de vérification en 40nm · un précurseur de SRAM en CMOS65nm Sur cette base le présent travail de thèse consistera en l'élargissement de l'éventail du champ de conception ULV vers la gestion d'alimentation, la compensation des conditions environnementales et l'optimisation architecturale afin de préparer l'industrialisation de futures applications ULVIoT applications continue to push towards ultra-low-power constrained ASICs, creating severe challenges to achieve sufficient power efficiency in extreme Voltage and Temperature conditions. Thus, it is necessary to build closed-loop compensation systems that are autonomous to environmental conditions especially temperature at sub-threshold regime. Two major work are proposed: an adaptive techniques that allow to enhance the performance of designs that leverage aggressive voltage scaling. we fully exploits the FD-SOI 28nm technology dual gate capabilities to both attain optimal power efficiency points and compensate for gradual changes in overall device performance due to process, voltage, and temperature variations. Our proposed compensation Unit system is a fully-digital error-prediction solution providing a compromise between industry reliability requirements and manufacturing guard-band reduction with low-invasiveness and post-silicon tunability. Critical-Paths timing monitors are distributed across the processor and tuned to match the closest critical paths. A programmable workload emulator allows to adapt and take into account the processor tasks. Generated warning Flags due to V-T variations are analyzed based on an adjustable warning rate and body bias is adapted correspondingly. Based on the operation voltage, either fine or coarse body biasing can be activated for compensation. The second part of this thesis addresses on-chip temperature monitoring that plagues aggressively voltage scaled ASICs. We propose to closely monitor temperature fluctuations at low-voltage but also hot-spot detection at nominal and over-drive supply voltage conditions
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Martins, Mayler Gama Alvarenga. "Applications of functional composition for CMOS and emerging technologies." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/164452.
Full textAbstract:
Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A composição funcional é uma abordagem de síntese de baixo para cima, provendo flexibilidade para implementar algoritmos com resultados ótimos ou sub-ótimos para diferentes tecnologias. A fim de investigar como a composição funcional se compara às abordagens de síntese estado-da-arte, propomos aplicar esse paradigma de síntese em seis cenários diferentes. Dois deles se concentram em circuitos baseados em CMOS e outros quatro em circuitos baseados em tecnologias emergentes. Em relação a circuitos baseados em CMOS, investigamos a composição funcional para fatoração de funções multi-saídas, aplicadas em um fluxo de resíntese. Também manipulamos funções aproximadas, a fim de sintetizar módulos de redundância tripla aproximada. No que diz respeito as tecnologias emergentes, exploramos a composição funcional através de diodos spintrônicos e outras abordagens promissoras com base em diferentes implementações de lógica: a lógica de limiar, lógica majoritária e lógica de implicação. Resultados apresentam uma melhoria considerável em relação aos métodos estadoda- arte tanto para aplicações CMOS quanto aplicações de tecnologias emergentes, demonstrando a capacidade de lidar com diferentes tecnologias e mostrando a possibilidade de melhorar tecnologias ainda não exploradas.The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.
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Cardoso, Guilherme Schwanke. "Impacto dos desvios de tensão de limiar induzidos por radiação ionizante no desempenho dos blocos básicos de dois amplificadores operacionais complementares." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/61871.
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Este trabalho estuda os efeitos de dose total ionizante (TID – Total Ionizing Dose) em amplificadores operacionais e em seus blocos básicos de construção. A radiação ionizante presente no espaço pode afetar o funcionamento das estruturas MOS, sendo que um dos parâmetros mais prejudicados é a tensão de limiar (Threshold Voltage). Em virtude da diferença nos mecanismos de aprisionamento de cargas nos óxidos dos transistores do tipo N e do tipo P, esses dois dispositivos exibem comportamentos distintos à medida que a dose acumulada aumenta referente à tensão de limiar. Por isso, foram investigados os comportamentos de dois tipos de amplificadores que podem ser ditos complementares entre si. Nesse contexto, através de simulações SPICE desvios na tensão de limiar foram promovidos através da injeção direta no arquivo de parâmetros da tecnologia considerada. Com isso, um conjunto de simulações foi feito para gerar a estimativa da tendência de comportamento de parâmetros que qualificam o desempenho dos amplificadores operacionais, como é o caso do produto ganho largura de banda (GB), ganho DC e THD (Total Harmonic Distortion). Nesse sentido, foi possível compreender os mecanismos associados à degradação de desempenho e concluir qual das duas arquiteturas pode apresentar melhor desempenho relacionado à TID.This work studies the effects of Total Ionizing Dose (TID) in operational amplifiers as well as in their basics building blocks. The radiation from space may affect functionality of MOS structures. One the most affected parameters is the threshold voltage. Due to the difference between N-type and P-type transistors related to the mechanism of charge trapping into the oxides, these two devices exhibit different behaviors, related to the threshold voltage parameter according to accumulated dose. Therefore, this work investigates the behavior of two counterpart operational amplifiers. In this context, by means of SPICE simulations, threshold deviations are injected into the transistors by modifying the technology models of the devices. Thus, a set of simulations was performed in order to generate an estimative of tendency for some of performance parameters of operational amplifiers, such as: the gain-bandwidth product (GB), DC gain, THD (Total Harmonic Distortion). In this sense, it was possible to understand the mechanisms associated to performance degradation and also, to conclude which of both architectures is more robust related to TID.
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Sebastian, Johny. "A Temperature stabilised CMOS VCO based on amplitude control." Diss., University of Pretoria, 2013. http://hdl.handle.net/2263/33447.
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Speed, power and reliability of analogue integrated circuits (IC) exhibit temperature dependency through the modulation of one or several of the following variables: band gap energy of the semiconductor, mobility, carrier diffusion, current density, threshold voltage, interconnect resistance, and variability in passive components. Some of the adverse effects of temperature variations are observed in current and voltage reference circuits, and frequency drift in oscillators. Thermal instability of a voltage-controlled oscillator (VCO) is a critical design factor for radio frequency ICs, such as transceiver circuits in communication networks, data link protocols, medical wireless sensor networks and microelectromechanical resonators. For example, frequency drift in a transceiver system results in severe inter-symbol interference in a digital communications system. Minimum transconductance required to sustain oscillation is specified by Barkhausen’s stability criterion. However it is common practice to design oscillators with much more transconductance enabling self-startup. As temperature is increased, several of the variables mentioned induce additional transconductance to the oscillator. This in turn translates to a negative frequency drift.
Conventional approaches in temperature compensation involve temperature-insensitive biasing proportional-to-absolute temperature, modifying the control voltage terminal of the VCO using an appropriately generated voltage. Improved frequency stability is reported when compensation voltage closely follows the frequency drift profile of the VCO. However, several published articles link the close association between oscillation amplitude and oscillation frequency. To the knowledge of this author, few published journal articles have focused on amplitude control techniques to reduce frequency drift. This dissertation focuses on reducing the frequency drift resulting from temperature variations based on amplitude control. A corresponding hypothesis is formulated, where the research outcome proposes improved frequency stability in response to temperature variations.
In order to validate this principle, a temperature compensated VCO is designed in schematic and in layout, verified using a simulation program with integrated circuit emphasis tool using the corresponding process design kit provided by the foundry, and prototyped using standard complementary metal oxide semiconductor technology. Periodic steady state (PSS) analysis is performed using the open loop VCO with temperature as the parametric variable in five equal intervals from 0 – 125 °C. A consistent negative frequency shift is observed in every temperature interval (≈ 11 MHz), with an overall frequency drift of 57 MHz. However similar PSS analysis performed using a VCO in the temperature stabilised loop demonstrates a reduced negative frequency drift of 3.8 MHz in the first temperature interval. During the remaining temperature intervals the closed loop action of the amplitude control loop overcompensates for the negative frequency drift, resulting in an overall frequency spread of 4.8 MHz. The negative frequency drift in the first temperature interval of 0 to 25 °C is due to the fact that amplitude control is not fully effective, as the oscillation amplitude is still building up. Using the temperature stabilised loop, the overall frequency stability has improved to 16 parts per million (ppm)/°C from an uncompensated value of 189 ppm/°C.
The results obtained are critically evaluated and conclusions are drawn. Temperature stabilised VCOs are applicable in applications or technologies such as high speed-universal serial bus, serial advanced technology attachment where frequency stability requirements are less stringent. The implications of this study for the existing body of knowledge are that better temperature compensation can be obtained if any of the conventional compensation schemes is preceded by amplitude control.Dissertation (MEng)--University of Pretoria, 2013.
Electrical, Electronic and Computer Engineering
unrestricted
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Ahmad, Salleh. "Développement et réalisation d'un circuit de microélectronique pour le détecteur spatial de rayons cosmiques JEM-EUSO." Thesis, Paris 11, 2012. http://www.theses.fr/2012PA112327.
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Extreme Universe Space Observatory on Japanese Experiment Module (JEM-EUSO) est conçu comme l’expérience de rayons cosmiques de prochaine génération pour observer les particules hautement énergétiques au-dessus de 10²⁰ eV. Le projet est mené par RIKEN et soutenu par une collaboration de plus de 200 membres provenant de 13 pays. Cet observatoire, sous la forme d'un télescope fluorescent, sera arrimé à la Station Spatiale internationale (ISS) pour un lancement prévu en 2017. En observant les gerbes atmosphériques produites dans la troposphère, à une altitude de 400 km, cet observatoire de rayons cosmique offrira une grande surface de détection, qui est au moins 100 fois supérieur que le plus grand détecteur de rayons cosmiques jamais construit. La surface focale de JEM-EUSO sera équipée d'environ 5000 unités de photomultiplicateur multianode 8x8 pixels (MAPMT). Un circuit intégré (ASIC), connu sous le nom SPACIROC, a été proposé pour la lecture du MAPMT. Cet ASIC de 64 voies propose des fonctionnalités comme le comptage de photons, la mesure des charges et le transfert de données à haute vitesse. Par-dessus tout, cet ASIC doit peu consommé afin de respecter la contrainte de puissance de JEM-EUSO. Réalisé en utilisant la technologie AMS Silicium-Germanium (SiGe) 0,35 µm, cet ASIC intègre 64 canaux de comptage de photons rapides (Photon Counting). La résolution de temps pour le comptage de photons est de 30 ns, ce qui permettra d’atteindre la valeur maximale comptage qui est de l'ordre de 10⁷ photons / s. Le système de mesure de charge est basé sur le Time-Over-Threshold qui offre 8 canaux de mesure. Chaque canal de mesure est une somme des 8 pixels du MAPMT et il est prévu que ce système est capable de mesurer jusqu'à 200 pC. La partie numérique fonctionne en continu et gère la conversion des données de chaque voie des blocs de Photon Counting et Time-Over-Threshold. Les données numériques sont transmises par l'intermédiaire de liaisons parallèles dédiées et ces opérations sont effectuées pendant une fenêtre de communication ou « Gate Time Unit » (GTU) de fréquence 400 kHz. Le taux de transfert des données d’ASIC avoisine les 200 Mbps ou 576 bits / GTU. La dissipation de puissance est strictement inférieure à 1 mW par canal ou 64 mW pour l'ASIC. Le premier prototype de SPACIROC a été envoyé pour fabrication en Mars 2010 au Centre Multi Projet (CMP). Des puces nues et packagés ont été reçues en Octobre 2010, ce qui a débuté la phase de caractérisation de cet ASIC. Après une phase de test réussie, des puces SPACIROC ont été intégrés dans l'électronique frontale d'un instrument pour détecter les sursauts gamma - Ultra Fast Flash Observatoire (UFFO) qui va être lancé en 2013. Vers la fin de l'année 2012, des cartes électroniques frontales conçues autour des puces SPACIROC ont été fabriqués pour le projet EUSO-Balloon. Ce projet de vol en ballon stratosphérique à une altitude de 40 km servira comme le démonstrateur technologique et l'ingénierie d'un instrument miniaturisé JEM-EUSO. La deuxième génération de cet ASIC a été envoyée à la fonderie en Décembre 2011. Ce second prototype, SPACIROC2, a été testé à partir de mai 2012. Les principales améliorations sont les suivantes: la consommation d'énergie a été revue à la baisse, ainsi que l'amélioration de la résolution temporelle de Photon Counting et l'extension de la gamme dynamique pour le module Time-Over-Threshold. Les mesures en cours ont montré que SPACIROC2 présente un bon comportement général et apporte des améliorations par rapport à son prédécesseurExtreme Universe Space Observatory on Japanese Experiment Module (JEM-EUSO) is conceived as the next generation cosmic rays experiment for observing the highly energetic particles above 5.10¹⁹ eV. The project is lead by RIKEN and supported by an active collaboration of more than 200 members from 13 countries. This observatory, in the shape of a wide field-of-view UV telescope, will be attached to the International Space Station (ISS) for a planned launch in 2017. Observing the Air Showers generated in troposphere from an altitude of 400 km, this space based cosmic rays experiment will offer a very large instantaneous detection surface, which is at least 100 times bigger than the largest land based cosmic rays observatory. The detection surface of JEM-EUSO will be equipped with around 5000 units of 8x8 pixels Multianode Photomultiplier (MAPMT). A radiation hardened mixed signal application-specific integrated circuit (ASIC), known as SPACIROC, has been proposed for reading out the MAPMT. This ASIC features 64-channel analog inputs, fast photon counting capabilities, charge measurements and high-speed data transfer. Above all, the power dissipation of this ASIC is required to be very low in order to comply with the strict power budget of JEM-EUSO. By taking the advantages of high speed AMS 0.35 µm Silicon-Germanium (SiGe) process, this ASIC integrates 64 fast Photon Counting channels. The photon counting time resolution is 30 ns, which allows the theoretical counting rate in the order of 10⁷ photons/s. The charge measurement system is based on Time-Over-Threshold which offers 8 measurement channels. Each measurement channel is composed of 8 pixels of the MAPMT and it is expected that this system will measure up to 200 pC. The digital part is then required to operate continuously and handles data conversion of each Photon Counting and Time-Over-Threshold channel. For the first version of this ASIC, one channel measurement channel for the dynode is also available. The digital data are transmitted via dedicated parallel communication links and within the defined Gate Time Unit (GTU) of 400 kHz frequency. The ASIC data output rate is in the vicinity of 200 Mbps or 576 bits/GTU. The power dissipation is kept strictly below 1 mW per channel or 64 mW for the ASIC. The first prototype of SPACIROC was sent for tapeout in March 2010 through Centre Multi Projet (CMP) prototyping services. The packaged ASICs and bare dies have been received in October 2010 which marked the characterization phase of this chip. After successful testing phase, SPACIROC chips were integrated into the front-end electronics of an instrument pathfinder for detecting the gamma ray bursts – Ultra Fast Flash Observatory (UFFO) which is foreseen to be launched in 2013. Towards the end of 2012, front-end board designed around SPACIROC chips have been fabricated for the EUSO-Balloon project. This balloon borne project will serve as a technical and engineering demonstrator of a fully miniaturized JEM-EUSO instrument which will be flown to the stratosphere at the altitude of 40 km. The second tapeout of this ASIC was done in December 2011. This second prototype, SPACIROC2, was tested from May 2012. The main improvements are as follows: lower power consumption due to better power management, enhancement in Photon Counting time resolution and extension the Time-Over-Threshold maximum input rate. The ongoing tests have shown that SPACIROC2 exhibits a good overall behavior and improvement compared to its predecessor
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Bortolon, Felipe Todeschini. "Static noise margin analysis for CMOS logic cells in near-threshold." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/178664.
Full textAbstract:
Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%).The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).
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Calhoun, Benton Highsmith 1978. "Low energy digital circuit design using sub-threshold operation." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/35527.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2006.Includes bibliographical references (p. 189-202).
Scaling of process technologies to deep sub-micron dimensions has made power management a significant concern for circuit designers. For emerging low power applications such as distributed micro-sensor networks or medical applications, low energy operation is the primary concern instead of speed, with the eventual goal of harvesting energy from the environment. Sub-threshold operation offers a promising solution for ultra-low-energy applications because it often achieves the minimum energy per operation. While initial explorations into sub-threshold circuits demonstrate its promise, sub-threshold circuit design remains in its infancy. This thesis makes several contributions that make sub-threshold design more accessible to circuit designers. First, a model for energy consumption in sub-threshold provides an analytical solution for the optimum VDD to minimize energy. Fitting this model to a generic circuit allows easy estimation of the impact of processing and environmental parameters on the minimum energy point. Second, analysis of device sizing for sub-threshold circuits shows the trade-offs between sizing for minimum energy and for minimum voltage operation.
(cont.) A programmable FIR filter test chip fabricated in 0.18pum bulk CMOS provides measurements to confirm the model and the sizing analysis. Third, a low-overhead method for integrating sub-threshold operation with high performance applications extends dynamic voltage scaling across orders of magnitude of frequency and provides energy scalability down to the minimum energy point. A 90nm bulk CMOS test chip confirms the range of operation for ultra-dynamic voltage scaling. Finally, sub-threshold operation is extended to memories. Analysis of traditional SRAM bitcells and architectures leads to development of a new bitcell for robust sub-threshold SRAM operation. The sub-threshold SRAM is analyzed experimentally in a 65nm bulk CMOS test chip.
by Benton H. Calhoun.
Ph.D.
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Molin, Quentin. "Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI111.
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Ce manuscrit est une contribution à l’étude de la fiabilité et de la robustesse des composants MOSFET sur carbure de silicium, matériau semi-conducteur grand gap qui possède des caractéristiques bien meilleures que le silicium. Ces nouveaux interrupteurs de puissances permettent d’obtenir entre autres propriétés remarquables, des fréquences de commutations et des tenues en tension plus élevées dans les systèmes de conversions de puissance. Ils sont particulièrement mis en avant depuis un peu plus d’une dizaine d’années pour les gains en performances, diminution des tailles et poids qu’ils apportent à certaines topologies de convertisseurs pour les réseaux haute tension à courant continu. Puis sont répertoriés les principaux mécanismes de défaillances de ces MOSFET SiC induits par la faiblesse de la grille. Toutes les mesures nécessaires au suivi des paramètres clés lors des prochains vieillissements sont présentées. Les résultats de nos tests sur l’instabilité de la tension de seuil sont aussi détaillés et un modèle empirique pour valider le comportement de relaxation observé est proposé. Celui-ci nous aidera par la suite à établir un protocole de mesure rigoureux de la tension de seuil. Les tests expérimentaux et résultats de vieillissement en statique et dynamique sur les composants 1,7 kV vont permettre de se rendre compte de l’importance de la dérive de la tension de seuil sur 1000 h. Dans le cas d’un vieillissement statique, il y a environ 7 % de dérive positive du VTH et un pourcentage équivalent pour les tests dynamiques. Des analyses supplémentaires (C-V et pompage de charge) sur l’oxyde de grille en cours de vieillissement sont proposées pour une meilleure compréhension des mécanismes mis en jeu dans la dégradation de l’oxyde. Enfin, les derniers tests présentés seront focalisés sur le comportement en court-circuit et courts-circuits répétitifs des mêmes composants. Avec une énergie critique évaluée autour de 1,5 J nos tests sur les MOSFET 1,7 kV montrent les limites de la robustesse de ces composants, avec une tenue en court-circuit bien inférieure à 10 µs et une incapacité à résister à plus de 150 courts-circuits successifs. L’influence de la tension entre drain et source y est notamment étudiée, et montre que l’énergie critique supportée par le composant diminue avec l’augmentation de cette tensionThis manuscript is a contribution to reliability and robustness study of MOSFET components on silicon carbide “SiC”, wide band gap semiconductor with better characteristics compared to silicon “Si” material. Those new power switches can provide better switching frequencies or voltage withstanding for example in power converter. SiC MOSFET are the results of approximately 10 years of research and development and can provide increased performances and weight to some converter topology for high voltage direct current networks. Others power switches available are still introduced and an introduction to reliability is explaining why such work on this new power switches is important. Transition from Si technologies to SiC ones require a lot of work regarding its robustness. Before showing reliability and robustness results is presented I give a lot of details regarding to the measurement and monitoring of key parameters used in the next chapters. The results of our tests on the threshold voltage instability are presented and how we validated an empirical model on this drift. This was used to propose an enhanced measurement protocol on the threshold voltage. Static and dynamic experimental results presented next will show if the voltage drift during ageing is significant or not. Further analysis is proposed to add more insight on the understanding of the oxide degradation mechanisms through C-V and charge pumping measurements. Finally, the ageing results presented on 1,7 kV SiC MOSFET are focused on the short-circuit and repetitive short-circuit behavior of the same components. Drain to source voltage influence on critical energy during this particular and stressful operation mode is studied. This time, the results are worrying.The last chapter is confidential
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Diril, Abdulkadir Utku. "Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6929.
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Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting the cost of the systems while the systems are filled with extra functionalities. This is the reason why a 3 GHz Intel processor now is priced less than what a 50MHz processor was priced 10 years ago. As in most cases, this comes with a price. This price is the complex design process and problems that stem from the reduction in physical dimensions.
As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the design flow to address these issues at every step of the design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft error tolerance of digital systems is considered as a trade off problem between power and reliability and a power aware dynamic soft error tolerance control strategy is developed.
The objective of this research is to provide CAD tools and circuit design techniques to optimize power consumption and to increase soft error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft error tolerance control scheme.
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Chen, Jian. "ULTRA LOW POWER READ-OUT INTEGRATED CIRCUIT DESIGN." Wright State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=wright1345480982.
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LIMA, FILHO Cristóvão Mácio de Oliveira. "Circuito integrado para multiplicação em GF(24) utilizando portas de limiar linear." Universidade Federal de Campina Grande, 2010. http://dspace.sti.ufcg.edu.br:8080/jspui/handle/riufcg/1504.
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CRISTOVÃO MÁCIO DE OLIVEIRA LIMA FILHO - DISSERTAÇÃO PPGEE 2010..pdf: 2095765 bytes, checksum: 1c2232fd0f1557df7308e04bad6426c2 (MD5)Made available in DSpace on 2018-08-20T19:33:13Z (GMT). No. of bitstreams: 1 CRISTOVÃO MÁCIO DE OLIVEIRA LIMA FILHO - DISSERTAÇÃO PPGEE 2010..pdf: 2095765 bytes, checksum: 1c2232fd0f1557df7308e04bad6426c2 (MD5) Previous issue date: 2010-06-09
Esta dissertação descreve o desenvolvimento de um leiaute de uma nova arquitetura de multiplicador em corpos finitos baseada no multiplicador de Mastrovito. Tal arquitetura tem como unidades de processamento as portas de limiar linear, que é o elemento básico de uma rede neural discreta. As redes neurais discretas implementadas com portas de limiar linear permitem reduzir a complexidade de certos circuitos antes implementados com lógica tradicional (Portas AND, OR e NOT). Com isso, a idéia de estender o uso de portas de limiar linear em operações aritméticas em corpos finitos se torna bastante atraente. Assim, para comprovar de forma prática, a eficiência das portas de limiar linear, a arquitetura de um multiplicador em GF(24), proposta em (LIDIANO - 2000), foi implementada utilizando as ferramentas de desenho de leiaute de circuito integrado da Mentor Graphics®. Os resultados da simulação do leiaute do circuito integrado do multiplicador em GF(24) são apresentados. Os mesmos indicaram um desempenho abaixo do esperado, devido a complexidade espacial do multiplicador em GF(2n) com 4=n não ser suficiente para que as vantagens da implementação com portas de limiar linear sejam visualizada.
This dissertation describes the development of a layout of new multiplication architecture in Galois field based on the Mastrovito multiplier. The processing unit of this new architecture is a threshold logic gate, which is a basic element of a discrete neural network. The discrete neural network built with threshold logic gates allow reduce de complexity of a certain circuits once built using traditional boolean gates (AND, OR and NOT). Therewith, the idea of extending the advantages of the threshold logic gates for arithmetic operations in Galois field to become very attractive. Thus, to confirm into practice form, the advantages of the threshold logic gates, a multiplier architecture in GF(24), proposed in (LIDIANO - 2000), was implemented using the integrated circuit layout tools of Mentor Graphics®. The results from simulations of the layout of multiplier in GF(24) are presented. These results indicated a low performance, due to the space complexity of GF(2n) multiplier with n = 4 is not enough for show the advantages of the multiplier implementation with threshold logic gates.
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Scaff, Robson. "Caracterização elétrica de dispositivos tipo ISFET com estrutura Si/SiO2/Si3N4 para medição de pH utilizando pseudoeletrodos de Pt, Ag e Au." Universidade de São Paulo, 2008. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01102008-142910/.
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Neste trabalho, foi realizado um estudo da caracterização elétrica dos ISFETs com estrutura Si/SiO2/Si3N4, utilizando pseudoeletrodos de Pt, Ag e Au como alternativas aos eletrodos convencionais para medições de pH. Primeiramente, foram empregados três métodos reportados na literatura (extrapolação linear para obtenção da tensão de limiar, segunda derivada para obtenção da tensão de limiar e corrente de sublimiar, respectivamente) com o objetivo de obter a sensibilidade dos ISFETs (mV/pH) e analisar a confiabilidade dos resultados utilizando eletrodo de referência padrão de Ag/AgCl. Posteriormente, tendo como base o eletrodo de Ag/AgCl, foram estudados os desempenhos de pseudoeletrodos de Pt, Ag e Au nas medidas de pH. Como resultado, observou-se que os pseudoeletrodos de Pt e Ag apresentaram sensibilidades compatíveis com o eletrodo de referência padrão de Ag/AgCl (~50mV/pH) para pH ácido na faixa de 1 a 3. Já o pseudoeletrodo de Au, manteve um comportamento aproximadamente linear ao longo de toda a faixa de pH estudada (1 a 10), porém, com sensibilidade inferior na faixa de 32 à 34mV/pH.In this work, it is presented a study of the electrical characterization of Si/SiO2/Si3N4 estructured ISFETs using Pt, Ag and Au pseudoelectrodes as alternative references to the conventional ones for pH measurements. At first, it was used three different methods (linear extrapolation method to obtain the threshold voltage, second derivative method to obtain the threshold voltage and subthreshold-current method, respectively) having as objective to obtain the sensitivity of the ISFETs (mV/pH) and to analyze the reliability of the results using the standard Ag/AgCl reference electrode. Subsequently, using the Ag/AgCl electrode as a base for comparation, it was studied the performance of Pt, Ag and Au pseudoelectrodes for pH measurement. As a result, it was observed that the Pt and Ag electrodes presented sensitivity similar to the standard Ag/AgCl reference electrode (~50mV/pH) for pH in the range of 1 to 3. On the other hand, the Au pseudoelectrode presented an approximately linear behavior in all studied range of the pH (1 to 10), but, with lower sensitivity varying in the range of 32 to 34mV/pH.
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Rosa, André Luís Rodeghiero. "Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/118526.
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Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP).This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).
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Kripalani, Rishi A. "Novel Integration of Conductive-ink Circuitry with a Paper-based Microfluidic Battery as an All-printed Sensing Platform." DigitalCommons@CalPoly, 2016. https://digitalcommons.calpoly.edu/theses/1694.
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The addition of powered components for active assays into paper-based analytical devices opens new opportunities for medical and environmental analysis in resource-limited applications. Current battery designs within such devices have yet to adopt a ubiquitous circuitry material, necessitating investigation into printed circuitry for scalable platforms. In this study, a microfluidic battery was mated with silver-nanoparticle conductive ink to prototype an all-printed sensing platform. A multi-layer, two-cell device was fabricated, generating 200 μA of direct electrical current at 2.5 V sustained for 16 minutes with a power loss of less than 0.1% through the printed circuitry. Printed circuitry traces exhibited resistivity of 75 to 211 10-5 Ω m. Resistance of the printed traces increased upwards of 200% depending on fold angle and directionality. X-ray diffraction confirmed the presence of face-centered cubic silver after sintering printed traces for 30 minutes at 150°C in air. A conductivity threshold was mapped and an ink concentration of 0.636 μL mm-3 was identified as the lower limit for optimal electrical performance.
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Rummens, François. "Systèmes intégrés pour l'hybridation vivant-artificiel : modélisation et conception d'une chaîne de détection analogique adaptative." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0431/document.
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La bioélectronique est un domaine transdisciplinaire qui oeuvre, entre autres, àl’interconnexion entre des systèmes biologiques présentant une activité électrique et le mondede l’électronique. Cette communication avec le vivant implique l’observation de l’activitéélectrique des cellules considérées et nécessite donc une chaine d’acquisition électronique.L’utilisation de Multi/Micro Electrodes Array débouche sur des systèmes devantacquérir un grand nombre de canaux en parallèle, dès lors la consommation etl’encombrement des circuits d’acquisition ont un impact significatif sur la viabilité dusystème destiné à être implanté.Cette thèse propose deux réflexions à propos de ces circuits d’acquisition. Une ces desréflexions a trait aux circuits d’amplification, à leur impédance d’entrée et à leurconsommation ; l’autre concerne un détecteur de potentiels d’action analogique, samodélisation et son optimisation.Ces travaux théoriques ayant abouti à des résultats concrets, un ASIC a été conçu,fabriqué, testé et caractérisé au cours de cette thèse. Cet ASIC à huit canaux comporte doncdes amplificateurs et des détecteurs de potentiels d’action analogiques et constitue le principalapport de ce travail de thèseBioelectronics is a transdisciplinary field which develops interconnection devicesbetween biological systems presenting electrical activity and the world of electronics. Thiscommunication with living tissues implies to observe the electrical activity of the cells andtherefore requires an electronic acquisition chain.The use of Multi / Micro Electrode Array leads to systems that acquire a large numberof parallel channels, thus consumption and congestion of acquisition circuits have asignificant impact on the viability of the system to be implanted.This thesis proposes two reflections about these acquisition circuits. One of thesereflections relates to amplifier circuits, their input impedance and consumption; the otherconcerns an analogue action potentials detector, its modeling and optimization.These theoretical work leading to concrete results, an ASIC was designed,manufactured, tested and characterized in this thesis. This eight-channel ASIC thereforeincludes amplifiers and analogue action potentials detector and is the main contribution of thisthesis
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Paniz, Vitor. "Simulação elétrica do efeito de dose total em células de memória estática (SRAM)." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27264.
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Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID.This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.
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yasami, saeed. "Design and Evaluation of an Ultra-Low PowerLow Noise Amplifier LNA." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50923.
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This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW
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Carstensen, Anna-Karin. "Connect : Modelling Learning to Facilitate Linking Models and the Real World trough Lab-Work in Electric Circuit Courses for Engineering Students." Doctoral thesis, Linköpings universitet, Fysik och elektroteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-97395.
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A recurring question in science and engineering education is why the students do not link knowledge from theoretical classes to the real world met in laboratory courses. Mathematical models and visualisations are widely used in engineering and engineering education. Very often it is assumed that the students are familiar with the mathematical concepts used. These may be concepts taught in high school or at university level. One problem, though, is that many students have never or seldom applied their mathematical skills in other subjects, and it may be difficult for them to use their skills in a new context. Some concepts also seem to be "too difficult" to understand. One of these mathematical tools is to use Laplace Transforms to solve differential equations, and to use the derived functions to visualise transient responses in electric circuits, or control engineering. In many engineering programs at college level the application of the Laplace Transform is considered too difficult for the students to understand, but is it really, or does it depend on the teaching methods used? When applying mathematical concepts during lab work, and not teaching the mathematics and practical work in different sessions, and also using examples varied in a very systematic way, our research shows that the students approach the problem in a very different way. It shows that by developing tasks consequently according to the Theory of Variation, it is not impossible to apply the Laplace Transform already in the first year of an engineering program. The original aim of this thesis was to show: how students work with lab-tasks, especially concerning the goal to link theory to the real world how it is possible to change the ways students approach the task and thus their learning, by systematic changes in the lab-instructions During the spring 2002 students were video-recorded while working with labs in Electric Circuits. Their activity was analysed. Special focus was on what questions the students raised, and in what ways these questions were answered, and in what ways the answers were used in the further activities. This work informed the model ”learning of a complex concept”, which was used as well to analyse what students do during lab-work, and what teachers intend their students to learn. The model made it possible to see what changes in the lab-instructions that would facilitate students learning of the whole, to link theoretical models to the real world, through the labactivities. The aim of the thesis has thus become to develop a model: The learning of a complex concept show how this model can be used as well for analysis of the intended object of learning as students activities during lab-work, and thus the lived object of learning use the model in analysis of what changes in instruction that are critical for student learning. The model was used to change the instructions. The teacher interventions were included into the instructions in a systematic way, according to as well what questions that were raised by the students, as what questions that were not noticed, but expected by the teachers, as a means to form relations between theoretical aspects and measurement results. Also, problem solving sessions have been integrated into the lab sessions. Video recordings were also conducted during the spring 2003, when the new instructions were used. The students' activities were again analysed. A special focus of the thesis concerns the differences between the results from 2002 and 2003. The results are presented in four sections: Analysis of the students' questions and the teachers' answers during the lab-course 2002 Analysis of the links students need to make, the critical links for learning Analysis of the task structure before and after changes Analysis of the students' activities during the new course The thesis ends with a discussion of the conclusions which may be drawn about the possibilities to model and develop teaching sequences through research, especially concerning the aim to link theoretical models to the real world.En stående fråga som lärare i naturvetenskapliga och tekniska utbildningar ställer är varför elever och studenter inte kopplar samman kunskaper från teoretiska kursmoment med den verklighet som möts vid laborationerna. Ett vanligt syfte med laborationer är att åstadkomma länkar mellan teori och verklighet, men dessa uteblir ofta. Många gånger används avancerade matematiska modeller och grafiska representationer, vilka studenterna lärt sig i tidigare kurser, men de har sällan eller aldrig tillämpat dessa kunskaper i andra ämnen. En av dessa matematiska hjälpmedel är Laplacetransformen, som främst används för att lösa differentialekvationer, och åskådliggöra transienta förlopp i ellära eller reglerteknik. På många universitet anses Laplacetransformen numera för svår för studenterna på kortare ingenjörsutbildningar, och kurser eller kursmoment som kräver denna har strukits ut utbildningsplanerna. Men, är det för svårt, eller beror det bara på hur man presenterar Laplacetransformen? Genom att låta studenterna arbeta parallellt med matematiken och de laborativa momenten, under kombinerade lab-lektionspass, och inte vid separata lektioner och laborationer, samt genom att variera övningsexemplen på ett mycket systematiskt sätt, enligt variationsteorin, visar vår forskning att studenterna arbetar med uppgifterna på ett helt annat sätt än tidigare. Det visar sig inte längre vara omöjligt att tillämpa Laplacetransformen redan under första året på civilingenjörsutbildning inom elektroteknik. Ursprungliga syftet med avhandlingen var att visa hur studenter arbetar med laborationsuppgifter, speciellt i relation till målet att länka samman teori och verklighet hur man kan förändra studenternas aktivitet, och därmed studenternas lärande, genom att förändra laborationsinstruktionen på ett systematiskt sätt. Under våren 2002 videofilmades studenter som utförde laborationer i en kurs i elkretsteori. Deras aktivitet analyserades. Speciellt studerades vilka frågor studenterna ställde till lärarna, på vilket sätt dessa frågor besvarades, och på vilket sätt svaren användes i den fortsatta aktiviteten. Detta ledde fram till en modell för lärande av sammansatta begrepp, som kunde användas både för att analysera vad studenterna gör och vad lärarna förväntar sig att studenterna ska lära sig. Med hjälp av modellen blev det då möjligt att se vad som behövde ändra i instruktionerna för att studenterna lättare skulle kunna utföra de aktiviteter som krävs för att länka teori och verklighet. Syftet med avhandlingen är därmed att ta fram en modell för lärande av ett sammansatt begrepp visa hur denna modell kan användas för såväl analys av önskat lärandeobjekt, som av studenternas aktivitet under laborationer, och därmed det upplevda lärandeobjektet använda modellen för att analysera vilka förändringar som är kritiska för studenters lärande. Modellen användes för att förändra laborationsinstruktionerna. Lärarinterventionerna inkluderades i instruktionerna på ett systematiskt sätt utifrån dels vilka frågor som ställdes av studenterna, dels vilka frågor studenterna inte noterade, men som lärarna velat att studenterna skulle använda för att skapa relationer framför allt mellan teoretiska aspekter och mätresultat. Dessutom integrerades räkneövningar och laborationer. Videoinspelningar utfördes även våren 2003, då de nya instruktionerna användes. Även dessa analyserades med avseende på studenternas aktiviteter. Skillnader mellan resultaten från 2002 och 2003 står i fokus. Avhandlingens resultatdel består av: Analys av studenternas frågor och lärarnas svar under labkursen 2002 Analys av de länkar studenterna behöver skapa för att lära Analys av laborationsinstruktionerna före och efter förändringarna Analys av den laborationsaktivitet som blev resultatet av de nya instruktionerna, och vilket lärande som då blev möjligt Avhandlingen avlutas med en diskussion om de slutsatser som kan dras angående möjligheter att via forskning utveckla modeller av undervisningssekvenser för lärande där målet är att länka samman teori och verklighet
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Labouré, Iooss Marie-José. "Faisabilité d'une carte électronique d'opérateurs de seuillage : déformation d'objets plans lors de transformations de type morphologique." Saint-Etienne, 1987. http://www.theses.fr/1987STET4014.
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Etude de la segmentation d'une image et plus particulièrement du seuillage d'une image. Classification de formes planes. De nombreux algorithmes sont présentés. La plupart sont fondés sur la connaissance de l'histogramme des niveaux de gris. Une carte électronique de seuillage a été développée. Des méthodes originales de détection de contours sont aussi explicitées. Dans une deuxième partie, une étude sur les déformations d'objets plans après dilatations successives est présentée
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Ponnuswami, Ashok Kumar. "Intractability Results for some Computational Problems." Diss., Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24638.
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In this thesis, we show results for some well-studied problems from learning theory and combinatorial optimization.
Learning Parities under the Uniform Distribution: We study the learnability of parities in the agnostic learning framework of Haussler and Kearns et al. We show that under the uniform distribution, agnostically learning parities reduces to learning parities with random classification noise, commonly referred to as the noisy parity problem. Together with the parity learning algorithm of Blum et al, this gives the first nontrivial algorithm for agnostic learning of parities. We use similar techniques to reduce learning of two other fundamental concept classes under the uniform distribution to learning of noisy parities. Namely, we show that learning of DNF expressions reduces to learning noisy parities of just logarithmic number of variables and learning of k-juntas reduces to learning noisy parities of k variables.
Agnostic Learning of Halfspaces: We give an essentially optimal hardness result for agnostic learning of halfspaces over rationals. We show that for any constant ε finding a halfspace that agrees with an unknown function on 1/2+ε fraction of examples is NP-hard even when there exists a halfspace that agrees with the unknown function on 1-ε fraction of examples. This significantly improves on a number of previous hardness results for this problem. We extend the result to ε = 2[superscript-Ω(sqrt{log n})] assuming NP is not contained in DTIME(2[superscript(log n)O(1)]). Majorities of Halfspaces: We show that majorities of halfspaces are hard to PAC-learn using any representation, based on the cryptographic assumption underlying the Ajtai-Dwork cryptosystem. This also implies a hardness result for learning halfspaces with a high rate of adversarial noise even if the learning algorithm can output any efficiently computable hypothesis. Max-Clique, Chromatic Number and Min-3Lin-Deletion: We prove an improved hardness of approximation result for two problems, namely, the problem of finding the size of the largest clique in a graph (also referred to as the Max-Clique problem) and the problem of finding the chromatic number of a graph. We show that for any constant γ > 0, there is no polynomial time algorithm that approximates these problems within factor n/2[superscript(log n)3/4+γ] in an n vertex graph, assuming NP is not contained in BPTIME(2[superscript(log n)O(1)]). This improves the hardness factor of n/2[superscript (log n)1-γ'] for some small (unspecified) constant γ' > 0 shown by Khot. Our main idea is to show an improved hardness result for the Min-3Lin-Deletion problem.
An instance of Min-3Lin-Deletion is a system of linear equations modulo 2, where each equation is over three variables. The objective is to find the minimum number of equations that need to be deleted so that the remaining system of equations has a satisfying assignment. We show a hardness factor of 2[superscript sqrt{log n}] for this problem, improving upon the hardness factor of (log n)[superscriptβ] shown by Hastad, for some small (unspecified) constant β > 0. The hardness results for Max-Clique and chromatic number are then obtained using the reduction from Min-3Lin-Deletion as given by Khot.
Monotone Multilinear Boolean Circuits for Bipartite Perfect Matching: A monotone Boolean circuit is said to be multilinear if for any AND gate in the circuit, the minimal representation of the two input functions to the gate do not have any variable in common. We show that monotone multilinear Boolean circuits for computing bipartite perfect matching require exponential size. In fact we prove a stronger result by characterizing the structure of the smallest monotone multilinear Boolean circuits for the problem.
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Hueso, González Jaime. "Analysis of wedge-shaped waveguides and design of multipactor-resistant microwave bandpass filters. Análisis de guías de onda en forma de cuña y diseño de filtros de microondas paso-banda resistentes al efecto multipactor." Doctoral thesis, Editorial Universitat Politècnica de València, 2013. http://hdl.handle.net/10251/33750.
Full textAbstract:
El efecto multipactor de ruptura en RF ha sido objeto de numerosos estudios desde
hace más de 80 años, a partir del desarrollo de los primeros aceleradores de partículas en
la primera mitad del siglo XX. A mediados de ese siglo, con el desarrollo de fuentes de alta
potencia para aplicaciones radar y la llegada de los satélites artificiales, la investigación del
multipactor cobró una considerable relevancia, al convertirse este fenómeno en un riesgo
determinante para costosos proyectos comerciales. Las guías de onda con secciones rectas
canónicas, como las rectangulares o las coaxiales, han sido tradicionalmente las más utilizadas
en dispositivos de microondas. Sus principales ventajas son que sus campos electromagnéticos pueden resolverse analíticamente, lo que permite su aplicación directa en diseños
complejos, y la simplicidad de su fabricación. Pero las capacidades de computación y las
prestaciones de los algoritmos se han multiplicado con los años, lo que ha permitido ampliar
el espectro de posibles topologías a geometrías casi arbitrarias, ofreciendo al diseñador una
mayor libertad creativa. En todo caso, gran parte de los dispositivos de microondas actuales
siguen confiando en la madurez y fiabilidad de las tecnologías de guía de onda tradicionales,
que no requieren una inversión adicional en equipos de fabricación. La supresión del efecto
multipactor es la motivación para arriesgarse a probar topologías de guía de onda innovadoras,
como la guía en forma de cuña.
Es en este contexto donde este trabajo de doctorado pretende ofrecer una contribuci'on.
En primer lugar, se ha desarrollado un modelo numérico para predecir el efecto multipactor
de ruptura en guías de onda huecas en forma de cuña. Esta herramienta ha permitido la
identificación de criterios óptimos de diseño. Así mismo, se ha adaptado un método de
síntesis de filtros paso-banda en guía rectangular para poder realizar un diseño similar pero
basado en la nueva topología. Como culminación, las estructuras diseñadas se han fabricado
y medido, con el fin de comprobar sus prestaciones electromagnéticas y su sensibilidad al
efecto multipactor. Se ha registrado además una patente para proteger estos nuevos filtros.
En resumen, el trabajo ha abarcado el ciclo de actividades relacionadas con el desarrollo
industrial completo de un dispositivo pasivo de microondas: investigación básica, análisis,
diseño, fabricación y calificación con medidas en el laboratorio.
Estas medidas han comprobado la mejora prevista en los umbrales de multipactor de los
filtros de microondas con topología en forma de cu¿na, y han confirmado que pueden ofrecer
respuestas en frecuencia similares a aquellas de filtros basados en una guía de onda rectangular
equivalente. Las implicaciones de los resultados han sido evaluadas a fondo y resumidas en este documento. Como observación final, se ha intentado redactar esta investigación de
manera que refleje el proceso natural de aprendizaje, mostrando los aciertos y errores experimentados
en el camino, todos los cuales han conducido al resultado final. Este reto no
hubiera sido posible sin el apoyo y compromiso de varios profesionales de diferentes centros
de investigación e industrias europeas (Universidad Politécnica de Valencia, Universidad de
Valencia, Agencia Espacial Europea, Thales Alenia Espacio Espa¿na, Technische Universit¿at
Darmstadt, 'Ecole Polythecnique F'ed'erale de Lausanne, Tesat, Aurora Software and Testing
y Val Space Consortium), a los cuales estoy agradecido.The multipactor RF breakdown effect has been object of numerous studies for over 80 years, since the development of the first particle accelerators in the beginning of the 20th century. Around the middle of that century, with the development of high power sources for radar applications and with the emergence of the artificial satellites, a new impulse was given to the multipactor research, since it became a risk for expensive commercial projects. Traditionally, waveguides with canonical cross sections, like rectangular or coaxial ones, have been the building blocks of most microwave devices. Their main advantages are that their electromagnetic fields can be solved analytically, enabling their direct application in complex designs, as well as their manufacturing simplicity. But over the years the computation capabilities and algorithms have continuously evolved, which has broadened the spectrum of possible topologies to almost arbitrary geometries, offering the designer more room for creativity. However, most of the current microwave devices still trust on the mature canonical waveguide technologies, which do not require an additional investment in manufacturing equipment. The suppression of the multipactor effect is the motivation for considering an innovative waveguide topology, like the wedge-shaped waveguide. It is within this context where this PhD work aims to offer a contribution. On the one hand, a numerical model for predicting the multipactor breakdown effect in wedge-shaped hollow waveguides has been developed. This tool has aided in the derivation of optimised design criteria. On the other hand, a bandpass filter synthesis method for rectangular waveguide has been adapted in order to calculate a similar design based on the new topology. As a culmination, the designed structures have been manufactured and tested, in order to verify their electromagnetic performance and their multipactor sensibility. A patent was also filed to protect these new filters. In short, this work has comprised the cycle of activities related to the whole industrial development of a passive microwave device: basic research, analysis, design, manufacturing and qualification through testing. These measurements have verified the predicted improvement in the multipactor thresholds of microwave filters with wedge-shaped topology, and have confirmed that they can offer similar frequency responses to the equivalent rectangular waveguide ones. The implications of the results have been thoroughly evaluated and summarised in this document. As a final remark, this research document has been drafted to reflect the natural learning process, and to show the rights and wrongs experienced in the way, which all have led to the final result. Such an endeavour would not have been possible without the support and commitment of several professionals from different European research centres and industries (Universidad Polit'ecnica de Valencia, Universidad de Valencia, European Space Agency, Thales Alenia Espacio Spain, Technische Universit¿at Darmstadt, 'Ecole Polythecnique F'ed'erale de Lausanne, Tesat, Aurora Software and Testing and Val Space Consortium), for which I am grateful.
Hueso González, J. (2013). Analysis of wedge-shaped waveguides and design of multipactor-resistant microwave bandpass filters. Análisis de guías de onda en forma de cuña y diseño de filtros de microondas paso-banda resistentes al efecto multipactor [Tesis doctoral]. Editorial Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33750
Alfresco
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Arpin, Louis. "Conception et intégration d'une architecture numérique pour l'ASIC LabPET[indice supérieur TM] II, un circuit de lecture d'une matrice de détection TEP de 64 pixels." Mémoire, Université de Sherbrooke, 2012. http://hdl.handle.net/11143/6148.
Full textAbstract:
Des développements technologiques récents concernant les photodiodes à effet avalanche (PDA) ont mené à la conception et la fabrication d'un tout nouveau module de détection de radiation TEP (tomographie d'émission par positrons) destiné à l'imagerie moléculaire préclinique. Il est basé sur une matrice de 8 par 8 scintillateurs LYSO (ortho-silicate de lutétium dopé au cérium, cerium-doped lutetium yttrium orthosilicate ) individuellement couplés aux pixels de deux matrices monolithiques de 4 par 8 PDA. Cette avancée, pouvant amener la résolution spatiale d'un scanner à passer sous la barrière du mm, exige la conception d'un tout nouveau système d'acquisition de données. En effet, il faut adapter le système de lecture individuelle de chacun des pixels du bloc de détection de façon à satisfaire la multiplication par ~8, relativement à une version antérieure (le LabPET[indice supérieur TM] I), de la densité de pixels du futur scanner LabPET[indice supérieur TM] II. Conséquemment, le traitement de signal numérique ne peut être exclusivement embarqué dans les matrices de portes logiques programmable (field-programmable gate array , FPGA) du système d'acquisition, en considérant les aspects monétaires, d'espace occupé et de puissance consommée de l'ensemble du projet LabPET[indice supérieur TM] II. De façon à s'adapter à cette nouvelle réalité, un nouveau circuit intégré à application spécifique (application specific integrated circuit, ASIC) à signaux mixtes avec 64 canaux d'acquisition, fabriqué avec la technologie TSMC CMOS 0,18 [micromètre], a été conçu. L'ASIC utilise la méthode de temps au-dessus d'un seuil (time over threshold , ToT), déjà implantée dans des applications de physique des hautes-énergies, de manière à extraire numériquement l'information relative à un rayonnement interagissant avec la matrice de détection (l'énergie, le temps et le numéro de pixel de l'événement). Dans le cadre de ce projet, une architecture complexe de machines à états-finis, cadencée par une horloge de 100 MHz, a été implantée et elle permet à l'ASIC d'identifier le taux anticipé de 3 000 événements par seconde par canal. Ceci est réalisé en calculant en temps réel le paramètre ToT tout en assurant la calibration adéquate de chacune des chaînes d'acquisition. Le circuit intégré peut caractériser jusqu'à 2 Mévénements/s malgré son unique lien différentiel à bas voltage (low-voltage differential signaling, LVDS) de transfert de données et consomme environ 600 mW. L'ASIC a été développé en suivant un processus de conception de circuits intégrés à signaux mixtes. Il permet notamment de minimiser et de vérifier l'impact des indésirables effets parasites sur la circuiterie analogique et numérique de l'ensemble avant que les dessins de masques ne soient envoyés vers la fonderie pour fabriquer le circuit désiré.
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Teichmann, Jürgen. "Untersuchung allgemeiner Eigenschaften, Optimierung und integrierte Realisierung logischer Schaltungen mit hystereseförmiger Übertragungskennlinie." Doctoral thesis, Universitätsbibliothek Chemnitz, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-132705.
Full textAbstract:
Zur Verbesserung der Störsicherheit bei der digitalen Signalübertragung wird eine Hysterese in die Übertragungskennlinie des Gatters eingefügt. Der Einfluss der Höhe der beiden Schwellwerte auf die Anzahl der auftretenden Fehler wird mittels eines Rechnerprogrammes untersucht. Ein Zufallsgenerator erzeugt Signale in verschiedenen Höhen und Breiten, die sich den ungestörten Signalen überlagern. Es erfolgt eine Umsetzung einer integrierten Schaltung auf einem TTL Master. Die Schaltung wird mittels eines eigens entwickelten Netzwerkanalyseprgrammes berechnet. Messergebnisse werden mitgeteiltTo enhance the noise immunity of digital signal transmission, a hysteresis is introduced to the transfer characteristic of integrated digital circuit. The influence of height of the two threshold values to the number of occurring errors is examined by a computer program. A random number generator generates signals of different heights and widths, which are superimposed on the undisturbed signals. There is an implementation of an integrated circuit on a TTL master. The DC performane is calculated by means of a specially developed circuit analysis program. Measurement results are presented
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Gillardin, Gérard. "Mise au point d'un appareillage de photoluminescence a haute resolution spatiale : application a l'etude des semiconducteurs et dispositifs electroniques iii-v." Clermont-Ferrand 2, 1988. http://www.theses.fr/1988CLF2D216.
Full textAbstract:
Description du dispositif permettant d'analyser des plaques de 2**(") de diametre a 1ok, avec de hautes resolutions laterales (20 et 1mu m), eventuellement a diverses energies. Realisation de cartographies a 300 et 10k: tres bonne correlation entre intensite de photoluminescence et defauts cristallins et chimiques; correspondance avec des mesures de resistivite electrique. Mise au point d'une procedure de qualification de l'homogeneite microscopique de gaas semi-isolant. Possibilite de prevoir la dispersion des tensions de seuil de transistors fet d'apres l'analyse du support de defaut, donc de classer et choisir les supports pour la realisation de circuits integres
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Platt, John C. "Sequential Threshold Circuits." Thesis, 1985. https://thesis.library.caltech.edu/6915/1/Platt_jc_1985.pdf.
Full text
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Hsieh, Chung-Han, and 謝宗翰. "Multi-Channel-Length Sub-Threshold CMOS Circuits." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/51703095557966187636.
Full textAbstract:
碩士國立中正大學
電機工程研究所
99
There are more special process procedure in nano era which changed the characteristic of semiconductor. The performance and energy consumption will get lost once designer still keep the same design technique without process consideration. A special byproduct called reverse short-channel-effect (RSCE) which can improve the circuit performance is involved. This paper will explore the circuit performance by utilizing TSMC 65 nm process. At present, foundry didn’t provide the special model for sub-threshold circuit design application. It is difficult to design a sub-threshold circuit due to the leakage at the sub-threshold operation. This paper will focus on the nanometer technology circuit design at sub-threshold operation. And design the standard cell library and flip-flops with reverse short-channel-effect (RSCE). This paper is also describe a device size optimization which be considered for sub-threshold operation. Experiment results using ISCAS’2003 benchmarks and fabricated in TSMC 65nm CMOS technology show that the critical path delay, power consumption.
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Tsai, Chen-Kuan, and 蔡正寬. "Static Timing Analysis for Threshold Logic Circuits." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/33554396451504851155.
Full textAbstract:
碩士國立清華大學
資訊工程學系
100
Threshold logic has been known as an alternative representation of Boolean logic due to its compactness characteristic. Recently, the developments in advanced nanotechnologies have also promised efficient implementations of threshold logic gates. Thus, many synthesis methodologies for threshold logic circuits have been proposed. On the other hand, the delay models of threshold logic gates accompanied with their implementation development have also been proposed. However, there has not been a timing analysis algorithm for threshold logic circuits to the best of our knowledge. Since threshold logic has a different mechanism in functional evaluation compared to the traditional Boolean logic, a threshold logic gate can represent a more complex function. As a result, the path sensitization criterion for criticality analysis in threshold logic circuits is also different. In this work, we propose a path sensitization criterion for threshold logic circuits, and develop a static timing analysis algorithm. The experimental results show the accuracy and efficiency of the proposed algorithm compared to the dynamic simulation approach for a set of MCNC and IWLS 2005 benchmarks.
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Lin, Yu-Yun, and 林郁芸. "Design Automation for Sub-Threshold Operational Amplifier Circuits." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/80723540973249436258.
Full textAbstract:
碩士國立中央大學
電機工程學系
105
Power has become the primary design constraint for chip designers today. To reduce power and increase service time, low-voltage low-power design becomes more and more important. One of the possible ways to achieve this goal is sub-threshold circuit design. By operating transistors at the region that Vdd is less than the transistor threshold voltage (Vdd
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"Testing of threshold logic latch based hybrid circuits." Master's thesis, 2013. http://hdl.handle.net/2286/R.I.20796.
Full textAbstract:
abstract: The advent of threshold logic simplifies the traditional Boolean logic to the single level multi-input function. Threshold logic latch (TLL), among implementations of threshold logic, is functionally equivalent to a multi-input function with an edge triggered flip-flop, which stands out to improve area and both dynamic and leakage power consumption, providing an appropriate design alternative. Accordingly, the TLL standard cell library is designed. Through technology mapping, hybrid circuit is generated by absorbing the logic cone backward from each flip-flip to get the smallest remaining feeder. With the scan test methodology adopted, design for testability (DFT) is proposed, including scan element design and scan chain insertion. Test synthesis flow is then introduced, according to the Cadence tool, RTL compiler. Test application is the process of applying vectors and the response analysis, which is mainly about the testbench design. A parameterized generic self-checking Verilog testbench is designed for static fault detection. Test development refers to the fault modeling, and test generation. Firstly, functional truth table test generation on TLL cells is proposed. Before the truth table test of the threshold function, the dependence of sequence of vectors applied, i.e., the dependence of current state on the previous state, should be eliminated. Transition test (dynamic pattern) on all weak inputs is proved to be able to test the reset function, which is supposed to erase the history in the reset phase before every evaluation phase. Remaining vectors in the truth table except the weak inputs are then applied statically (static pattern). Secondly, dynamic patterns for all weak inputs are proposed to detect structural transistor level faults analyzed in the TLL cell, with single fault assumption and stuck-at faults, stuck-on faults, and stuck-open faults under consideration. Containing those patterns, the functional test covers all testable structural faults inside the TLL. Thirdly, with the scope of the whole hybrid netlist, the procedure of test generation is proposed with three steps: scan chain test; test of feeders and other scan elements except TLLs; functional pattern test of TLL cells. Implementation of this procedure is discussed in the automatic test pattern generation (ATPG) chapter.Dissertation/Thesis
M.S. Electrical Engineering 2013
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"Modeling and Implementation of Threshold Logic Circuits and Architectures." Doctoral diss., 2010. http://hdl.handle.net/2286/R.I.8637.
Full textAbstract:
abstract: Threshold logic has long been studied as a means of achieving higher performance and lower power dissipation, providing improvements by condensing simple logic gates into more complex primitives, effectively reducing gate count, pipeline depth, and number of interconnects. This work proposes a new physical implementation of threshold logic, the threshold logic latch (TLL), which overcomes the difficulties observed in previous work, particularly with respect to gate reliability in the presence of noise and process variations. Simple but effective models were created to assess the delay, power, and noise margin of TLL gates for the purpose of determining the physical parameters and assignment of input signals that achieves the lowest delay subject to constraints on power and reliability. From these models, an optimized library of standard TLL cells was developed to supplement a commercial library of static CMOS gates. The new cells were then demonstrated on a number of automatically synthesized, placed, and routed designs. A two-stage 2's complement integer multiplier designed with CMOS and TLL gates utilized 19.5% less area, 28.0% less active power, and 61.5% less leakage power than an equivalent design with the same performance using only static CMOS gates. Additionally, a two-stage 32-instruction 4-way issue queue designed with CMOS and TLL gates utilized 30.6% less area, 31.0% less active power, and 58.9% less leakage power than an equivalent design with the same performance using only static CMOS gates.Dissertation/Thesis
Ph.D. Computer Science 2010
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Kuo, Pin-Yi, and 郭品宜. "On Rewiring and Simplification for Canonicity in Threshold Logic Circuits." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/24438379402320702667.
Full textAbstract:
碩士國立清華大學
資訊工程學系
99
重接線已高度發展並廣泛地被運用在傳統布林邏輯設計上的合成與最佳化；臨界邏輯，相較於布林邏輯擁有較精簡的特性，是一種新的邏輯表示方式。現今，伴隨著奈米材料技術的演進，臨界邏輯上的研究，包含多層合成、驗證與測試，皆蓬勃發展。這篇論文提出了一個實作在臨界邏輯電路的重接線演算法，藉由移除一個目標線，並加上相對應的改正網路來修正電路的功能性；同時使一個臨界邏輯閘以標準型態表示的簡化程序也被提出，標準表示也是功能性驗證的一重要性質。實驗結果展現了此演算法實作在臨界邏輯電路上的邏輯重建能力；除此之外，在合成一個具有新輸入端數目限制的臨界網路，相較於最先進的臨界邏輯合成演算法，我們提出的方法加快了7.1倍的速度。
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Celinski, Peter. "Threshold logic based implementation of high performance VLSI arithmetic circuits." Thesis, 2006. http://hdl.handle.net/2440/122095.
Full textAbstract:
This Thesis focuses on the area of high speed very large scale integration (VLSI) complementary metal oxide semiconductor (CMOS) circuit design using threshold logic (TL) techniques. The work described in this document contributes three major advances on high speed TL based CMOS circuit design: (i) the development and experimental verification of novel high speed TL gate circuit topologies; (ii) a method for delay modelling of sense-amplifier based TL gates and (iii) novel TL based networks for the implementation of high speed arithmetic circuits. In this Thesis, the basics and previous work in threshold logic are reviewed, including theoretical results for TL based networks used in arithmetic and TL gate circuit design techniques. Novel floating gate based TL circuit implementations based on precharged sense-amplifiers employing charge recycyling are described and experimentally verified. A new weight-shared circuit technique is proposed which significantly reduces the area cost. Based on the theory of Logical Effort, a model for the Charge Recycling Threshold Logic (CRTL) gate is developed and experimentally verified. This model is used to evaluate and compare a number of CRTL based circuits, demonstrating its significant reduced delay compared to conventional static and dynamic CMOS logic. New parallel counters are proposed and partial product reduction trees based on these counters for use in parallel multipliers are shown to be significantly faster than previously published schemes. The 64-bit prefix-8 adder presented here is the fastest 64-bit adder published to date. The contributions in this Thesis are an important step towards alleviating the issues faced in present day VLSI arithmetic design and demonstrate for the first time the significant benefits offered by TL compared to conventional logic circuit techniques. The methodologies introduced are shown to lead to increased circuit compactness and reduced power dissipation which are of particular interest for future smart sensor technology and will potentially impact on future portable electronics systems for a range of applications from mobile personal communications through to aerospace systems.Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2007
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Zangeneh, Mahmoud. "Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors." Thesis, 2015. https://hdl.handle.net/2144/16096.
Full textAbstract:
The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2- and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based RRAM array consumes the least write energy (4.06 pJ/bit) and read energy (188 fJ/bit) when storing 3 bits/cell for 100 nsec write and 1 nsec read access times. Similarly, HfOx-based RRAM array consumes the least write energy (365 fJ/bit) and read energy (173 fJ/bit) when storing 3 bits/cell for 1 nsec write and 200 nsec read access times.
On the logic side, we investigate the use of equalization techniques to improve the energy efficiency of digital sequential logic circuits in sub-threshold regime. We first propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors in digital logic designed in sub-threshold regime. This mitigation of timing errors can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path in a combinational logic block using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% (on average) in the sub-threshold regime. Overall, the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. We also propose a tunable adaptive feedback equalizer circuit that can be used with sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in sub-threshold digital logic circuits. For a 64-bit adder designed in 130 nm our proposed approach can reduce the normalized delay variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. In addition, we present detailed energy-performance models of the adaptive feedback equalizer circuit. This work serves as a foundation for the design of robust, energy-efficient digital logic circuits in sub-threshold regime.
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Krebs, Andreas [Verfasser]. "Typed semigroups, majority logic, and threshold circuits / vorgelegt von Andreas Krebs." 2008. http://d-nb.info/991466683/34.
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