Dissertations / Theses: 'Thin Film Transistors (TFT)'

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Hein, Moritz. "Organic Thin-Film Transistors." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-167894.

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Organic thin ﬁlm transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These beneﬁts are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric ﬁeld-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identiﬁed as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and signiﬁcantly alleviating the bias-stress eﬀect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.

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Dong, Hanpeng. "Microcrystalline silicon based thin film transistors fabricated on flexible substrate." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S173/document.

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Le travail de cette thèse porte sur le développement de transistors en couche mince (Thin Film Transistors, TFTs) à base de silicium microcristallin fabriqués sur un substrat flexible à très basse température (T< 180 °C). La première partie de ce travail a consisté à étudier la stabilité électrique de ces TFTs. L'étude de la stabilité électrique des TFTs de type N fabriqués sur verre a montré que ces TFTs sont assez stables, la tension de seuil VTH ne se décale que de 1.2 V au bout de 4 heures de stress sous une tension de grille VGSstress= +50V et à une température T=50 °C. L'instabilité électrique de ces TFTs est principalement causée par le piégeage des porteurs dans l'isolant de grille. La deuxième étape de ce travail s'est concentrée sur l'étude du comportement de ces TFTs sous déformation mécanique. Ces TFTs sont soumis à un stress mécanique en tension et en compression. Le rayon de courbure minimum que les TFTs pouvaient supporter est r=1.5 mm en tension et en compression. La limitation de la déformation mécanique de ces TFTs est principalement due à la contrainte mécanique du nitrure de silicium utilisé comme isolant de grille des TFTs. Autrement dit, ces TFTs sont mécaniquement fiables et présentes une faible variation du courant ION, de l'ordre de 1%, même après 200 cycles de déformation mécanique. Ces résultats obtenus laissent entrevoir la possibilité de concevoir une électronique flexible pouvant être pliée en 2. Enfin, les TFTs sont fabriqués avec différents isolants de grille afin d'augmenter la mobilité d'effet de champ. Malheureusement, aucun isolant de grille utilisé dans ces études n'a permis d'augmenter la mobilité d'effet de champ sans dégrader la stabilité électrique des TFTs. Des études plus détaillées et des optimisations complémentaires sur ces isolants de grille sont nécessaires
This work deals with the development of microcrystalline silicon thin film transistors (TFTs) fabricated on flexible substrate at low temperature (T=180 °C). The first step of this work consists in studying the electrical stability of TFTs. The N-type TFTs fabricated on glass substrate are electrically stable under gate bias stress VGStress= +50V at T=50 °C. The threshold voltage shift (ΔVTH) was only 1.2 V during 4 hours. This electrical instability of TFTs is mainly due to carrier trapping inside the silicon nitride gate insulator. The second step of this work lies in the study of the mechanical behavior of the TFTs. Both tensile and compressive strains were applied on TFTs. The minimum curvature radius is r=1.5 mm for both tension and compression. The main limitation of TFTs comes from the mechanical strain εlimit of silicon nitride used as gate insulator of TFTs. Also, these TFTs are mechanically reliable: the variation of ION current was only 1% after 200 cycles mechanical bending. These results obtained open the way to the development of flexible electronics that can be folded in half.Finally, TFTs have been fabricated using different gate insulators in order to improve the mobility. Unfortunately, all the gate insulators used couldn’t improve mobility without sacrificing electrical stability of TFT. More detailed studies and complementary optimization of these gate insulators are necessary

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Ho, Tsz Kin. "Design of TFT circuit and touchscreen electronics /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20HO.

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Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device." Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.

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n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.

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Rossi, Leonardo. "Flexible oxide thin film transistors: fabrication and photoresponse." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/14542/.

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Gli ossidi amorfi semiconduttori (AOS) sono nuovi candidati per l’elettronica flessibile e su grandi aree: grazie ai loro legami prevalentemente ionici hanno una mobilità relativamente alta (µ > 10cm^2/Vs) anche nella fase amorfa. Transistor a film sottile (TFT) basati sugli AOS saranno quindi più performanti di tecnologie a base di a-Si e più economici di quelle a base di silicio policristallino. Essendo amorfi, possono essere depositati a basse temperature e su substrati polimerici, caratteristica chiave per l’elettronica flessibile e su grandi aree. Per questa tesi, diversi TFT sono stati fabbricati e caratterizzati nei laboratori del CENIMAT all’Università Nova di Lisbona sotto la supervisione del Prof. P. Barquinha. Questi dispositivi sono composti di contatti in molibdeno, un canale semiconduttivo di ossido di zinco, gallio e indio (IGZO) e un dielettrico composto da 7 strati alternati di SiO2 e SiO2+Ta2O5. Tutti i dispositivi sono stati depositati mediante sputtering su sostrati flessibili (fogli di PEN). Le misure tensione-corrente mostrano che i dispositivi mantengono alte mobilità (decine di 10cm^2/Vs) anche quando fabbricati a temperature inferiori a 200°C. Si è analizzato il funzionamento dei dispositivi come fototransistor rilevando la risposta alla luce ultravioletta e in particolare la loro responsività e spostamento della tensione di soglia in funzione della lunghezza d’onda incidente. Questi risultati consentono di formulare ipotesi sul comportamento dei dispositivi alla scala microscopica. In particolare, indicano che i) la mobilità del canale non è influenzata dall’illuminazione, ii) sia l'IGZO sia il Ta2O5 contribuiscono al processo di fotoconduttività e iii) il processo di fotogenerazione non è adiabatico. La tesi contiene inoltre una descrizione del processo di ricombinazione e presenta un’applicazione pratica di tali dispositivi in un circuito per RFID. Infine, esplora la possibilità di migliorarne la flessibilità e le prestazioni.

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Fratelli, Ilaria. "Flexible oxide thin film transistors: device fabrication and kelvin probe force microscopy analysis." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/13538/.

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I transistor a film sottile basati su ossidi amorfi semiconduttori sono ottimi candidati nell'ambito dell'elettronica su larga scala. Al contrario delle tecnologie basate su a-Si:H a poly-Si, gli AOS presentano un'elevata mobilità elettrica (m > 10 cm^2/ Vs) nonostante la struttura amorfa. Inoltre, la possibilità di depositare AOS a basse temperature e su substrati polimerici, permette il loro impiego nel campo dell'elettronica flessibile. Al fine di migliorare questa tecnologia, numerosi TFT basati su AOS sono stati fabbricati durante 4 mesi di attività all'Università Nova di Lisbona. Tutti i transistor presentano un canale formato da a-GIZO, mentre il dielettrico è stato realizzato con due materiali differenti: Parylene (organico) e 7 strati alternati di SiO2 e SiO2 + Ta2O5. I dispositivi sono stati realizzati su substrati flessibili sviluppando una nuova tecnica per la laminazione e la delaminazione di fogli di PEN su supporto rigido. L'ottimizzazione del processo di fabbricazione ha permesso la realizzazione di dispositivi che presentano caratteristiche paragonabili a quelle previste per TFT costruiti su substrati rigidi (m = 35.7 cm^2/Vs; VON = -0.10 V; S = 0.084 V/dec). Al Dipartimento di Fisica dell'UNIBO, l'utilizzo del KPFM ha permesso lo studio a livello microscopico delle prestazioni presentate dai dispositivi analizzati. Grazie a questa tecnica di indagine, è stato possibile analizzare l'impatto delle resistenze di contatto sui dispositivi meno performanti e identificare l'esistenza di cariche intrappolate nei TFT basati su Parylene. Gli ottimi risultati ottenuti dall'analisi KPFM suggeriscono un futuro impiego di questa tecnica per lo studio del legame tra stress meccanico e degradazione elettrica dei dispositivi. Infatti, la comprensione dei fenomeni microscopici dovuti alla deformazione strutturale sarà un passaggio indispensabile per lo sviluppo dell'elettronica flessibile.

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Jakob, Markus Prüfer. "Compact DC Modelling of Short-Channel Effects in Organic Thin-Film Transistors." Doctoral thesis, Universitat Rovira i Virgili, 2022. http://hdl.handle.net/10803/673905.

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Els transistors orgànics de capa fina (TFT) són dispositius prometedors per a les pantalles flexibles de matriu activa i els conjunts de sensors, ja que poden fabricar-se a temperatures de procés relativament baixes i, per tant, no sols en vidre, sinó també en substrats polimèrics. Per a millorar el rendiment dinàmic dels dispositius i circuits TFT , una reducció agressiva de la longitud de canal provoca efectes extrínsecs en els dispositius que han de ser capturats per models compactes. Aquesta tesi presenta models analítics, basats en la física, de la degradació de la pendent subumbral, el roll-off del voltatge llindar i l'efecte DIBL en TFTs coplanars i escalonats que poden ser implementats en qualsevol model compacte de corrent continu arbitrari que estigui definit pel voltatge llindar i la pendent subumbral. Per tant, l'equació diferencial de Laplace es resol per a la geometria coplanar i escalonada aplicant la transformación Schwarz-Cristoffel. Les solucions del potencial serveixen de base per a la definició de les equacions del model. A més, es desenvolupen models compactes de les barreres Schottky dependents de la polarització en les interfícies font/semiconductor i drenador/semiconductor en els TFT coplanars i escalonats, que modelen la injecció i l'ejecció de portadors de càrrega, respectivament, com a corrent d'emissió termoiònica.
Los transistores orgánicos de capa fina (TFT) son dispositivos prometedores para las pantallas flexibles de matriz activa y los conjuntos de sensores, ya que pueden fabricarse a temperaturas de proceso relativamente bajas y, por tanto, no sólo en vidrio, sino también en sustratos poliméricos. Para mejorar el rendimiento dinámico de los dispositivos y circuitos TFT, una reducción agresiva de la longitud de los canales provoca efectos extrínsecos en los dispositivos que tienen que ser capturados por modelos compactos. Esta tesis presenta modelos analíticos, basados en la física, de la degradación de la pendiente subumbral, el roll-off del voltaje umbral y el efecto DIBL en TFTs coplanares y escalonados que pueden ser implementados en cualquier modelo compacto de corriente continua arbitrario que esté definido por el voltaje umbral y la pendiente subumbral. Por lo tanto, la ecuación diferencial de Laplace se resuelve para la geometría coplanar y escalonada aplicando la transformación Schwarz-Christoffel. Las soluciones del potencial sirven de base para la definición de las ecuaciones del modelo. Además, se desarrollan modelos compactos de las barreras Schottky dependientes de la polarización en las interfaces fuente/semiconductor y drenador/semiconductor en los TFT coplanares y escalonados, que modelan la inyección y la eyección de portadores de carga, respectivamente, como corriente de emisión termoiónica
Organic thin-film transistors (TFTs) are promising devices for flexible active-matrix displays and sensor arrays, since they can be fabricated at relatively low process temperatures and thus not only on glass, but also on polymeric substrates. In order to improve the dynamic TFT and circuit performance, an aggressive reduction of the channel length causes extrinsic de-vice effects that have to be captured by compact models. This dissertation presents analytical, physics-based models of the subthreshold-swing degra-dation, the thresholdvoltage roll-off and DIBL effects in coplanar and staggered TFTs that can be implemented in any arbitrary compact dc model that are defined by the threshold voltage and the subthreshold swing. Therefore, Laplace’s differential equation is solved for the coplanar and staggered geometry by applying the Schwarz-Christoffel transformation. The potential solutions serve as a basis for the definition of the model equations. Further-more, compact models of the biasdependent Schottky barriers at the source/semiconductor and drain/semiconductor interfaces in coplanar and staggered TFTs are derived, which model the charge carriers injection and ejection, respectively, as thermionic emission cur-rent. Thereby, in case of the source barrier, the Schottky barrier lowering effect due to im-age charges is captured and therefore, an analytical expression of the electric field at the source barrier is derived.

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Dosev, Dosi Konstantinov. "Fabrication, characterisation and modelling of nanocrystalline silicon thin-film transistors obtained by hot-wire chemical vapour deposition." Doctoral thesis, Universitat Politècnica de Catalunya, 2003. http://hdl.handle.net/10803/6324.

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Hot-wire chemical vapour deposition (HWCVD) is a promising technique that permits polycrystalline silicon films with grain size of nanometers to be obtained at high deposition rates and low substrate temperatures. This material is expected to have better electronic properties than the commonly used amorphous hydrogenated silicon (a-Si:H).

In this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.

The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.

The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.
Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions.

The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.
We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.

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Noring, Martin. "To automatically estimate the surface area coverage of carbon nanotubes on thin film transistors with image analysis : Bachelor’s degree project report." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-157168.

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This report discuss the developement of a MATLAB-based tool for the analysis ofsurface area coverage of carbon nanotube networks from atomic force microscopyimages. The tool was compared with a manual method and the conclusion was that ithas, at least, the same accuracy as the manual mehtod, and it needs much less time forthe analysis. The tool couldn’t analyze images of carbon nanotube networks if theimages were to noisy or the networks to dense. The tool can help in the research ofthin-film transistors with carbon nanotube networks as the semiconducting channelmaterial.

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Zhu, Lei. "Modeling of a-Si:H TFT I-V Characteristics in the Forward Subthreshold Operation." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/868.

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The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

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Elzwawi, Salim Ahmed Ali. "Cathodic Arc Zinc Oxide for Active Electronic Devices." Thesis, University of Canterbury. Electrical and Computer Engineering, 2015. http://hdl.handle.net/10092/10852.

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The filtered cathodic vacuum arc (FCVA) technique is a well established deposition method for wear resistant mechanical coatings. More recently, this method has attracted attention for growing ZnO based transparent conducting films. However, the potential of FCVA deposition to prepare ZnO layers for electronic devices is largely unexplored. This thesis addresses the use of FCVA deposition for the fabrication of active ZnO based electronic devices. The structural, electrical and optical characteristics of unintentionally doped ZnO films grown on different sapphire substrates were systematically investigated. The potential of FCVA to grow both polar and non-polar ZnO films was demonstrated. The resulting films showed considerable promise for device applications with properties including high transparency(> 90%), moderate intrinsic carrier concentrations (10¹⁷ - 10¹⁹ cm⁻³), electron mobilities up to 110 cm⁻²/Vs, low surface roughness (< 5 nm) and well-structured photoluminescence. Post-growth annealing in oxygen at temperatures up to 800 C produced significant improvements in the electronic and optical properties of these films, due to the formation of larger grains with lower inter-grain potential barriers. Silver oxide (AgOᵪ ) and iridium oxide (IrOᵪ) Schottky diodes fabricated on annealed FCVA ZnO films showed ideality factors as low as 1.20, barrier heights up to 0.85 eV and high sensitivity to ultraviolet light (up to ̴ 10⁻⁵ at -2 V). Transparent and opaque MESFETs fabricated on these films showed well defined field effect characteristics, channel mobilities up to 70 cm⁻²/Vs and insensitivity to 1 mW/cm⁻² visible light. These devices were further subjected to extensive bias and temperature stress tests. MESFET stability appeared to be strongly dependent on Schottky gate type, bias conditions and ZnO film morphology. Positive bias stress of AgOᵪ gated devices resulted in irreversible damage, that is thought to be due to Ag electromigration across the gate interface. Mapping of the surface potential of the ZnO channel material with Kelvin probe force microscopy suggested a strong relationship between the defect density at grain boundaries and both channel mobility and current stability. Interval growth techniques were found to reduce the density of defects at grain boundaries and produced MESFETs with higher current stability. IrOᵪ gated devices showed superior bias stability and temperature resilience from 25 C-195 C.

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Ullah, Syed Shihab. "Solution Processing Electronics Using Si6 H12 Inks: Poly-Si TFTs and Co-Si MOS Capacitors." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/28902.

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The development of new materials and processes for electronic devices has been driven by the integrated circuit (IC) industry since the dawn of the computer era. After several decades of '"Moore's Law"-type innovation, future miniaturization may be slowed down by materials and processing limitations. By way of comparison, the nascent field of flexible electronics is not driven by the smallest possible circuit dimension, but instead by cost and form-factor where features typical of 1970s CMOS (i.e., channel length - IO ?m) will enable flexible electronic technologies such as RFID, e-paper, photovoltaics and health monitoring devices. In this thesis. cyclohexasilane is proposed and used as a key reagent in solution processing of poly-Si and Co-Si thin films with the former used as the active layer in thin film transistors (TFTs) and the latter as the gate metal in metal-oxide-semiconductor (MOS) capacitors. A work function of 4.356 eV was determined for the Co-Si thin films via capacitance-voltage (C-Y) characterization which differs slightly from that extracted from ultraviolet photoemission spectroscopy (UPS) data (i.e., 4.8 eV). Simulation showed the difference between the C-V and UPS-derived data may be attributed to the existence of 8.3 x 10 (exponent 10) cm-2 interface charge density in the oxide-semiconductor junction. Poly-Si TFTs prepared using Si6 H12-based inks maintained the following electrical attributes: field effect mobility of 0.1 cm2V-1s-1; threshold voltage of 66 V; and, an on/off ratio of 1630. A BSIM3 version 3 NFET model was modified through global parametric extraction procedure to match the transfer characteristics of the fabricated poly-Si TFT. It is anticipated that this model can be utilized for future design simulation for solution-processed poly-Si circuits.

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Grant, David James. "Bottom-Gate TFTs With Channel Layer Deposited by Pulsed PECVD." Thesis, University of Waterloo, 2004. http://hdl.handle.net/10012/805.

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Nanocrystalline silicon (nc-Si:H) is a promising material for Thin-Film Transistors (TFTs) offering potentially higher mobilities and improved stability over hydrogenated amorphous silicon (a-Si:H). The slow growth rate of nc-Si:H can be overcome by using pulsed Plasma-Enhanced Chemical Vapour Deposition (PECVD). Pulsed PECVD also reduces powder particle formation in the plasma and provides added degrees of freedom for process optimization. Unlike high frequency PECVD, pulsed PECVD can be scaled to deposit films over large areas with no reduction in performance. For this thesis, silicon thin films were deposited by the pulsed PECVD technique at a temperature of 150 °C and TFTs were made using this material. Radio Frequency (RF) power and silane (SiH₄) flow rate were varied in order to study the effect of different levels of crystallinity on the film. Raman spectroscopy, Atomic Force Microscope (AFM), X-Ray Diffraction (XRD), electrical conductivity, Hall mobility, optical band gap, and stability under light-soaking were measured using films of two different thicknesses, 50 nm and 300 nm. From the Raman data we see that the 50 nm films deposited with high hydrogen dilution are mostly amorphous, indicating the presence of a thick incubation layer. The 300nm samples deposited with hydrogen dilution, on the other hand, showed very high crystallinity and conductivity, except for 300-2 which was surprisingly, mostly amorphous. AFM and XRD measurements were also performed to confirm the Raman data and get an estimate for the crystallite grain size in the 300 nm samples. The conductivity was measured for all films, and the Hall mobility and carrier concentration was measured for one of the 300 nm films. The thin samples which are mostly amorphous show low conductivity whereas the thick high crystallinity films show high conductivity, and n-type behaviour possibly due to oxygen doping. The optical gap was also measured using Ultra Violet (UV) light and results indicate the possible presence of small crystallites in the 50 nm films. The conductivity's stability under light-soaking was measured to observe the material's susceptibility to degradation, and the 300 nm with high crystallinity were much more stable than the a-Si:H films. All the results of these measurements varied depending on the film and these results are discussed. Bottom-gate TFTs were fabricated using a pulsed PECVD channel layer and an amorphous silicon nitride (a-SiN:H) gate dielectric. The extracted parameters of one of the best TFTs are μ_sat ≤ 0. 38 cm² V^-1 s^-1, V_t,sat ≥ 7. 3 V, I_on/off > 10⁶, and S < 1 V/decade. These parameters were extracted semi-automatically from the basic Field-Effect Transistor (FET) model using a computer program. Extraction using a more complicated model yielded similar results for mobility and threshold voltage but also gave a large power parameter α of 2. 31 and conduction band tail slope of 30 meV. The TFT performance and material properties are presented and discussed. On this first attempt at fabricating TFTs using a nc-Si:H channel layer deposited by pulsed PECVD, results were obtained which are consistent with results for low temperature a-Si:H TFTs and previous pulsed PECVD TFTs. The channel layer was mostly amorphous and non-crystalline, possibly due to the amorphous substrate or insufficient hydrogen dilution in the plasma. The 300 nm films showed, however, that high crystallinity material deposited directly on glass can easily be obtained, and this material showed less degradation under light-soaking than the purely amorphous counterpart. Pulsed PECVD is a promising technique for the growth of nc-Si:H and with further materials development and process optimization for TFTs, it may prove to be useful for the growth of high-quality nc-Si:H TFT channel layers.

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14

Lindner, Thomas. "Organische Feldeffekt-Transistoren: Modellierung und Simulation." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2005. http://nbn-resolving.de/urn:nbn:de:swb:14-1116323078792-49660.

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Die vorliegende Arbeit befasst sich mit der Simulation und Modellierung organischer Feldeffekt-Transistoren (OFETs). Mittels numerischer Simulationen wurden detaillierte Untersuchungen zu mehreren Problemstellungen durchgeführt. So wurde der Einfluss einer exponentiellen Verteilung von Trapzuständen, entsprechend dem sogenannten a-Si- oder TFT-Modell, auf die Transistorkennlinien untersucht. Dieses Modell dient der Beschreibung von Dünnschicht-Transistoren mit amorphen Silizium als aktiver Schicht und wird teils auch für organische Transistoren als zutreffend angesehen. Dieser Sachverhalt wird jedoch erstmals in dieser Arbeit detailliert untersucht und simulierte Kennlinien mit gemessenen Kennlinien von OFETs verglichen. Insbesondere aufgrund der Dominanz von Hysterese-Effekten in experimentellen Kennlinien ist jedoch eine endgültige Aussage über die Gültigkeit des a-Si-Modells schwierig. Neben dem a-Si-Modell werden auch noch andere Modelle diskutiert, z.B. Hopping-Transport zwischen exponentiell verteilten lokalisierten Zuständen (Vissenberg, Matters). Diese Modelle liefern, abhängig von den zu wählenden Modellparametern, zum Teil ähnliche Abhängigkeiten. Möglicherweise müssen die zu wählenden Modellparameter selbst separat gemessen werden, um eindeutige Schlussfolgerungen über den zugrundeliegenden Transportmechanismus ziehen zu können. Unerwünschte Hysterese-Effekte treten dabei sowohl in Transistorkennlinien als auch in Kapazitäts-Spannungs- (CV-) Kennlinien organischer MOS-Kondensatoren auf. Diese Effekte sind bisher weder hinreichend experimentell charakterisiert noch von ihren Ursachen her verstanden. In der Literatur findet man Annahmen, dass die Umladung von Trapzuständen oder bewegliche Ionen ursächlich sein könnten. In einer umfangreichen Studie wurde daher der Einfluß von Trapzuständen auf quasistatische CV-Kennlinien organischer MOS-Kondensatoren untersucht und daraus resultierende Hysterese-Formen vorgestellt. Aus den Ergebnissen läßt sich schlussfolgern, dass allein die Umladung von Trapzuständen nicht Ursache für die experimentell beobachteten Hysteresen in organischen Bauelementen sein kann. Eine mögliche Erklärung für diese Hysterese-Effekte wird vorgeschlagen und diskutiert. In einem weiteren Teil der Arbeit wird im Detail die Arbeitsweise des source-gated Dünnschicht-Transistors (SGT) aufgezeigt, ein Transistortyp, welcher erst kürzlich in der Literatur eingeführt wurde. Dies geschieht am Beispiel eines Transistors auf der Basis von a-Si als aktiver Schicht, die Ergebnisse lassen sich jedoch analog auch auf organische Transistoren übertragen. Es wird geschlussfolgert, dass der SGT ein gewöhnlich betriebener Dünnschicht-Transistor ist, limitiert durch das Sourcegebiet mit großem Widerstand. Die detaillierte Untersuchung des SGT führt somit auf eine Beschreibung, die im Gegensatz zur ursprünglich verbal diskutierten Arbeitsweise steht. Ambipolare organische Feldeffekt-Transistoren sind ein weiterer Gegenstand der Arbeit. Bei der Beschreibung ambipolarer Transistoren vernachlässigen bisherige Modelle sowohl die Kontakteigenschaften als auch die Rekombination von Ladungsträgern. Beides wird hingegen in den vorgestellten numerischen Simulationen erstmalig berücksichtigt. Anhand eines Einschicht-Modellsystems wurde die grundlegende Arbeitsweise von ambipolaren (double-injection) OFETs untersucht. Es wird der entscheidende Einfluß der Kontakte sowie die Abhängigkeit gegenüber Variationen von Materialparametern geklärt. Sowohl der Kontakteinfluß als auch Rekombination sind entscheidend für die Arbeitsweise. Zusätzlich werden Möglichkeiten und Einschränkungen für die Datenanalyse mittels einfacher analytischer Ausdrücke aufgezeigt. Es zeigte sich, dass diese nicht immer zur Auswertung von Kennlinien herangezogen werden dürfen. Weiterhin werden erste Simulationsergebnisse eines ambipolaren organischen Heterostruktur-TFTs mit experimentellen Daten verglichen.

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15

Lindner, Thomas. "Organische Feldeffekt-Transistoren: Modellierung und Simulation." Doctoral thesis, Technische Universität Dresden, 2004. https://tud.qucosa.de/id/qucosa%3A24492.

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Die vorliegende Arbeit befasst sich mit der Simulation und Modellierung organischer Feldeffekt-Transistoren (OFETs). Mittels numerischer Simulationen wurden detaillierte Untersuchungen zu mehreren Problemstellungen durchgeführt. So wurde der Einfluss einer exponentiellen Verteilung von Trapzuständen, entsprechend dem sogenannten a-Si- oder TFT-Modell, auf die Transistorkennlinien untersucht. Dieses Modell dient der Beschreibung von Dünnschicht-Transistoren mit amorphen Silizium als aktiver Schicht und wird teils auch für organische Transistoren als zutreffend angesehen. Dieser Sachverhalt wird jedoch erstmals in dieser Arbeit detailliert untersucht und simulierte Kennlinien mit gemessenen Kennlinien von OFETs verglichen. Insbesondere aufgrund der Dominanz von Hysterese-Effekten in experimentellen Kennlinien ist jedoch eine endgültige Aussage über die Gültigkeit des a-Si-Modells schwierig. Neben dem a-Si-Modell werden auch noch andere Modelle diskutiert, z.B. Hopping-Transport zwischen exponentiell verteilten lokalisierten Zuständen (Vissenberg, Matters). Diese Modelle liefern, abhängig von den zu wählenden Modellparametern, zum Teil ähnliche Abhängigkeiten. Möglicherweise müssen die zu wählenden Modellparameter selbst separat gemessen werden, um eindeutige Schlussfolgerungen über den zugrundeliegenden Transportmechanismus ziehen zu können. Unerwünschte Hysterese-Effekte treten dabei sowohl in Transistorkennlinien als auch in Kapazitäts-Spannungs- (CV-) Kennlinien organischer MOS-Kondensatoren auf. Diese Effekte sind bisher weder hinreichend experimentell charakterisiert noch von ihren Ursachen her verstanden. In der Literatur findet man Annahmen, dass die Umladung von Trapzuständen oder bewegliche Ionen ursächlich sein könnten. In einer umfangreichen Studie wurde daher der Einfluß von Trapzuständen auf quasistatische CV-Kennlinien organischer MOS-Kondensatoren untersucht und daraus resultierende Hysterese-Formen vorgestellt. Aus den Ergebnissen läßt sich schlussfolgern, dass allein die Umladung von Trapzuständen nicht Ursache für die experimentell beobachteten Hysteresen in organischen Bauelementen sein kann. Eine mögliche Erklärung für diese Hysterese-Effekte wird vorgeschlagen und diskutiert. In einem weiteren Teil der Arbeit wird im Detail die Arbeitsweise des source-gated Dünnschicht-Transistors (SGT) aufgezeigt, ein Transistortyp, welcher erst kürzlich in der Literatur eingeführt wurde. Dies geschieht am Beispiel eines Transistors auf der Basis von a-Si als aktiver Schicht, die Ergebnisse lassen sich jedoch analog auch auf organische Transistoren übertragen. Es wird geschlussfolgert, dass der SGT ein gewöhnlich betriebener Dünnschicht-Transistor ist, limitiert durch das Sourcegebiet mit großem Widerstand. Die detaillierte Untersuchung des SGT führt somit auf eine Beschreibung, die im Gegensatz zur ursprünglich verbal diskutierten Arbeitsweise steht. Ambipolare organische Feldeffekt-Transistoren sind ein weiterer Gegenstand der Arbeit. Bei der Beschreibung ambipolarer Transistoren vernachlässigen bisherige Modelle sowohl die Kontakteigenschaften als auch die Rekombination von Ladungsträgern. Beides wird hingegen in den vorgestellten numerischen Simulationen erstmalig berücksichtigt. Anhand eines Einschicht-Modellsystems wurde die grundlegende Arbeitsweise von ambipolaren (double-injection) OFETs untersucht. Es wird der entscheidende Einfluß der Kontakte sowie die Abhängigkeit gegenüber Variationen von Materialparametern geklärt. Sowohl der Kontakteinfluß als auch Rekombination sind entscheidend für die Arbeitsweise. Zusätzlich werden Möglichkeiten und Einschränkungen für die Datenanalyse mittels einfacher analytischer Ausdrücke aufgezeigt. Es zeigte sich, dass diese nicht immer zur Auswertung von Kennlinien herangezogen werden dürfen. Weiterhin werden erste Simulationsergebnisse eines ambipolaren organischen Heterostruktur-TFTs mit experimentellen Daten verglichen.

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16

Abusabee, K. M. "Thin film engineering for transparent thin film transistors." Thesis, Nottingham Trent University, 2014. http://irep.ntu.ac.uk/id/eprint/127/.

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Zinc oxide (ZnO) and Indium Gallium Zinc Oxide (IGZO) thin films are of interest as oxide semiconductors in thin film transistor (TFT) applications, due to visible light transparency, and low deposition temperature. There is particular interest in ZnO and IGZO based transparent TFT devices fabricated at low temperature on low cost flexible substrates. However, thermal annealing processes are typically required to ensure a good performance, suitable long term stability, and to control the point defects which affect the electrical characteristics. Hence there is interest in post deposition processing techniques, particularly where alternatives to high temperature thermal treatments can be utilised in combination with low temperature substrates. This thesis presents the results of a series of experimental studies as an investigation into photonic (excimer laser) processing of low temperature ZnO and IGZO thin films deposited by RF magnetron sputtering and/or by high target utilisation sputtering (HiTUS), to optimise the microstructure and electrical properties for potential use in thin film electronic applications. ZnO thin films were grown at various deposition parameters by varying oxygen flow rates, RF power, oxygen concentration, and growth temperatures. Subsequently, the films were subjected to three different annealing processes: (i) Thermal Annealing (furnace): samples were thermally annealed in air at temperatures ranging from 300 °C to 880 °C for 1 hour. (ii) Rapid Thermal Annealing: samples were annealed in nitrogen and oxygen environment at temperatures of 600 °C, 740 °C, 880 °C, and 1000 °C, and dwell times of 1-16 s. (iii) Excimer laser annealing: samples were annealed at ambient conditions using a Lambda Physik 305i 284 nm, 20 ns pulse KrF excimer laser with a beam delivery system providing a homogenised 10 mm x 10 mm uniform irradiation at the sample plane. Processing was undertaken at fluences in the range of 0 to 350 mJ/cm2 at single and multiple pulses. IGZO thin films were also investigated following RF magnetron deposition without intentional substrate heating and at various other deposition conditions, followed by laser processing in air at laser energy densities in the range of 0 to 175 mJ/cm2 with single pulse. Processed ZnO films were characterised by room temperature photoluminescence excitation which exhibited that laser annealing at high fluences resulted in suppression of the observed visible deep level emission (DLE) with evolution of a strong UV near band emission (NBE) peak, indicating a reduction of intrinsic defects without film degradation or materials loss that occurred by thermal and rapid thermal annealing. Also the intensity of the NBE peak was strongly influenced by the films growth temperature, with the results showing that as the growth temperature increased beyond ambient; the intensity of the resultant NBE peak decreased as a function of laser energy. TEM studies demonstrate that laser processing provides a controlled in-depth crystallisation and modification of ZnO films. Therefore, laser processing is shown to be a suitable technique to control the crystal microstructure and defect properties as a function of two lasers processing parameters (fluence, number of pulses) - realising optimised film properties as a localised region isolated from the substrate or sensitive underlying layers. In terms of electrical properties, the results indicated a significant drop in sheet resistance as a function of laser anneal from highly resistive (>5 MΩ/sq.) to about 860 Ω/sq. To produce IGZO thin films without intentional substrate heating with lowest sheet resistance as a function of laser processing, low deposition pressure, low oxygen concentration, and high RF power are required. Room temperature Hall effect mobility of 50 nm thick IGZO increased significantly as the laser energy density increased from 75 mJ/cm2 to 100 mJ/cm2 at single pulse reaching values of 11.1 cm2/Vs and 13.9 cm2/Vs respectively.

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17

Cheng, Xiang. "TFTs circuit simulation models and analogue building block designs." Thesis, University of Cambridge, 2018. https://www.repository.cam.ac.uk/handle/1810/271853.

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Building functional thin-film-transistor (TFT) circuits is crucial for applications such as wearable, implantable and transparent electronics. Therefore, developing a compact model of an emerging semiconductor material for accurate circuit simulation is the most fundamental requirement for circuit design. Further, unique analogue building blocks are needed due to the specific properties and non-idealities of TFTs. This dissertation reviews the major developments in thin-film transistor (TFT) modelling for the computer-aided design (CAD) and simulation of circuits and systems. Following the progress in recent years on oxide TFTs, we have successfully developed a Verilog-AMS model called the CAMCAS model, which supports computer-aided circuit simulation of oxide-TFTs, with the potential to be extended to other types of TFT technology families. For analogue applications, an accurate small signal model for thin film transistors (TFTs) is presented taking into account non-idealities such as contact resistance, parasitic capacitance, and threshold voltage shift to exhibit higher accuracy in comparison with the adapted CMOS model. The model is used to extract the zeros and poles of the frequency response in analogue circuits. In particular, we consider the importance of device-circuit interactions (DCI) when designing thin film transistor circuits and systems and subsequently examine temperature- and process-induced variations and propose a way to evaluate the maximum achievable intrinsic performance of the TFT. This is aimed at determining when DCI becomes crucial for a specific application. Compensation methods are reviewed to show examples of how DCI is considered in the design of AMOLED displays. Based on these design considerations, analogue building blocks including voltage and current references and differential amplifier stages have been designed to expand the analogue library specifically for TFT circuit design. The $V_T$ shift problem has been compensated based on unique circuit structures. For a future generation of application, where ultra low power consumption is a critical requirement, we investigate the TFT’s subthreshold operation through examining several figures of merit including intrinsic gain ($A_i$), transconductance efficiency ($g_m/I_{DS}$) and cut-off frequency ($f_T$). Here, we consider design sensitivity for biasing circuitry and the impact of device variations on low power circuit behaviour.

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18

Zhu, Wen Wei. "Organic thin film transistors." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19597.

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Organic thin film transistors (OTFTs) have been fabricated using four different semiconducting polymers: poly[2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), polyhedral oligomeric silsesquioxanes (POSS) poly (2-methoxy-5-(2'-ethyl-hexyloxy)-l,4-phenylene vinylene) (MEH-PPV-POSS), poly[N-(3-methylphenyl)-N,N-diphenylamine-4,4'-diyl] (poly-TPD), and polyhedral oligomeric silsesquioxanes (POSS) poly (N,N'-bis(4-butylphenyl)-N,N'-bis(phenyl)benzidine (poly-TPD-POSS). These OTFTs were fabricated on heavily doped «-type silicon wafers with thermally grown silicon dioxide layer was used as gate insulator. Except for MEH-PPV, the OTFTs studied in this work are the first for the above organic semiconductor materials. From results of current-voltage measurements, it was observed that the present OTFTs showed I-V characteristics of typical /^-channel thin film transistors. Some of the fabricated OTFTs showed performance with relatively large field-effect mobilities (>10~4 cm2 V"1 s"1). The mobility of semiconducting polymer with polyhedral oligomeric silsesquioxanes (POSS) was at least one order of magnitude larger than that of parent polymer without the POSS. The largest mobility value was obtained on poly-TPD-POSS (4.34 x 10"4 cm2 V"1 s"1) in room atmosphere and at room temperature. Thermal annealing under different conditions was carried out on the polymers and the effects on carrier field-effect mobilities were examined. The thermal annealing can increase slightly the field-effect mobilities of the polymers without POSS. However, no significant effect was observed on the field-effect mobilities of the polymers with POSS.

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19

Panda, Durga Prasanna. "Nanocrystalline silicon thin film transistors." [Ames, Iowa : Iowa State University], 2006.

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20

Qian, Feng. "Thin film transistors in polysilicon /." Full text open access at:, 1988. http://content.ohsu.edu/u?/etd,162.

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21

Bauza, M. "Nanocrystalline silicon thin film transistors." Thesis, University College London (University of London), 2013. http://discovery.ucl.ac.uk/1385744/.

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This thesis presents my work on the fabrication of nanocrystalline silicon (nc-Si) thin film transistors and characterization of their stability under different conditions. Nc-Si transistors are promising alternative to the current amorphous silicon (a-Si:H) devices, especially in areas where a-Si:H TFTs are reaching the performance ceiling, e.g. new large area applications such as active matrix organic light emitting diode displays (AMOLED). This is mostly due to the superior nc-Si properties – high carrier mobility and good electrical stability stemming from the crystalline Si grains embedded in a disordered a-Si:H matrix. Another large advantage of nc-Si TFTs over competing materials is the full compatibility with the a-Si:H fabrication base. Nanocrystalline silicon is a relatively new material and some aspects require further investigation before industrial applications. The pool of knowledge on nc-Si devices is especially shallow for the electrical stability of bottom gate TFTs under prolonged illumination which is important for several thin film applications, such as AMOLED and phototransistors. This issue was selected as the main topic of the thesis. Top gate TFTs were also designed, fabricated, characterized and compared to the bottom gate transistors. The electrically detected magnetic resonance method was employed to investigate the nc-Si/dielectric structures and it was shown that it can be used to evaluate the TG TFT channel/dielectric interface.

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22

Lloyd, Giles Christian Rome. "Novel conjugated polymer thin film transistors." Thesis, University of Liverpool, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.399071.

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23

Stott, J. E. "Organic thin film transistors : integration challenges." Thesis, University College London (University of London), 2013. http://discovery.ucl.ac.uk/1393282/.

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This thesis considers some of the requirements and challenges in the eld of organic thin lm transistors (OTFTs), from the standpoint of large scale integration using low temperature plastic compatible processes. A combination of processes and materials for use in the fabrication of OTFTs is developed, yielding device performance comparable with the state of the art for bottom-contact, bottom-gate, organic small molecule thin lm transistors. High quality silicon nitride (SiNx) gate dielectric material is developed using plasma enhanced chemical vapour deposition (PECVD) at a low temperature (150 C) compatible with plastic substrates. A variety of high quality lms are developed, allowing an investigation into the impact of changes in SiNx composition on OTFT performance. Surface modi cation strategies on SiNx substrates are considered, leading to almost an order of magnitude enhancement in OTFT performance, suggesting a suitable device architecture for large scale integration, and exploitation of novel organic material properties. We then examine organic semiconductor nanowire devices, which have begun to emerge as a new and exciting class of device in recent years. This work explores the possibilities of combining traditional thin lm transistor fabrication techniques with novel organic nanowires and examines the resultant transistor device behaviour. Two-dimensional arrays of nanowire devices are analysed, demonstrating the suitability of devices for large area applications. The combination of a large area and plastic compatible, low temperature dielectric with well known organic semiconductors in thin lm devices suggests that the integration of novel organic nanowires could provide an exciting performance enhancement over traditional OTFT devices.

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24

Herlogsson, Lars. "Electrolyte-Gated Organic Thin-Film Transistors." Doctoral thesis, Linköpings universitet, Institutionen för teknik och naturvetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69636.

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There has been a remarkable progress in the development of organic electronic materials since the discovery of conducting polymers more than three decades ago. Many of these materials can be processed from solution, in the form as inks. This allows for using traditional high-volume printing techniques for manufacturing of organic electronic devices on various flexible surfaces at low cost. Many of the envisioned applications will use printed batteries, organic solar cells or electromagnetic coupling for powering. This requires that the included devices are power efficient and can operate at low voltages. This thesis is focused on organic thin-film transistors that employ electrolytes as gate insulators. The high capacitance of the electrolyte layers allows the transistors to operate at very low voltages, at only 1 V. Polyanion-gated p-channel transistors and polycation-gated n-channel transistors are demonstrated. The mobile ions in the respective polyelectrolyte are attracted towards the gate electrode during transistor operation, while the polymer ions create a stable interface with the charged semiconductor channel. This suppresses electrochemical doping of the semiconductor bulk, which enables the transistors to fully operate in the field-effect mode. As a result, the transistors display relatively fast switching (≤ 100 µs). Interestingly, the switching speed of the transistors saturates as the channel length is reduced. This deviation from the downscaling rule is explained by that the ionic relaxation in the electrolyte limits the channel formation rather than the electronic transport in the semiconductor. Moreover, both unipolar and complementary integrated circuits based on polyelectrolyte-gated transistors are demonstrated. The complementary circuits operate at supply voltages down to 0.2 V, have a static power consumption of less than 2.5 nW per gate and display signal propagation delays down to 0.26 ms per stage. Hence, polyelectrolyte-gated circuits hold great promise for printed electronics applications driven by low-voltage and low-capacity power sources.

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Breban, Mihaela. "Photocurrent spectroscopy of pentacene thin film transistors." College Park, Md. : University of Maryland, 2006. http://hdl.handle.net/1903/3973.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2006.
Thesis research directed by: Physics. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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Chen, Y. "Novel polysilicon high voltage thin film transistors." Thesis, University of Cambridge, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.597542.

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Research in High Voltage Thin Film Transistors (HVTFTs) has been driven by the need for devices with reduced on-state resistance and high blocking capability to improve the performance of large area electronic applications. Conventional HVTFTs give unsatisfactory performance because of the high on-state resistance, low breakdown voltage (Offset Drain HVTFT), high possibility of oxide failure and requirement for extra external bias line (Metal Field Plate HVTFT) etc. This thesis presents a novel high voltage thin film transistor structure - Semi-Insulating Field Plate HVTFT (SIFP HVTFT) which utilises a semi-insulating layer as the field plate to modify the conductivity in the offset region. The new structure has demonstrated and enhanced on-state performance relative to conventional offset drain device and a much improved blocking capability compared with all existing high voltage thin film transistor structures. Unlike conventional offset drain TFTs, during the "on-state", the channel formed under the gate can be extended into the offset region by the potential on the semi-insulating field plate which is controlled by the bias on the gate and the drain. Equivalent circuit models for the SIFP HVTFT have been developed for the device analysis. New concepts such as "extended channel" have been proposed for the first time to illustrate the device physics underlying the improvement in performance of the new device. The superior blocking capability is attributed to a very small leakage current flowing through the semi-insulating field plate which increases the radius of potential curvature near the drain. This leakage current, however, does not significantly contribute to the main current flowing through the device. It is concluded that the SIFP HVTFT presents a new concept to the high voltage thin film transistor family and has clearly shown many advantages over conventional HVTFTs.

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Nausieda, Ivan Alexander. "Pentacene integrated thin-film transistors and circuits." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/55119.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
Page 179 blank. Cataloged from PDF version of thesis.
Includes bibliographical references.
Organic semiconductors offer the potential of large-area, mechanically flexible electronics due to their low processing temperatures. We have developed a near-room-temperature (< 95°C) process flow to fabricate pentacene integrated organic thin-film transistors (OTFTs) compatible with plastic substrates such as polyethylene terephthalate (PET). Integration of inkjet printed organic photoconductors (OPDs) based on titanyl pthalocyanine with OTFTs is demonstrated for the first time in an integrated process. Using the OTFT as a switch in series with an OPD, a pixel circuit was designed and measured, in addition to a proof-of-concept 4x4 active matrix imager. The individual pixels were measured to have a responsivity of 6x10-5 A/W, and a pixel on/off conductance ratio of 880, both at an irradiance of 5 mW/cm 2. The imager uses a 25 V power supply and was shown to correctly image a "T" pattern after 1st order calibration. A model for the current-voltage characteristics based upon amorphous silicon models was implemented in MATLAB to investigate design trade-offs in organic digital circuits. A dual threshold voltage process is suggested to enable area-efficient zero-VGS current sources. The area and power savings of this approach is discussed compared to a single VT process. We also motivate the necessity for lowering the power supply, both for area savings and improvement in circuit lifetime due to reduction in bias stress effects. A process flow for a dual VT OTFT technology, enabled using two gate metals, is presented. By using a low work function metal (aluminum) and a high work function metal (platinum), we can obtain two threshold voltage devices.
(cont.) Devices were measured to be nominally identical, shifted by a VSG which we call the [Delta]VT. A [Delta]VT of 0.6 V was consistently observed over multiple wafer lots. This is the first demonstration of modification of OTFT VT by changing the gate work function. Area-minimized digital logic designed in the dual VT technology was demonstrated with a 3 V supply, the lowest supply reported for integrated OTFTs. In addition, we report some of the first analog organic integrated circuits, including a differential pair with differential gain of 23 dB and common-mode rejection ratio (CMRR) of 23 dB. A two-stage uncompensated operational amplifier was fabricated and measured to have an open-loop gain of 36 dB and unity gain frequency of 7.5 Hz. The op-amp has a unity gain-bandwidth product of 473 Hz while dissipating < 2 nW with a 5 V supply. The comparator uses 5 nW of power, and has an input offset of 200 mV. We show the frequency response of the op-amp and comparator are dominated by parasitic overlap capacitances. The parasitics of the zero-VGs load limits frequency response, and technological improvements to increase operating frequency are suggested. We motivate a self-aligned process flow, which uses a high optical density gate to serve as a mask layer. A backside exposure patterns the source/drain layer. It is demonstrated that the parasitic capacitances can be reduced by almost an order of magnitude, from 1 fF/jlm to 0.15 fF/jm. A method to improve carrier mobility is also presented. These process improvements have the potential to improve the switching speeds of organic circuits by more than two orders of magnitude.
by Ivan Alexander Nausieda.
Ph.D.

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28

Marinkovic, Marko [Verfasser]. "Contact resistance effects in thin film solar cells and thin film transistors / Marko Marinkovic." Bremen : IRC-Library, Information Resource Center der Jacobs University Bremen, 2013. http://d-nb.info/1037014243/34.

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29

Hein, Moritz. "Organic Thin-Film Transistors: Characterization, Simulation and Stability." Doctoral thesis, 2013. https://tud.qucosa.de/id/qucosa%3A28703.

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Organic thin ﬁlm transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These beneﬁts are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric ﬁeld-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identiﬁed as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and signiﬁcantly alleviating the bias-stress eﬀect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.:1. Introduction and Motivation 10 2. Organic Semiconductors and Thin-Film Transistors 12 2.1. Fundamentals of Organic Semiconductors 12 2.1.1. Structural and Electronic Properties 12 2.1.2. Polarons and Trap States 15 2.1.3. Doping of Organic Semiconductors 16 2.2. Charge-Carrier Transport in Organic Semiconductors 18 2.2.1. Field-Eﬀect Mobility 18 2.2.2. Gaussian Disorder Model 21 2.2.3. Variable-Range Hopping Models 24 2.2.4. Fishchuk Model 26 2.3. Organic Field-Eﬀect Transistors 27 2.3.1. Transistor Geometry 27 2.3.2. Transistor Equations 29 2.3.3. Evaluation of Mobility 32 2.3.4. Threshold Voltage 34 2.3.5. Contact Resistance 35 2.3.6. Au-SAMs 38 2.3.7. Dielectric 39 2.3.8. Scaling and Short Channel Eﬀects 41 2.3.9. Stability and Bias-Stress 43 2.4. Device Simulation 44 3. Materials and Methods 46 3.1. Materials 46 3.2. Sample Preparation 50 3.2.1. Sample Preparation in cooperation with the industrial partner 51 3.2.2. Sample Preparation at IAPP 52 3.2.3. Staggered Transistors at IAPP 56 3.3. Sample Characterization 57 3.3.1. Electrical Measurement Setup 57 3.3.2. Parameter Extraction 60 3.3.3. Contact Resistance 61 3.3.4. Kelvin-Probe Atomic Force Microscopy 64 3.3.5. UPS Measurement 65 4. Organic Field-Effect Transistors - Experiment and Simulation 67 4.1. Bottom-Gate Transistors 67 4.1.1. Semiconductors 67 4.1.2. Bipolar Transport 72 4.1.3. Electrode Treatments 74 4.1.4. Channel Treatments 77 4.1.5. Polymer Transistors 79 4.2. Polymer Transistors at Room Temperature 85 4.2.1. Parameter Extraction 85 4.2.2. Four-Point-Probe Measurements 90 4.2.3. Transferline Methode 96 4.2.4. UPS Measurements 100 4.3. Cryostat Measurements 102 4.3.1. Transistor Characteristics 102 4.3.2. Contact Resistance 105 4.3.3. Density of States 107 4.4. Transistor Simulation 110 4.4.1. Introduction of Device Simulation with Genius 110 4.4.2. Mesh and Geometry 111 4.4.3. Contact Resistance of Charge-Carrier Injection 112 4.4.4. Temperature Dependent Simulations 114 4.4.5. Implementation of Donor Traps 116 4.4.6. Poole-Frenkel Discussion 118 4.4.7. Contact Resistance of Geometry 122 4.4.8. Simulation with Advanced Mobility Models 123 4.5. Bias-Stress Reliability 128 4.5.1. Bias-Stress Phenomena 128 4.5.2. Doped Transistors 136 4.5.3. Polymer Transistors 145 5. Conclusion and Outlook 150 A. Appendix 154 A.1. Charge-Carrier Mobility measurements for solar cell materials 154 A.2. Simulation pictures 154 B. Bibliography 160

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30

Sinha, Rajat. "Reliability Physics of Thin-Film Transistors." Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5682.

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Thin-film transistor technology based on non-crystalline materials forms the workhorse of large area electronics applications including display systems, sensor systems and novel technologies including flexible electronics. A successful development and commercialisation of any technology requires a thorough understanding of the physics and reliability concerns revolving around that technology. Electrostatic discharge (ESD) is one of the major reliability concerns in microelectronics industry and can plague the device development at many stages. It is a high-field high-frequency phenomenon and involves charge transfer from one body to another. Studying ESD behaviour also leverages studies on non-equilibrium electro thermal behaviour of the device and highlights various high-field effects taking place in the device under test. In this work, we study the ESD behaviour of thin-film transistor technologies based on hydrogenated amorphous silicon (a-Si:H) and organic materials. In the first chapter, we give an overview of the current level of understanding vis-a-vis the ESD behavior of non-crystalline materials based thin- lm technology platform. A brief discussion on the ESD behavior and testing methodology of conventional silicon technology is presented. We also discuss ESD issues in TFT technology, current roadblocks and possible solutions. We also discuss other reliability issues that plague TFTs. Following this, a detailed description, based on earlier studies, of the physical behavior, failure characteristic and degradation behavior of hydrogenated amorphous silicon, metal oxide based semiconductors, poly silicon and organics based semiconductors is presented. A review of plethora of strategies that have been employed to enhance the ESD robustness in these technologies, including novel designs and architectures is presented. In the second chapter, we discuss, in detail, physical behavior of inverted staggered hydrogenated amorphous silicon TFT technology under ESD stress conditions. Using electrical and optical techniques, device failure and TLP quasi-static I-V characteristics are discussed. Raman spectroscopy is utilized to study any material variations with the stress levels. Finally, we move on to discuss the impact of device design including impact of device dimensions and architectural parameters including top passivation on the ESD behavior of these devices. As we move on to the third chapter, we study the device degradation of a-Si:H thin-film transistors under the application of high field stress. I-V, C-V and raman spectroscopy measurements are used to investigate the degradation mechanism. Threshold voltage shift under moderate and high electric field in investigated and spatial variance of degradation mechanism along the channel length is discussed. Variation of material properties is studied. We also discuss the role of self-heating in device degradation and is studied by varying the pulse width of stress pulses in nanoseconds range. We also discuss the performance recovery mechanism through the application of thermal and gate bias anneal and this has been investigated through a recursive cycle of stress- anneal and measurements. Following these investigations, we report and study the phase transition behavior of a-Si:H TFTs under high-field nano-second timescale electrical stress. This transition is confirmed through a series of measurements including Raman Spectroscopy, Atomic force microscopy, Scanning electron microscopy, Transmission electron microscopy and I-V measurements. The observed behavior is attributed to avalanche generation, optical phonon generation and localisation. We also study the case of drain underlap devices and study how their behavior is different from conventional TFTs. Impact of pulse condition including pulse width and channel dimensions on the onset of phase transition is also explored. Interestingly, it is also found that the discussed phase transition mechanism yields resultant nc-Si of quality at par with commercial methods. At this point in the thesis, we have investigated the ESD and high-field reliability behavior in a-Si:H TFTs. In the next chapter, we move our discussion towards incorporating device architecture that improves the ESD robustness of a-Si:H TFT technology. The discussed architecture is shown to improve the ESD robustness by 4-5 times with the same area. We also investigate the physics of device behavior and explore the impact of technological parameters on failure behavior. We also take a look at the pre breakdown degradation behavior of this architecture. Finally, we take a look at the ESD behavior of thin-film resistors. In the next chapter, we discuss the ESD behavior of a-Si:H based diode-connected transistors. We discuss the ESD behavior as a function of stressing conditions, device dimensions and on the application of negative ESD stress. We then discuss the instability behavior of a-Si:H based diode-connected TFTs. This investigations assumes importance due to the important role of these devices in switching and ESD protection circuits. Variations in cut-in voltage of device under test is studied with application of the stress. DC I-V measurements are used to explore the degradation behavior and shift in cut-in voltage as a function of ambient temperature, pulse width and voltage levels is investigated. It is also found that the degradation mechanism in these devices is different from the case of conventional TFTs. Till this point in this thesis, discussions have revolved around the behavior of a-Si:H based devices. However, large area electronics based on novel classes of materials have gained significant traction in recent years. One such class of materials is that of organic semiconductors. Organic semiconductors also offer the advantage of cheaper fabrication with lower thermal budget. This has enabled their application in flexible and printable electronics. In the course of this work, we focus on pentacene as the model organic material. In the seventh chapter, we discuss the ESD failure of pentacene channel OTFTs. Charge transport mechanism at nano-second timescale is studied and orders of magnitude difference are observed in DC and ESD timescales. Device failure is investigated through SEM imaging and EDX spectroscopy. We also discuss the impact of self-heating behavior along with the impact of channel dimensions and stressing conditions. It is observed that the device failure is not due to semiconductor breakdown. We also study the impact of introduction of self-assembled monolayer on charge transport and ESD failure. Finally, we discuss the device failure for the case of high-voltage pentacene OTFTs with a 1μm thick dielectric. Following the investigation of ESD behavior of pentacene based OTFTs, we report high frequency behavior of pentacene channel OTFTs through the exploration of transient voltage waveforms in the eighth chapter. Pentacene OTFTs present a delayed response to the applied signal due to the parasitic impedance involved. The device behavior is affected by the bias stress effect and self-heating effect. It is also shown that as the channel length increases, device responds faster. However, this behavior is shown to be present at smaller channel length and as the channel length increases, the device impedance increases and response gets slower.

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31

Nair, Aswathi R. "Textured Gate Thin Film Transistors and Circuits." Thesis, 2018. https://etd.iisc.ac.in/handle/2005/5415.

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Reliable, high performance integrated circuits based on thin film transistors (TFTs) on flexible substrates have a lot of advantages, especially in applications like flexible displays, spherical image sensors, wearable devices for health care and communication etc. However, the materials for flexible substrates are temperature sensitive, which limits the fabrication process temperature and hence TFTs have non-crystalline semiconductor films as their active layer. The low transconductance associated with these films and absence of complementary devices often makes circuit design a tedious procedure. Also, TFTs on flexible substrates experience significant mechanical strain due to bending and buckling, which affects their performance. Therefore, a study on the influence of bending on the behavior of TFTs is also essential to design high performance integrated circuits. Bending can alter the electrical properties of TFTs in two ways; it can cause stresses in the Metal-Insulator-Semiconductor (MIS) stack and it can change the electric field distribution due to curvature at the MIS stack. Here, we have developed analytical models that explain the impact of curvature alone on the TFT. The electrostatics of the MIS stack and the current-voltage characteristics of the TFT are obtained by solving Poisson-Boltzmann equation in polar co-ordinates. The results show that the impact of curvature is significant until the radius of curvature is one order more than the insulator thickness (observed during buckling). The analytical models are validated using TCAD simulations performed on amorphous indium gallium zinc oxide TFTs, for which a close match (error less than 2%) is obtained. In the second part of the thesis we have experimentally demonstrated how texturing of gate metal layer influences the transconductance of TFTs. Texturing introduces curvature at the insulator-semiconductor interface and alters the TFT parameters and current-voltage characteristics. This method is advantageous over aspect ratio scaling method, because the latter results in increased layout area and increased overlap capacitance, which in turn limits the resolution and performance of array based active matrix architectures. Instead, textured TFTs permits transconductance modulation even for minimum aspect ratio devices. Experiments are performed on hydrogenated amorphous silicon TFTs for comparing the performance of planar and textured devices. The texturing is realized in the shape of periodic striations oriented along different directions, using a dual gate metal deposition and patterning. The textured TFTs show upto ±40% increase or decrease in transconductance depending on the angle of orientation of texturing as compared to conventional planar TFTs. The influence of texturing on various TFT parameters is also discussed. Detailed analytical models for electrostatics and current voltage characteristics are provided to explain the behavior of textured devices. These models are then compared with experiments which show a good match between the two. The third part of the thesis discusses the use of these textured TFTs for designing circuits with better performance. Common source amplifiers fabricated with textured TFTs show twice the dc gain as compared to planar TFTs without changing the aspect ratio. The last part of the thesis discusses the aspect of threshold voltage instability in TFTs. Both planar and textured TFTs are subjected to threshold voltage shift by biasing them at constant drain and gate bias for one hour. The results show that the angle of orientation of texturing influences the shift in threshold voltage with time

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32

Moradi, Maryam. "Vertical Thin Film Transistors for Large Area Electronics." Thesis, 2008. http://hdl.handle.net/10012/3937.

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The prospect of producing nanometer channel-length thin film transistors (TFTs) for active matrix addressed pixelated arrays opens up new high-performance applications in which the most amenable device topology is the vertical thin film transistor (VTFT) in view of its small area. The previous attempts at fabricating VTFTs have yielded devices with a high drain leakage current, a low ON/OFF current ratio, and no saturation behaviour in the output current at high drain voltages, all induced by short channel effects. To overcome these adversities, particularly dominant as the channel length approaches the nano-scale regime, the reduction of the gate dielectric thickness is essential. However, the problems with scaling the gate dielectric thickness are the high gate leakage current and early dielectric breakdown of the insulator, deteriorating the device performance and reliability. A novel ultra-thin SiNx film suitable for the application as the gate dielectric of short channel TFTs and VTFTs is developed. The deposition is performed in a standard 13.56MHz PECVD system with silane and ammonia precursor gasses diluted in nitrogen. The deposited 50nm SiNx films demonstrate excellent electrical characteristics in terms of a leakage current of 0.1 nA/cm?? and a breakdown electric field of 5.6MV/cm. Subsequently, the state of the art performances of 0.5??m channel length VTFTs with 50 and 30nm thick SiNx gate dielectrics are presented in this thesis. The transistors exhibit ON/OFF current ratios over 10^9, the subthreshold slopes as sharp as 0.23 V/dec, and leakage currents in the fA range. More significantly, a high associated yield is obtained for the fabrication of these devices on 3-inch rigid substrates. Finally, to illustrate the tremendous potential of the VTFT for the large area electronics, a 2.2-inch QVGA AMOLD display with in-pixel VTFT-based driver circuits is designed and fabricated. An outstanding value of 56% compared to the 30% produced by conventional technology is achieved as the aperture ratio of the display. Moreover, the initial measurement results reveal an excellent uniformity of the circuit elements.

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33

"Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors." Doctoral diss., 2016. http://hdl.handle.net/2286/R.I.37039.

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abstract: A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs between low temperature and low stress (less than -70 MPa compressive) and device performance. Devices with a dark current of less than 1.0 pA/mm2 and a quantum efficiency of 68% have been demonstrated. Alternative processing techniques, such as pixelating the PIN diode and using organic photodiodes have also been explored for applications where extreme flexibility is desired.
Dissertation/Thesis
Doctoral Dissertation Chemical Engineering 2016

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34

Chiu, Yi-Ming, and 邱義銘. "Study of Drain Engineering in Polycrystalline Silicon Thin-Film-Transistors (Poly-Si TFT)." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/73013755227128557554.

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碩士
國立臺灣科技大學
電子工程系
93
Polycrystalline silicon (polysilicon) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays, allowing the integration of both active matrix and driving circuitry on the same substrate. However, conventional self-aligned polysilicon TFTs present several undesired effects in the electrical characteristics, including large off-state currents (leakage), kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and electric field near the drain region relief is essential. In this thesis, a novel poly-Si TFTs formed by using the large-angle-tilt-implanted-drain (LATID) scheme has been analyzed. First, three types TFTs with different drain structure were fabricated. They are the conventional single source/drain TFTs, the Lightly-Doped-Drain (LDD) TFTs and the large-angle-tilt-implanted drain (LATID) TFT. Next, the electrical characteristics of the LDD TFTs formed with different fabrication parameters such as LDD implantation doses and implanting energies were investigated. From the results, the relation between electrical characteristics of the LDD TFTs and such process parameters has been identified. In the same ways, electrical characteristics of the LATID TFTs were also studied. The LATID TFTs are formed with various LATID doses, various LATID energies and various LATID tilt angle. It is found that the implantation dose and implantation energy affected the performance of the LDD and the LATID TFTs. The implantation tilt angle of the LATID TFTs, moreover, has a most profound influence on the performance of the LATID TFTs. Finally, the electrical characteristics of the conventional single source/drain TFTs, the LDD TFTs and the LATID TFTs were compared. It could be found that the LATID TFTs achieve much smaller leakage than both the conventional single source/drain TFTs and the LDD TFTs, attributable to the more effective suppression of carrier emission via trap states. Moreover, the peak impact ionization current, associated with the device reliability, of the LATID TFTs is also significantly smaller than that of the conventional TFTs and the LDD TFTs. As a result, a poly-Si TFTs with excellent device characteristics and reliability can be implemented by simply using the LATID fabrication scheme.

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35

Chun-DaTu and 塗俊達. "Design of a-Si:H Thin-Film Transistors Driving Circuit for TFT-LCD Applications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/10539326124633239785.

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36

"Design of NMOS and CMOS Thin Film Transistors and Application to Electronic Textiles." Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.15126.

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abstract: The field of flexible displays and electronics gained a big momentum within the recent years due to their ruggedness, thinness, and flexibility as well as low cost large area manufacturability. Amorphous silicon has been the dominant material used in the thin film transistor industry which could only utilize it as N type thin film transistors (TFT). Amorphous silicon is an unstable material for low temperature manufacturing process and having only one kind of transistor means high power consumption for circuit operations. This thesis covers the three major researches done on flexible TFTs and flexible electronic circuits. First the characterization of both amorphous silicon TFTs and newly emerging mixed oxide TFTs were performed and the stability of these two materials is compared. During the research, both TFTs were stress tested under various biasing conditions and the threshold voltage was extracted to observe the shift in the threshold which shows the degradation of the material. Secondly, the design of the first flexible CMOS TFTs and CMOS gates were covered. The circuits were built using both inorganic and organic components (for nMOS and pMOS transistors respectively) and functionality tests were performed on basic gates like inverter, NAND and NOR gates and the working results are documented. Thirdly, a novel large area sensor structure is demonstrated under the Electronic Textile project section. This project is based on the concept that all the flexible electronics are flexible in only one direction and can not be used for conforming irregular shaped objects or create an electronic cloth for various applications like display or sensing. A laser detector sensor array is designed for proof of concept and is laid in strips that can be cut after manufacturing and weaved to each other to create a real flexible electronic textile. The circuit designed uses a unique architecture that pushes the data in a single line and reads the data from the same line and compares the signal to the original state to determine a sensor excitation. This architecture enables 2 dimensional addressing through an external controller while eliminating the need for 2 dimensional active matrix style electrical connections between the fibers.
Dissertation/Thesis
Ph.D. Electrical Engineering 2012

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37

Trivedi, Kruti. "Design, Fabrication and Characterization of ZnO based Thin Film Schottky Diodes and Transistors." Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5821.

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The thesis focuses on the development of thin film Schottky diodes and thin film transistors (TFTs) based on ZnO. ZnO has been recognized as a promising candidates for the next generation of transparent and flexible electronics for displays. Some of the interesting properties of ZnO include the variation from insulating to semiconducting nature by change of stoichiometry, the relative low toxicity enabling its use in edible materials, the presence of a reasonably high electron mobility and its high transmission to visible light. All of these properties have increased interest for the development of ZnO-TFTs and diodes. This work focuses on process development of thin film Schottky diodes( Al-ZnO-Ag) and transistors(Al-ZnO-ZrO2). The Schottky diodes were developed with thermally evaporated Aluminium ohmic contact and silver Schottky contact. The fabricated diodes had cut-in voltage between 1-2 V with mean reverse saturation current of 1.0 x 10^-7 A and an excellent rectification ratio of 10^6. Thin film transistors were developed with thermally evaporated Aluminium contacts for Gate, Source and Drain. Zinc oxide was used as semiconductor channel material. For process development of thin film transistors, Zinc oxide was used as semiconductor and a transparent thin film with transmittance of 83.45 % at 450 nm was deposited using DC Reactive sputtering of zinc in oxygen ambient of 1 x 10^-3 mbar. The optical bandgap was found to be around 3.15 eV. ZrO2 was selected as Gate dielectric because of its high dielectric constant, wide band gap and excellent chemical and thermal stability. The ZrO2 thin film was deposited by DC reactive sputtering in an oxygen ambient of 1.5 x 10^-3 mbar. The maximum drain to source current was found to be 25.45 mA and maximum leakage gate current was found to be 0.22 mA.

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38

Huang, San-Hao, and 黃三豪. "Optical Design of Novel Thin Film Transistor (TFT) Auto Laser Repair Equipment." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/43053139906065513961.

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碩士
國立中興大學
精密工程學系所
98
Taiwan plays one of the world''s leading OEM panel production roles. However, in the fast booming panel industry, the ability to handle the defects on panels is not so strong. Especially when panel size gets larger and larger and shows defective symbols, the fixing technique will be of much importance. In response to this demand, the domestic companies are using laser technology to develop “ TFT Auto Laser Repair Equipment ”, but the machine core parts “ laser repair system ” needs being imported from U.S. and Japan, and the price is high. In light of this, the main contribution of this thesis is to design “ laser repair system ”, with using of optics principle and optics software. We successfully design and simulate the internal optical components and the overall system. Thus our country has built our own design capability. In addition to “ laser repair system ”, a unique technology called “ fast fiber optic ” has been developed, which can be used to judge material defects on panels immediately. When this novel technique is integrated with the auto repair machine, this improved equipment can have the benefits of reducing human inspection errors and enhance the repair yield.

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39

Zhang, Jia-Wei, and 張家偉. "Structure Design of Polycrystalline Silicon Thin-Film-Transistors (Poly-Si TFTs)." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/43301490118093242811.

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碩士
國立臺灣科技大學
電子工程系
97
Polycrystalline silicon thin-film-transistors (Poly-Si TFTs) have been widely used in various applications, such as static random memories (SRAMs), photodetector amplifier, scanner, and active matrix liquid crystal displays (AMLCDs). The electron field mobility of the ploy-Si TFT is larger than that of the amorphous-Si (a-Si) TFT, allowing the integration of both active matrix and driving circuitry on the same substrate. However, the conventional self-aligned poly-si TFT induces several undesired effects in the electrical characteristics, including large off-state currents (leakage), kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and electric field near the drain region relief is essential. In order to improve the electrical properties of devices and process simplification, in this thesis, poly-Si TFTs formed by using the large-angle-tilt-implantation-through-spacer (LATITS) scheme and the hetero-structure poly-SiGe/poly-Si TFT scheme have been analyzed. First, three types TFTs with different drain structures were fabricated. They are the conventional single source/drain TFT, the Lightly-Doped-Drain (LDD) TFT and the large-angle-tilt-implantation-through-spacer (LATITS) TFT. Next, the electrical characteristics of LATITS TFTs formed with different fabrication parameters such as implantation dose, implantation energy and implantation tilt angle were investigated. And then, the electrical characteristics of the conventional single source/drain TFT, the LDD TFT, and the LATITS TFT were compared. It could be found that the LATITS TFT causes much smaller leakage current than both the conventional single source/drain TFT and the LDD TFT, attributable to the more effective suppression of carrier emission via trap states. As a result, a poly-Si TFT with excellent device characteristics and reliability can be implemented by simply using the LATITS fabrication scheme. Finally, the hetero-structure poly-SiGe/poly-Si TFT was studied. By changing the thickness of poly-SiGe and ploy-Si as well as studying the influence of different drain voltages. At low drain bias, it’s found that a thinner channel layer has the better ability to suppress the bulk punch-through, and the threshold voltage is lower. In addition, because the band gap of the poly-SiGe TFT is smaller than that of the poly-Si TFT, thus the poly-SiGe TFT shows a larger driving current. However, the leakage current for the poly-Si TFT is lower than that for the poly-SiGe TFT. Hence, we can use the hetero-structure poly-SiGe/poly-Si TFT to get a higher driving current and a lower leakage current. On the other hand, the channel layer thickness of the poly-SiGe TFT and the poly-Si TFT is changed to study its influence on device characteristics. The on-current and the leakage current are obviously increased when the gate oxide thickness is decreased, due to the better gate control ability.

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40

Wu, Min-Lin, and 吳旻霖. "Study of buried-channel Polycrystalline Silicon Thin-Film-Transistors (Poly-Si TFTs)." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/82rtt3.

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碩士
國立臺灣科技大學
電子工程系
94
Poly-Si TFTs play an important role for panel fabrications, enhancing the integration of both active matrix and peripheral driving circuitry on the same substrate. However, poly-Si TFTs lead to some poor effects, like large off-state currents, kink effect and hot carrier effect. These effects are mainly due to the high lateral electric field intensity near the drain, so it is necessary to alleviate the electric field intensity for improving those problems mentioned-above. We use TSUPREM-4 to simulate the TFT structures and operate MEDICI to simulate the electrical characteristics of devices. In this thesis, three types TFTs with different structure were studied. They are the conventional single source/drain TFTs, the TFTs with Vth-adjustment method and the buried-channel (BC) TFTs. Some fabrication parameters such as various gate oxide thicknesses and different gate length (or channel length) would also included in discussion with the three structures. After adding the LDD structure, the samples of the three structures would be also discussed. Finally, the electrical characteristics of the conventional single source/drain TFTs, the TFTs with Vth-adjustment method, the BC TFTs, and the BC TFTs with LDD structure were compared. They were the conventional single source/drain TFTs, boron implantation dose at 1E12 cm-2 doses with 20keV energy for the TFT with Vth-adjustment method, the BC TFT with phosphorus implantation dose at 2E11 cm-2 doses with 30keV energy and boron implantation dose at 1E12 cm-2 doses with 20keV energy, and the LDD structure is formed with phosphorus implantation dose at 2E11 cm-2 doses at 100 keV energy for the BC TFT. It could be found that the BC TFTs with LDD structure achieve much smaller leakage and less kink effect than the other three structures, attributable to the more effective suppression of carrier emission via trap states. Moreover, the lower lateral electric field intensity near the drain also showed in BC TFTs with LDD structure. As the result, the simple and self-aligned method for the BC with LDD structure is an effective way on panel fabrications to improve some bias-caused problems.

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41

Raghuraman, Mathangi. "Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3176.

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Thin Film Transistors (TFTs) are widely used in large area electronics because they offer the advantage of low cost fabrication and wide substrate choice. TFTs have been conventionally used for switching applications in large area display arrays. But when it comes to designing a sensor actuator system on a flexible substrate comprising entirely of organic and inorganic TFTs, there are two main challenges – i) Fabrication of complementary TFT devices is difficult ii) TFTs have a drift in their threshold voltage (VT) on application of gate bias. Also currently there are no circuit simulators in the market which account for the effect of VT drift with time in TFT circuits. The first part of this thesis focuses on integrating the VT shift model in the commercially available AIM-Spice circuit simulator. This provides a new and powerful tool that would predict the effect of VT shift on nodal voltages and currents in circuits and also on parameters like small signal gain, bandwidth, hysteresis etc. Since the existing amorphous silicon TFT models (level 11 and level 15) of AIM-Spice are copyright protected, the open source BSIM4V4 model for the purpose of demonstration is used. The simulator is discussed in detail and an algorithm for integration is provided which is then supported by the data from the simulation plots and experimental results for popular TFT configurations. The second part of the thesis illustrates the idea of using negative feedback achieved via contact resistance modulation to minimize the effect of VT shift in the drain current of the TFT. Analytical expressions are derived for the exact value of resistance needed to compensate for the VT shift entirely. Circuit to realize this resistance using TFTs is also provided. All these are experimentally verified using fabricated organic P-type Copper Phthalocyanine (CuPc) and inorganic N-type Tin doped Zinc Oxide (ZTO) TFTs. The third part of the thesis focuses on building a robust amplifier using these TFTs which has time invariant DC voltage level and small signal gain at the output. A differential amplifier using ZTO TFTs has been built and is shown to fit all these criteria. Ideas on vertical routing in an actual sensor actuator interface using this amplifier have also been discussed such that the whole system may be “tearable” in any contour. Such a sensor actuator interface can have varied applications including wrap around thermometers and X-ray machines.

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42

"Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers." Master's thesis, 2012. http://hdl.handle.net/2286/R.I.15984.

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abstract: ABSTRACT This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10 - 100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.
Dissertation/Thesis
M.S. Electrical Engineering 2012

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43

Chiou, Chi-Ming, and 邱啟明. "The method for checking alignment accuracy of a thin film transistor (TFT) by TEG test." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/44027398025017740963.

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碩士
中原大學
電子工程研究所
100
Today’s TFT LCD Panel Makers use optical measurement to measure the distance of patterns exposed by two different masks to present the alignment accuracy of two mask . But it is hard to do a lot of alignment accuracy check，because the optical measurement’s tact time is very long for each inspection . This article mainly introduced the method for checking alignment accuracy of a thin film transistor (TFT)，the switch is using the Mask Overlap relations to form a open or non-open circuit and combine the Array TEG(Test Element Group) for checking alignment accuracy. It was found the design of space GE/PE should be 3.5um，because after wet etching process it will become to 2um，it means that the overlap of GE/PE is almost about 1um，will match the control spec of Overlap for LCD Maker.

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44

Lai, Erh-Kun, and 賴二琨. "Process Integration of 3D Thin Film Transistor (TFT) NAND Flash and Resistive Random Access Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/6jcdv2.

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45

Peng, Yu-Shen, and 彭昱燊. "Process and Structure Design of Microcrystalline Silicon Thin-Film-Transistors (μC-Si TFTs)." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57982851018671873312.

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碩士
國立臺灣科技大學
電子工程系
98
Microcrystalline silicon thin-film-transistors (μC-Si TFTs) have been widely studied. Due to better device characteristic, and large area growth using a lower temperature process, compared to amorphous silicon thin-film-transistors, it has larger electron field mobility and lower energy band gap. Recently, it has been believed can substitute for the a-Si:H TFTs on large substrate area liquid crystal displays application status. However, μC-Si TFTs has some unavoidable problems, such as, large leakage current, non-uniform on fabrication, and worse device characteristic than polycrystalline silicon TFTs. For the improvement of device characteristic and the process simplification for μC-Si TFTs, in this thesis, μC-Si TFTs formed by using self-aligned silicided scheme and top gate staggered-type μC-Si TFTs structure have been studied, respectively. In this thesis, μC-Si TFTs were examined by device simulation. First, the self aligned silicided scheme μC-Si TFTs are discussed. As compared to the previous top-gate staggered structure, the self-aligned silicided scheme leads to larger bending of energy band near the source region, which facilitates causing more carriers tunneling. In addition, for the top-gate staggered structure, since the source/drain electrode is spaced from the surface channel layer, the parasitic series resistance between the electrode and surface channel layer is considerably caused. As a result, the self-aligned silicided scheme can cause a larger conduction current than the top-gate staggered structure. Following, the silicide thickness of self aligned silicided scheme is changed, to study its influence to device characteristic. Second, top gate staggered type μC-Si TFTs with difference channel layer thicknesses are discussed. It is found that, for a given electrode thickness, a proper channel layer thickness should be chosen to achieve better device characteristic. Finally, as compared with single electrode metal, the stacked electrode can achieve a better trade-off between nmos and pmos driving current.

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46

Chuang, Shu-Ya, and 莊淑雅. "A Study of Device Characteristics and Applications of Polysilicon Thin Film Transistors(TFTs)." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/90113193098412417917.

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碩士
國立交通大學
電子研究所
82
In this thesis, the poly-Si TFTs devices are fabricated by conventional standard CMOS and BiCMOS processes. The char- acteristics and electrical parameters of the devices have been obsreved and studied, including small dimension effect and off- current behavior. And the gate-controlled mobility is also characterized and explained. These CMOS/BiCMOS com- patible poly-Si TFTs can be used in the situation where chip area reduction of circuits is a very important concern, be- cause of its ability of three-dimensional integration. The basic application idea is that if the TFTs can be realized by any process, it will become more applicable in more situ- ation. It has also been shown that the photosensitivity of the poly- TFTs is significant. The dependences of the photocurrent on gate voltage, drain voltage and channel doping are studied, and the physical mechanisms are given.The excellent photosen- sitivity may be applied to the design of light sensor or light trigger elements and integrated on CMOS/BiCMOS chip.

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47

Chen, Lei-Guang, and 陳雷光. "A LTPS (Low temperature polysilicon) TFT (Thin-film transistor) Chip for Dielectrophoretic Manipulation and Bio-detection." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/12593496600019510167.

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碩士
國立清華大學
電子工程研究所
98
This study has successfully used LTPS TFT process technology to design a bio chip that can perform dielectrophoretic (DEP) manipulation and optical detection. The LTPS process has the benefit of less post-processing steps required than the CMOS (complementary metal oxide semiconductor) process to realize the chip. In addition, the process can provide a large chip area at low cost. Reliability, however, is the main issue that the LTPS process has to improve. The basic principle of DEP force and its mathematical model will be presented. CFD-RC software is utilized for simulation to ensure microbeads can be successfully moved to the target electrodes based on our design. Bio-detection is achieved by using image sensors. H-spice simulation is used to verify the feasibility of the circuit design. In the experiments, a thin layer of silicon dioxide is deposited on chip surface for surface functionalization and biomolecule immobilization. Immobilized microbeads can be moved to the target microelectrodes by DEP and produce specific bindings with the immobilized biomolecules on sensor surface. Those beads are successfully detected by the optical sensors underneath microelectrodes to validate the bio-recognition event.

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48

Raghuraman, Mathangi. "Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface." Thesis, 2014. http://hdl.handle.net/2005/3176.

Full text

Abstract:

Thin Film Transistors (TFTs) are widely used in large area electronics because they offer the advantage of low cost fabrication and wide substrate choice. TFTs have been conventionally used for switching applications in large area display arrays. But when it comes to designing a sensor actuator system on a flexible substrate comprising entirely of organic and inorganic TFTs, there are two main challenges – i) Fabrication of complementary TFT devices is difficult ii) TFTs have a drift in their threshold voltage (VT) on application of gate bias. Also currently there are no circuit simulators in the market which account for the effect of VT drift with time in TFT circuits. The first part of this thesis focuses on integrating the VT shift model in the commercially available AIM-Spice circuit simulator. This provides a new and powerful tool that would predict the effect of VT shift on nodal voltages and currents in circuits and also on parameters like small signal gain, bandwidth, hysteresis etc. Since the existing amorphous silicon TFT models (level 11 and level 15) of AIM-Spice are copyright protected, the open source BSIM4V4 model for the purpose of demonstration is used. The simulator is discussed in detail and an algorithm for integration is provided which is then supported by the data from the simulation plots and experimental results for popular TFT configurations. The second part of the thesis illustrates the idea of using negative feedback achieved via contact resistance modulation to minimize the effect of VT shift in the drain current of the TFT. Analytical expressions are derived for the exact value of resistance needed to compensate for the VT shift entirely. Circuit to realize this resistance using TFTs is also provided. All these are experimentally verified using fabricated organic P-type Copper Phthalocyanine (CuPc) and inorganic N-type Tin doped Zinc Oxide (ZTO) TFTs. The third part of the thesis focuses on building a robust amplifier using these TFTs which has time invariant DC voltage level and small signal gain at the output. A differential amplifier using ZTO TFTs has been built and is shown to fit all these criteria. Ideas on vertical routing in an actual sensor actuator interface using this amplifier have also been discussed such that the whole system may be “tearable” in any contour. Such a sensor actuator interface can have varied applications including wrap around thermometers and X-ray machines.

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49

Rajachidambaram, Jaana Saranya. "Evaluation of amorphous oxide semiconductors for thin film transistors (TFTs) and resistive random access memory (RRAM) applications." Thesis, 2011. http://hdl.handle.net/1957/26517.

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Thin-film transistors (TFTs) are primarily used as a switching element in liquid crystal displays. Currently, amorphous silicon is the dominant TFT technology for displays, but higher performance TFTs will become necessary to enable ultra-definition resolution high-frequency large-area displays. Amorphous zinc tin oxide (ZTO) TFTs were fabricated by RF magnetron sputter deposition. In this study, the effect of both deposition and post annealing conditions have been evaluated in regards to film structure, composition, surface contamination, and device performance. Both the variation of oxygen partial pressure during deposition and the temperature of the post-deposition annealing were found to have a significant impact on TFT properties. X-ray diffraction data indicated that the ZTO films remain amorphous even after annealing to 600° C. Rutherford backscattering spectrometry indicated that the Zn:Sn ratio of the films was ~1.7:1 which is slightly tin rich compared to the sputter target composition. X-ray photoelectron spectroscopy data indicated that the films had significant surface contamination and that the Zn:Sn ratios changed depending on sample annealing conditions. Electrical characterization of ZTO films using TFT test structures indicated that mobilities as high as 17 cm² V⁻¹ s⁻¹ could be obtained for depletion mode devices. It was determined that the electrical properties of ZTO films can be precisely controlled by varying the deposition conditions and annealing temperature. It was found that the ZTO electrical properties could be controlled where insulating, semiconducting and conducting films could be prepared. This precise control of electrical properties allowed us to incorporate sputter deposited ZTO films into resistive random access memory (RRAM) devices. RRAM are two terminal nonvolatile data memory devices that are very promising for the replacement of silicon-based Flash. These devices exhibited resistive switching between high-resistance states to low-resistance states and low-resistance states to high-resistance states depending on polarity of applied voltages and current compliance settings. The device switching was fundamentally related to the defect states and material properties of metal and insulator layers, and their interfaces in the metalinsulator-metal (MIM) structure.
Graduation date: 2012
Access restricted to the OSU Community at author's request from Jan. 6, 2012 - Jan. 6, 2013

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50

Chung, Lung-Sheng, and 鍾隆陞. "The Ten Thin Film Transistor-Liquid Crystal Display(TFT-LCD) Manufacturers of Operating Analysis and Performance Assessment." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/99099373048102261857.

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碩士
開南大學
專案管理研究所
98
With the trend of rapid development in the digital information of the world，the product demand of information industry on light、thin and less-electricity leads the accelerated development of global thin film transistor-Liquid Crystal Display(TFT-LCD) manufacturers. Moreover, the main production line concentrates in South Korea and Taiwan and the sales volume of the global total output value is 83% approximately in the existing big factory of the thin film transistor-Liquid Crystal Display (TFT-LCD). TFT-LCD display has already been a main product of the information industry at present, in view of growing rapidly of demand in the world, the competition of TFT-LCD manufacturers have been a fierce phenomenon. The most important subject for administrator of every TFT-LCD manufacturer is how to make the best disposition of resources and create more and more profits. Korea and Japan TFT-LCD manufacturers are regarded as the research object in this research, via the relevant TFT-LCD manufacturer environmental trend analysis in the IEK and the public observation station and the public statement, and the annual financial statement in the 10 TFT-LCD manufacturers in the world; through the improvement of Data Envelopment Analysis (DEA) in order to measure the dynamic operation performance in Taiwan, Korea and Japan TFT-LCD manufacturers in 2002 to 2007. The survey results showed that the Innolux has the highest management accomplishment while the Toshiba comes up the last.

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