Relevant bibliographies by topics / Thin Film Transistors (TFT)

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Academic literature on the topic 'Thin Film Transistors (TFT)'

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Published: 6 September 2023

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Journal articles on the topic "Thin Film Transistors (TFT)"

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Park, Hyun-Woo, Sera Kwon, Aeran Song, Dukhyun Choi, and Kwun-Bum Chung. "Dynamics of bias instability in the tungsten-indium-zinc oxide thin film transistor." Journal of Materials Chemistry C 7, no. 4 (2019): 1006–13. http://dx.doi.org/10.1039/c8tc03585g.

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The key to full understanding of the degradation mechanism of oxide thin film transistors (Ox-TFTs) by gate bias stress is to investigate dynamical changes of the electron trap site at the channel region while a real-time gate bias is applied to the actual thin film transistor (TFT) structure.
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Pokharel, Peshal, and Lalita Shrestha. "Fabrication of Transparent Thin Film for Application of Thin Film Transistor (TFT) and Microelectronics." Himalayan Journal of Science and Technology 6, no. 1 (December 31, 2022): 22–28. http://dx.doi.org/10.3126/hijost.v6i1.50645.

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A thin-film transistor (TFT) is a special type of metal-oxide-semiconductor field-effect transistor (MOSFET) made by coating an insulating substrate with layers of an active semiconductor layer, metallic contacts, and the dielectric layer. FET transistors consist of three main components: source, gate, and drain. The main objective of the work is to fabricate the channel component by growing the ZnO nanostructure on the glass substrate using spin coating and spray pyrolysis methods. Thin films of zinc oxide (ZnO) were deposited on glass substrates by spin coating techniques from a precursor solution containing zinc acetate, ethanol and hydroxide of ammonia. After deposition, the films were centrifuged and evaporated. The application of spray pyrolysis has been used to deposit a wide variety of thin films, which are used in a variety of devices, such as solar cells, sensors and solid oxide fuel cells. It has been observed that the properties of the deposited thin films often depend on the preparation conditions; concentration levels of the precursor solution, coating time, electrical and optical properties of the glass substrate, etc. The average resistance of the sheet of samples F1, F5, F52, and F57 was 8.7 Ω, 9.14 Ω, 8.9 Ω and 9.42 Ω and of the samples, F2, F29, F39, and F53 were 9.5 Ω, 9.3 Ω, 9.9 Ω, 10.0 Ω respectively, at a growth temperature of 3400C. The thin films of ZnO were found to be highly transparent between the visible and near-infrared regions of the electromagnetic spectrum and the transmission of each sample decreases with three layers of ZnO seed layer. The decrease in the transmission of the samples confirms the coating of the ZnO seed layer on it. This work has demonstrated that transparent thin films can be fabricated using local techniques developed from locally available materials using less harmful chemical reagents such as zinc acetate. Such fabricated films are optically absorptive and inherently transmissive, further suggesting that they can be used as a channel material in thin film transistors.
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Manoli, Kyriaki, Preethi Seshadri, Mandeep Singh, Cinzia Di Franco, Angelo Nacci, Gerardo Palazzo, and Luisa Torsi. "Solvent-gated thin-film-transistors." Physical Chemistry Chemical Physics 19, no. 31 (2017): 20573–81. http://dx.doi.org/10.1039/c7cp03262e.

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TFTs gated through highly polar solvents have a salt independent response while for low polarity solvents the TFT current increases with salt. This was accounted for by the different contributions of Helmholtz and Guy-Chapman electrical double layers to the capacitance.
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Kuo, Yue. "(Invited) Oxide TFT Applications: Principles and Challenges." ECS Meeting Abstracts MA2022-02, no. 35 (October 9, 2022): 1285. http://dx.doi.org/10.1149/ma2022-02351285mtgabs.

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The main advantage of the thin film transistor (TFT) is that it can be fabricated on non-wafer substrate independent of the size, flexibility, and morphology. All composing films of the TFT are deposited at the low temperature. Therefore, TFTs can be applied to a broad range of consumer, biological, chemical, and optical products that are difficult to fabricate with the wafer based MOSFETs. There are many reports on a-Si:H and poly-Si TFT applications in displays, imagers, sensors, drivers, flexible electronics, and circuits (1,2). In principle, oxide TFTs can be applied to similar products. However, since the device characteristics and compositing materials of the oxide TFT are different from those of the a-Si:H and poly- Si TFTs, as shown in Figure 1 and Table 1, there are advantages and disadvantages in former’s applications. In this presentation, oxide TFT applications in the following three areas will be discussed. Control of the attached device, such as pixel-driving in displays, Integrated circuits, such as drivers or inverters, and Changing of characteristics with environment, such as pH, optical, and temperature sensors. L. Antonuk, Chapt. 10, and Y. Kuo, Chapt. 11, Amorphous Silicon Thin Film Transistors, pp. 395-505, Kluwer Academic Publishers, 2004. B.-D. Choi, et al., Chapt. 11-13, Polycrystalline Silicon Thin Film Transistors, Y. Kuo Editor, pp. 360-495, Kluwer Academic Publishers, 2004. Kuo and G. W. Chang, ECS Trans, 64(10), 145-153 (2014). Figure 1
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Mądzik, Mateusz Tomasz, Elangovan Elamurugu, Raquel Flores, and Jaime Viegas. "Impact of glycerol on Zinc Oxide based thin film transistors with Indium Molybdenum Oxide electrodes." MRS Advances 1, no. 4 (2016): 265–68. http://dx.doi.org/10.1557/adv.2016.26.

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ABSTRACTThin-film transistors (TFT) were fabricated at a room-temperature (RT) with zinc oxide (ZnO) channel and indium molybdenum oxide (IMO) electrodes. To isolate the gate oxide and gate electrode influence on the device performance, common gate configuration on a commercial substrate with thermal SiO2 (100 nm) was selected. A threshold voltage (VTh) of 10 V and ION/IOFF ratio of 1 × 10-5 were obtained. Once the reference data was taken transistors were exposed to glycerol. Temporary changes in device characteristics were observed due to the influence of glycerol, a low conductivity medium. To exclude the possibility of sugar alcohol being the main conductor, measurement on dummy transistor electrode was performed retaining the distance between probes. The TFT device under test revealed ten times higher drain current but also a change in threshold voltage and leakage current. Transistors under glycerol influence were always open with the positive gate bias.
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Yan, Xingzhen, Kai Shi, Xuefeng Chu, Fan Yang, Yaodan Chi, and Xiaotian Yang. "Stepped Annealed Inkjet-Printed InGaZnO Thin-Film Transistors." Coatings 9, no. 10 (September 27, 2019): 619. http://dx.doi.org/10.3390/coatings9100619.

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The preparation of thin-film transistors (TFTs) using ink-jet printing technology can reduce the complexity and material wastage of traditional TFT fabrication technologies. We prepared channel inks suitable for printing with different molar ratios of their constituent elements. Through the spin-coated and etching method, two different types of TFTs designated as depletion and enhancement mode were obtained simply by controlling the molar ratios of the InGaZnO channel elements. To overcome the problem of patterned films being prone to fracture during high-temperature annealing, a stepped annealing method is proposed to remove organic molecules from the channel layer and to improve the properties of the patterned films. The different interfaces between the insulation layers, channel layers, and drain/source electrodes were processed by argon plasma. This was done to improve the printing accuracy of the patterned InGaZnO channel layers, drain, and source electrodes, as well as to optimize the printing thickness of channel layers, reduce the defect density, and, ultimately, enhance the electrical performance of printed TFT devices.
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Gu, Guiru, Yunfeng Ling, Runyu Liu, Puminun Vasinajindakaw, Xuejun Lu, Carissa S. Jones, Wu-Sheng Shih, et al. "All-Printed Thin-Film Transistor Based on Purified Single-Walled Carbon Nanotubes with Linear Response." Journal of Nanotechnology 2011 (2011): 1–4. http://dx.doi.org/10.1155/2011/823680.

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We report an all-printed thin-film transistor (TFT) on a polyimide substrate with linear transconductance response. The TFT is based on our purified single-walled carbon nanotube (SWCNT) solution that is primarily consists of semiconducting carbon nanotubes (CNTs) with low metal impurities. The all-printed TFT exhibits a high ON/OFF ratio of around 103and bias-independent transconductance over a certain gate bias range. Such bias-independent transconductance property is different from that of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the special band structure and the one-dimensional (1D) quantum confined density of state (DOS) of CNTs. The bias-independent transconductance promises modulation linearity for analog electronics.
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Nagamatsu, Shuichi, Masataka Ishida, Shougo Miyajima, and Shyam S. Pandey. "P3HT Nanofibrils Thin-Film Transistors by Adsorbing Deposition in Suspension." Materials 12, no. 21 (November 5, 2019): 3643. http://dx.doi.org/10.3390/ma12213643.

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A novel film preparation method utilizing polymer suspension, entitled adsorbing deposition in suspensions (ADS), has been proposed. The poly(3-hexylthiophene) (P3HT) toluene solution forms P3HT nanofibrils dispersed suspension by aging. P3HT nanofibrils are highly crystallized with sharp vibronic absorption spectra. By the ADS method, only P3HT nanofibrils in suspension can be deposited on the substrate surface without any disordered fraction from the dissolved P3HT in suspension. Formed ADS film contains only the nanostructured conjugated polymer. Fabricated polymer thin-film transistor (TFT) utilizing ADS P3HT film shows good TFT performances with low off current, narrow subthreshold swing and large on/off current ratio.
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Furuta, Mamoru, and Yusaku Magari. "(Invited, Digital Presentation) Nondegenerate Hydrogen-Doped Polycrystalline Indium Oxide (InOx:H) Thin Films for High-Mobility Thin Film Transistors." ECS Meeting Abstracts MA2022-02, no. 35 (October 9, 2022): 1266. http://dx.doi.org/10.1149/ma2022-02351266mtgabs.

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Transparent metal oxide semiconductors (OSs) have been extensively investigated for use as the active channel layer of thin film transistors (TFTs) for next-generation flat-panel displays, nonvolatile memories, image sensors, and pH sensors, to name a few. Among OSs, the amorphous In–Ga–Zn–O (IGZO) has attracted particular attention for TFT applications owing to its high field effect mobility (μFE) of more than 10 cm2V−1s−1, steep subthreshold swing (S.S.), extremely low off-state current, large-area uniformity, and good bias stress stability. Although the μFE of an IGZO TFT is approximately one order of magnitude higher than that of an amorphous Si TFT, further improvement of the μFE of OS TFTs is required to expand their range of applications as an alternative to polycrystalline Si TFT. Single-crystalline In2O3 has a Hall mobility as high as 160 cm2V−1s−1, which makes amorphous (a-) or polycrystalline (poly-) InOx a potential material for enhancing the μFE of OS TFTs. However, undoped InOx thin films is known as a degenerate semiconductor with high background electron density of over 1020 cm-3, which is attributed to the presence of native defects, such as oxygen vacancies, making them unsuitable for a channel material of OS TFTs. In this presentation, nondegenerate hydrogen-doped polycrystalline InOx (poly-InOx:H) thin films were successfully prepared by low-temperature solid phase crystallization (SPC). A degenerate amorphous InOx:H thin film was deposited by sputtering in Ar, O2, and H2 gases, and an amorphous to polycrystalline phase transition (SPC) of the film was achieved after PDA at more than 175 °C. By PDA at 250 °C in air, a nondegenerate poly-InOx:H film could be obtained with a carrier density as low as 2.4 × 1017 cm−3, which is approximately three orders of magnitude lower than that of the initial a-InOx:H film. The TFTs with a 50 nm thick nondegenerate poly-InOx:H channel could be fully depleted by a gate electric field. A maximum μFE of 125.7 cm2V−1s−1 was exhibited by the TFT with the poly-InOx:H channel. The use of a nondegenerate poly-InOx:H film is a promising approach to boost the μFE of OS TFTs.
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Shin, Seung Won, Jae Eun Cho, Hyun-Mo Lee, Jin-Seong Park, and Seong Jun Kang. "Photoresponses of InSnGaO and InGaZnO thin-film transistors." RSC Advances 6, no. 87 (2016): 83529–33. http://dx.doi.org/10.1039/c6ra17896k.

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ITGO TFT were fabricated to study the photoresponses of indium-based oxide semiconductors. We found that the increased amount and low electron binding energy of indium can improve the recovery time of ITGO TFTs.
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Dissertations / Theses on the topic "Thin Film Transistors (TFT)"

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Hein, Moritz. "Organic Thin-Film Transistors." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-167894.

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Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.
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Dong, Hanpeng. "Microcrystalline silicon based thin film transistors fabricated on flexible substrate." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S173/document.

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Le travail de cette thèse porte sur le développement de transistors en couche mince (Thin Film Transistors, TFTs) à base de silicium microcristallin fabriqués sur un substrat flexible à très basse température (T< 180 °C). La première partie de ce travail a consisté à étudier la stabilité électrique de ces TFTs. L'étude de la stabilité électrique des TFTs de type N fabriqués sur verre a montré que ces TFTs sont assez stables, la tension de seuil VTH ne se décale que de 1.2 V au bout de 4 heures de stress sous une tension de grille VGSstress= +50V et à une température T=50 °C. L'instabilité électrique de ces TFTs est principalement causée par le piégeage des porteurs dans l'isolant de grille. La deuxième étape de ce travail s'est concentrée sur l'étude du comportement de ces TFTs sous déformation mécanique. Ces TFTs sont soumis à un stress mécanique en tension et en compression. Le rayon de courbure minimum que les TFTs pouvaient supporter est r=1.5 mm en tension et en compression. La limitation de la déformation mécanique de ces TFTs est principalement due à la contrainte mécanique du nitrure de silicium utilisé comme isolant de grille des TFTs. Autrement dit, ces TFTs sont mécaniquement fiables et présentes une faible variation du courant ION, de l'ordre de 1%, même après 200 cycles de déformation mécanique. Ces résultats obtenus laissent entrevoir la possibilité de concevoir une électronique flexible pouvant être pliée en 2. Enfin, les TFTs sont fabriqués avec différents isolants de grille afin d'augmenter la mobilité d'effet de champ. Malheureusement, aucun isolant de grille utilisé dans ces études n'a permis d'augmenter la mobilité d'effet de champ sans dégrader la stabilité électrique des TFTs. Des études plus détaillées et des optimisations complémentaires sur ces isolants de grille sont nécessaires
This work deals with the development of microcrystalline silicon thin film transistors (TFTs) fabricated on flexible substrate at low temperature (T=180 °C). The first step of this work consists in studying the electrical stability of TFTs. The N-type TFTs fabricated on glass substrate are electrically stable under gate bias stress VGStress= +50V at T=50 °C. The threshold voltage shift (ΔVTH) was only 1.2 V during 4 hours. This electrical instability of TFTs is mainly due to carrier trapping inside the silicon nitride gate insulator. The second step of this work lies in the study of the mechanical behavior of the TFTs. Both tensile and compressive strains were applied on TFTs. The minimum curvature radius is r=1.5 mm for both tension and compression. The main limitation of TFTs comes from the mechanical strain εlimit of silicon nitride used as gate insulator of TFTs. Also, these TFTs are mechanically reliable: the variation of ION current was only 1% after 200 cycles mechanical bending. These results obtained open the way to the development of flexible electronics that can be folded in half.Finally, TFTs have been fabricated using different gate insulators in order to improve the mobility. Unfortunately, all the gate insulators used couldn’t improve mobility without sacrificing electrical stability of TFT. More detailed studies and complementary optimization of these gate insulators are necessary
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Ho, Tsz Kin. "Design of TFT circuit and touchscreen electronics /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20HO.

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Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device." Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.

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n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.
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Rossi, Leonardo. "Flexible oxide thin film transistors: fabrication and photoresponse." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/14542/.

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Gli ossidi amorfi semiconduttori (AOS) sono nuovi candidati per l’elettronica flessibile e su grandi aree: grazie ai loro legami prevalentemente ionici hanno una mobilità relativamente alta (µ > 10cm^2/Vs) anche nella fase amorfa. Transistor a film sottile (TFT) basati sugli AOS saranno quindi più performanti di tecnologie a base di a-Si e più economici di quelle a base di silicio policristallino. Essendo amorfi, possono essere depositati a basse temperature e su substrati polimerici, caratteristica chiave per l’elettronica flessibile e su grandi aree. Per questa tesi, diversi TFT sono stati fabbricati e caratterizzati nei laboratori del CENIMAT all’Università Nova di Lisbona sotto la supervisione del Prof. P. Barquinha. Questi dispositivi sono composti di contatti in molibdeno, un canale semiconduttivo di ossido di zinco, gallio e indio (IGZO) e un dielettrico composto da 7 strati alternati di SiO2 e SiO2+Ta2O5. Tutti i dispositivi sono stati depositati mediante sputtering su sostrati flessibili (fogli di PEN). Le misure tensione-corrente mostrano che i dispositivi mantengono alte mobilità (decine di 10cm^2/Vs) anche quando fabbricati a temperature inferiori a 200°C. Si è analizzato il funzionamento dei dispositivi come fototransistor rilevando la risposta alla luce ultravioletta e in particolare la loro responsività e spostamento della tensione di soglia in funzione della lunghezza d’onda incidente. Questi risultati consentono di formulare ipotesi sul comportamento dei dispositivi alla scala microscopica. In particolare, indicano che i) la mobilità del canale non è influenzata dall’illuminazione, ii) sia l'IGZO sia il Ta2O5 contribuiscono al processo di fotoconduttività e iii) il processo di fotogenerazione non è adiabatico. La tesi contiene inoltre una descrizione del processo di ricombinazione e presenta un’applicazione pratica di tali dispositivi in un circuito per RFID. Infine, esplora la possibilità di migliorarne la flessibilità e le prestazioni.
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Fratelli, Ilaria. "Flexible oxide thin film transistors: device fabrication and kelvin probe force microscopy analysis." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/13538/.

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I transistor a film sottile basati su ossidi amorfi semiconduttori sono ottimi candidati nell'ambito dell'elettronica su larga scala. Al contrario delle tecnologie basate su a-Si:H a poly-Si, gli AOS presentano un'elevata mobilità elettrica (m > 10 cm^2/ Vs) nonostante la struttura amorfa. Inoltre, la possibilità di depositare AOS a basse temperature e su substrati polimerici, permette il loro impiego nel campo dell'elettronica flessibile. Al fine di migliorare questa tecnologia, numerosi TFT basati su AOS sono stati fabbricati durante 4 mesi di attività all'Università Nova di Lisbona. Tutti i transistor presentano un canale formato da a-GIZO, mentre il dielettrico è stato realizzato con due materiali differenti: Parylene (organico) e 7 strati alternati di SiO2 e SiO2 + Ta2O5. I dispositivi sono stati realizzati su substrati flessibili sviluppando una nuova tecnica per la laminazione e la delaminazione di fogli di PEN su supporto rigido. L'ottimizzazione del processo di fabbricazione ha permesso la realizzazione di dispositivi che presentano caratteristiche paragonabili a quelle previste per TFT costruiti su substrati rigidi (m = 35.7 cm^2/Vs; VON = -0.10 V; S = 0.084 V/dec). Al Dipartimento di Fisica dell'UNIBO, l'utilizzo del KPFM ha permesso lo studio a livello microscopico delle prestazioni presentate dai dispositivi analizzati. Grazie a questa tecnica di indagine, è stato possibile analizzare l'impatto delle resistenze di contatto sui dispositivi meno performanti e identificare l'esistenza di cariche intrappolate nei TFT basati su Parylene. Gli ottimi risultati ottenuti dall'analisi KPFM suggeriscono un futuro impiego di questa tecnica per lo studio del legame tra stress meccanico e degradazione elettrica dei dispositivi. Infatti, la comprensione dei fenomeni microscopici dovuti alla deformazione strutturale sarà un passaggio indispensabile per lo sviluppo dell'elettronica flessibile.
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Jakob, Markus Prüfer. "Compact DC Modelling of Short-Channel Effects in Organic Thin-Film Transistors." Doctoral thesis, Universitat Rovira i Virgili, 2022. http://hdl.handle.net/10803/673905.

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Els transistors orgànics de capa fina (TFT) són dispositius prometedors per a les pantalles flexibles de matriu activa i els conjunts de sensors, ja que poden fabricar-se a temperatures de procés relativament baixes i, per tant, no sols en vidre, sinó també en substrats polimèrics. Per a millorar el rendiment dinàmic dels dispositius i circuits TFT , una reducció agressiva de la longitud de canal provoca efectes extrínsecs en els dispositius que han de ser capturats per models compactes. Aquesta tesi presenta models analítics, basats en la física, de la degradació de la pendent subumbral, el roll-off del voltatge llindar i l'efecte DIBL en TFTs coplanars i escalonats que poden ser implementats en qualsevol model compacte de corrent continu arbitrari que estigui definit pel voltatge llindar i la pendent subumbral. Per tant, l'equació diferencial de Laplace es resol per a la geometria coplanar i escalonada aplicant la transformación Schwarz-Cristoffel. Les solucions del potencial serveixen de base per a la definició de les equacions del model. A més, es desenvolupen models compactes de les barreres Schottky dependents de la polarització en les interfícies font/semiconductor i drenador/semiconductor en els TFT coplanars i escalonats, que modelen la injecció i l'ejecció de portadors de càrrega, respectivament, com a corrent d'emissió termoiònica.
Los transistores orgánicos de capa fina (TFT) son dispositivos prometedores para las pantallas flexibles de matriz activa y los conjuntos de sensores, ya que pueden fabricarse a temperaturas de proceso relativamente bajas y, por tanto, no sólo en vidrio, sino también en sustratos poliméricos. Para mejorar el rendimiento dinámico de los dispositivos y circuitos TFT, una reducción agresiva de la longitud de los canales provoca efectos extrínsecos en los dispositivos que tienen que ser capturados por modelos compactos. Esta tesis presenta modelos analíticos, basados en la física, de la degradación de la pendiente subumbral, el roll-off del voltaje umbral y el efecto DIBL en TFTs coplanares y escalonados que pueden ser implementados en cualquier modelo compacto de corriente continua arbitrario que esté definido por el voltaje umbral y la pendiente subumbral. Por lo tanto, la ecuación diferencial de Laplace se resuelve para la geometría coplanar y escalonada aplicando la transformación Schwarz-Christoffel. Las soluciones del potencial sirven de base para la definición de las ecuaciones del modelo. Además, se desarrollan modelos compactos de las barreras Schottky dependientes de la polarización en las interfaces fuente/semiconductor y drenador/semiconductor en los TFT coplanares y escalonados, que modelan la inyección y la eyección de portadores de carga, respectivamente, como corriente de emisión termoiónica
Organic thin-film transistors (TFTs) are promising devices for flexible active-matrix displays and sensor arrays, since they can be fabricated at relatively low process temperatures and thus not only on glass, but also on polymeric substrates. In order to improve the dynamic TFT and circuit performance, an aggressive reduction of the channel length causes extrinsic de-vice effects that have to be captured by compact models. This dissertation presents analytical, physics-based models of the subthreshold-swing degra-dation, the thresholdvoltage roll-off and DIBL effects in coplanar and staggered TFTs that can be implemented in any arbitrary compact dc model that are defined by the threshold voltage and the subthreshold swing. Therefore, Laplace’s differential equation is solved for the coplanar and staggered geometry by applying the Schwarz-Christoffel transformation. The potential solutions serve as a basis for the definition of the model equations. Further-more, compact models of the biasdependent Schottky barriers at the source/semiconductor and drain/semiconductor interfaces in coplanar and staggered TFTs are derived, which model the charge carriers injection and ejection, respectively, as thermionic emission cur-rent. Thereby, in case of the source barrier, the Schottky barrier lowering effect due to im-age charges is captured and therefore, an analytical expression of the electric field at the source barrier is derived.
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Dosev, Dosi Konstantinov. "Fabrication, characterisation and modelling of nanocrystalline silicon thin-film transistors obtained by hot-wire chemical vapour deposition." Doctoral thesis, Universitat Politècnica de Catalunya, 2003. http://hdl.handle.net/10803/6324.

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Hot-wire chemical vapour deposition (HWCVD) is a promising technique that permits polycrystalline silicon films with grain size of nanometers to be obtained at high deposition rates and low substrate temperatures. This material is expected to have better electronic properties than the commonly used amorphous hydrogenated silicon (a-Si:H).

In this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.

The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.

The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.
Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions.

The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.
We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.
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Noring, Martin. "To automatically estimate the surface area coverage of carbon nanotubes on thin film transistors with image analysis : Bachelor’s degree project report." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-157168.

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This report discuss the developement of a MATLAB-based tool for the analysis ofsurface area coverage of carbon nanotube networks from atomic force microscopyimages. The tool was compared with a manual method and the conclusion was that ithas, at least, the same accuracy as the manual mehtod, and it needs much less time forthe analysis. The tool couldn’t analyze images of carbon nanotube networks if theimages were to noisy or the networks to dense. The tool can help in the research ofthin-film transistors with carbon nanotube networks as the semiconducting channelmaterial.
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Zhu, Lei. "Modeling of a-Si:H TFT I-V Characteristics in the Forward Subthreshold Operation." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/868.

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The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.
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Books on the topic "Thin Film Transistors (TFT)"

1

Tsukada, Toshihisa. TFT/LCD: Liquid-crystal displays addressed by thin-film transistors. Amsterdam: Gordon and Breach, 1996.

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Hakumaku toranjisuta gijutsu no subete: Kōzō, tokusei, seizō purosesu kara jisedai TFT made = Thin film transistor. Tōkyō: Kōgyō Chōsakai, 2007.

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Aoki, Hitoshi. Dynamic characterization of a-Si TFT-LCD pixels. Palo Alto, CA: Hewlett-Packard Laboratories, Technical Publications Department, 1996.

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Tsukada, Toshihisa. TFT/LCD: Liquid-crystal displays addressed by thin-film transistors. Amsterdam: Gordon and Breach, 1996.

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Taiwan de jing tan hao: Tai Ri Han TFT shi ji zhi zheng. Taiabei Shi: Shi bao wen hua chu ban qi ye gu fen you xian gong si, 2004.

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Bo mo jing ti guan (TFT) zhen lie zhi zao ji shu. Shanghai Shi: Fu dan da xue chu ban she, 2007.

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Maeda, Shigenobu. Teishōhi denryoku kōsoku MOSFET gijutsu: Takesshō shirikon TFT fukagata SRAM to SOI debaisu. Tōkyō: Sipec, 2002.

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International Workshop on Active Matrix Liquid Crystal Displays (2001 Tokyo, Japan). AM-LCD 01: Digest of technical papers : 2001 International Workshop on Active Matrix Liquid Crystal Displays, TFT technologies and related materials, July 11-13, 2001, Kogakuin University, Tokyo, Japan. [Kobe, Japan]: Japan Society of Applied Physics, 2001.

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International Workshop on Active Matrix Liquid Crystal Displays (1999 Tokyo, Japan). AM-LCD 99: Digest of technical papers :1999 International Workshop on Active Matrix Liquid Crystal Displays, TFT technologies and related materials, July 14-16, 1999, Kogakuin University, Tokyo, Japan. [Kobe, Japan]: Japan Society of Applied Physics, 1999.

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Brotherton, S. D. Introduction to Thin Film Transistors: Physics and Technology of TFTs. Heidelberg: Springer International Publishing, 2013.

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Book chapters on the topic "Thin Film Transistors (TFT)"

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Ishihara, Ryoichi. "Poly-Si TFT Structures." In Thin Film Transistors, 670–700. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_15.

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Choi, Byong-Deok, Inhwan Lee, and Oh-Kyong Kwon. "Poly-Si TFT Drivers." In Thin Film Transistors, 885–949. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_22.

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Kuo, Yue. "a-Si:H TFT Structures." In Thin Film Transistors, 183–202. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_4.

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Kuo, Yue. "Poly-Si TFT for non-LCD Applications." In Thin Film Transistors, 989–1021. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_24.

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Flewitt, Andrew J., and William I. Milne. "a-Si:H TFT Thin Film and Substrate Materials." In Thin Film Transistors, 15–78. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_2.

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Higashi, Seiichiro. "Process Integration Issues for Poly-Si TFT Fabrication." In Thin Film Transistors, 849–83. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_21.

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Kuo, Yue. "Plasma Etching in a-Si:H TFT Array Fabrication." In Thin Film Transistors, 273–312. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_7.

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Matsumura, Hideki, Akira Izumi, and Atsushi Masuda. "Catalytic Chemical Vapor Deposition of a-Si:H TFT." In Thin Film Transistors, 377–94. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_9.

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Kuo, Yue. "Deposition of Dielectric Thin Films for a-Si:H TFT." In Thin Film Transistors, 241–71. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_6.

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Brotherton, S. D. "Poly-Si TFT Performance." In Introduction to Thin Film Transistors, 253–300. Heidelberg: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-00002-2_8.

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Conference papers on the topic "Thin Film Transistors (TFT)"

1

Colli, A. "Thin film transistors on nanostructured layers prepared by nanowire lithography." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379875.

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Tang, Wei, Jiaqing Zhao, Qiaofeng Li, and Xiaojun Guo. "Highly Sensitive Low Power Ion-sensitive Organic Thin-Film Transistors." In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT). IEEE, 2018. http://dx.doi.org/10.1109/cad-tft.2018.8608054.

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Chen, Yonghua, Zhinong Yu, Xuyang Li, and Jin Cheng. "Low-Temperature Fabrication of Solution-Processed InGaZnO Thin-Film Transistors." In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT). IEEE, 2018. http://dx.doi.org/10.1109/cad-tft.2018.8608055.

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Lv, Nannan, Zening Wang, Lei Lu, and Mingxiang Wang. "Structure Optimization on Elevated-Metal a-InGaZnO Thin Film Transistors." In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT). IEEE, 2018. http://dx.doi.org/10.1109/cad-tft.2018.8608105.

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Wu, Yue, Weina Yong, Chia-Yu Lee, and Hang Zhou. "An Asymmetric Metal Electrode for TFT-LCDs." In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT). IEEE, 2018. http://dx.doi.org/10.1109/cad-tft.2018.8608114.

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Adl, Ahmad Hossein, Samira Farsinezhad, Alex Ma, Douglas W. Barlage, and Karthik Shankar. "High Performance Zinc Oxide Thin Film Transistors Through Improved Material Processing and Device Design." In ASME 2014 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2014. http://dx.doi.org/10.1115/imece2014-36941.

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Solution processing (SP) is a cheap, simple and high-throughput method for the fabrication of ZnO thin film transistors (TFTs). Lack of enhancement mode operation, poor crystallinity, traps, and poor control of the carrier concentration are some of the disadvantages of this method. The high intrinsic electron concentration of SP-ZnO makes saturation of TFTs non-trivial. We report on Schottky barrier thin film transistors (SB-TFT). By biasing the source Schottky contact in reverse bias, a depletion region is formed around the source contact hence depleting the region from the free charge carriers which produces the saturation of the device. The effect of the Schottky contact is illustrated by comparing the operation of SB-TFTs with that of conventional TFTs.
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Zhou, Yongkai, Shik Lin Lee, Chao Fu, Younan Hua, and Xiaomin Li. "Fault Isolation and TEM Study in State-of-Art Thin-Film Transistors." In ISTFA 2015. ASM International, 2015. http://dx.doi.org/10.31399/asm.cp.istfa2015p0374.

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Abstract In this work, we discussed the fault isolation method for the Thin-Film Transistor (TFT). Many defects in the TFT can be directly observed by optical microscope; however, some defects are not visible in either optical microscope or SEM making the fault isolation effort very challenging. We demonstrated that OBIRCH can be used to find defect locations in TFT failures for leakage and shorts. The TFT is so fragile that the laser power and biasing voltage have to be very carefully controlled to avoid damaging the TFT. After identifying the defect location by OBIRCH hot spot detection, the defect was successfully captured with TEM analysis.
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He, Yongli, Ya Gao, Zehua Liu, Jie Luo, Chenxi Zhang, and Qing Wan. "Indium-Zinc-Oxide Electric-Double-Layer Thin-Film Transistors for Humidity Sensing." In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT). IEEE, 2018. http://dx.doi.org/10.1109/cad-tft.2018.8608110.

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Zhong, Wei, Guoyuan Li, and Rongsheng Chen. "Vapor-phase self-assembled monolayer on InSnZnO Thin-Film Transistors for enhanced performance." In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT). IEEE, 2018. http://dx.doi.org/10.1109/cad-tft.2018.8608102.

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Deng, Xuan, Yuqing Zhang, Haishi Fu, and Shengdong Zhang. "High mobility metal-oxide thin film transistors with IGZO/In2O3 dual-channel structure." In 2018 9th International Conference on Computer Aided Design for Thin-Film Transistors (CAD-TFT). IEEE, 2018. http://dx.doi.org/10.1109/cad-tft.2018.8608103.

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Reports on the topic "Thin Film Transistors (TFT)"

1

Ray, Asim K. Design of Novel Organic Thin Film Transistors for Wearable Electronics. Fort Belvoir, VA: Defense Technical Information Center, August 2012. http://dx.doi.org/10.21236/ada565909.

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Hatalis, Miliadis K. Low Temperature Polysilicon Thin Film Transistors in Advanced Display Technologies. Fort Belvoir, VA: Defense Technical Information Center, September 2000. http://dx.doi.org/10.21236/ada388339.

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Park, Chan E. Nanocomposite Gate Dielectrics With Nanoparticles for Organic Thin Film Transistors. Fort Belvoir, VA: Defense Technical Information Center, September 2006. http://dx.doi.org/10.21236/ada473096.

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