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Calhoun, Kenneth Harold. "Thin film compound semiconductor devices for photonic interconnects." Diss., Georgia Institute of Technology, 1993. http://hdl.handle.net/1853/15478.
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Modi, Mitul B. "Fracture in stress engineered, high density, thin film interconnects." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/16336.
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Zheng, Jiantao. "Interfacial fracture of micro thin film interconnects under monotonic and cyclic loading." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26489.
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Thesis (Ph. D.)--Mechanical Engineering, Georgia Institute of Technology, 2009.Committee Chair: Sitaraman, Suresh; Committee Member: Degertekin, Levent; Committee Member: McDowell, David; Committee Member: Tummala, Rao; Committee Member: Vandentop, Gilroy; Committee Member: Wang, Zhong Lin. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Au, Yeung Billy. "Chemical Vapor Deposition of Thin Film Materials for Copper Interconnects in Microelectronics." Thesis, Harvard University, 2012. http://dissertations.umi.com/gsas.harvard:10227.
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The packing density of microelectronic devices has increased exponentially over the past four decades. Continuous enhancements in device performance and functionality have been achieved by the introduction of new materials and fabrication techniques. This thesis summarizes the thin film materials and metallization processes by chemical vapor deposition (CVD) developed during my graduate study with Professor Gordon at Harvard University. These materials and processes have the potential to build future generations of microelectronic devices with higher speeds and longer lifetimes. Manganese Silicate Diffusion Barrier: Highly conformal, amorphous and insulating manganese silicate \((MnSi_xO_y)\) layers are formed along the walls of trenches in interconnects by CVD using a manganese amidinate precursor vapor that reacts with the surfaces of the insulators. These \((MnSi_xO_y)\) layers are excellent barriers to diffusion of copper, oxygen and water.
Manganese Capping Layer: A selective CVD manganese capping process strengthens the interface between copper and dielectric insulators to improve the electromigration reliability of the interconnects. High selectivity is achieved by deactivating the insulator surfaces using vapors containing reactive methylsilyl groups. Manganese at the Cu/insulator interface greatly increases the strength of adhesion between the copper and the insulator. Bottom-up Filling of Copper and Alloy in Narrow Features: Narrow trenches, with widths narrow than 30 nm and aspect ratios up to 9:1, can be filled with copper or copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. A conformal manganese nitride \((Mn_4N)\) layer serves as a diffusion barrier and adhesion layer. Iodine atoms chemisorb on the \(Mn_4N\) layer and are then released to act as a catalytic surfactant on the surface of the growing copper layer to achieve void-free, bottom-up filling. Upon post-annealing, manganese in the alloy diffuses out from the copper and forms a self-aligned barrier in the surface of the insulator. Conformal Seed Layers for Plating Through-Silicon Vias: Through-silicon vias (TSV) will speed up interconnections between chips. Conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1 can be prepared using vapor deposition techniques. \(Mn_4N\) is deposited conformally on the silica surface by CVD to provide strong adhesion at Cu/insulator interface. Conformal copper or Cu-Mn alloy seed layers are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process.Chemistry and Chemical Biology
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Seo, Sang-Woo. "Development of thin film photodetectors and their applications multispectral detection and high speed optical interconnections /." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180408/unrestricted/seo%5fsang-woo%5f200312%5fphd.pdf.
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Ginga, Nicholas J. "On-chip dielectric cohesive fracture characterization and mitigation investigation through off-chip carbon nanotube interconnects." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52225.
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The cohesive fracture of thin films is a concern for the reliability of many devices in microelectronics, MEMS, photovoltaics, and other applications. In microelectronic packaging the cohesive fracture toughness has become a concern with new low-k dielectric materials currently being used. To obtain the low-k values needed to meet electrical performance goals, the mechanical strength of the material has decreased. This has resulted in cohesive cracks occurring in the Back End of Line (BEoL) dielectric layers of the microelectronic packages. These cracks lead to electronic failures and occur after thermal loading (due to CTE mismatch of materials) and mechanical loading. To prevent these cohesive cracks, it is necessary to measure the cohesive fracture resistance of these thin films to implement during the design and analysis process. Many of the current tests to measure the cohesive fracture resistance of thin films are based on methods developed for larger scale specimens. These methods can be difficult to apply to thin films due to their size and require mechanical fixturing, physical contact near the crack tip, and complicated stress fields. Therefore, a fixtureless cohesive fracture resistance measurement technique has been developed that utilizes photolithography fabrication processes. This technique uses a superlayer thin film with a high intrinsic stress deposited on top of the desired test material to drive cohesive fracture through the thickness of test material. In addition to developing a technique to measure the fracture resistance of dielectric thin films, the use of carbon nanotube (CNT) forests as off-chip interconnects is investigated as a potential method to mitigate the fracture of these materials. The compressive and tensile modulus of CNT forests is characterized, and it is seen that the modulus is several orders of magnitude less than that of a single straight CNT. The low-modulus CNT forest will help mechanically decouple the chip from the board and reduce stress occurring in the dielectric layers as compared to the current technology of solder ball interconnects and therefore improve reliability. The mechanical performance of these CNT interconnects is investigated by creating a finite-element model of a flip chip electronic package utilizing CNT interconnects and comparing the chip stresses to a traditional solder ball interconnect scenario. Additionally, flip chips are fabricated with CNT forest interconnects, assembled to an FR4 substrate, and subjected to accelerated thermomechanical testing to experimentally investigate their performance.
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Crozier, M. L. "Development of a novel series interconnect for thin-film photovoltaics." Thesis, Heriot-Watt University, 2017. http://hdl.handle.net/10399/3228.
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Weaver, David John. "A study of graphoepitaxially grown Al and Cu interconnects." Thesis, University of York, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.265566.
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Wikström, Adam. "Modeling of stresses and deformation in thin film and interconnect line structures." Doctoral thesis, KTH, Solid Mechanics, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3224.
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Wikström, Adam. "Modeling of stresses and deformation in thin film and interconnect line structures /." Stockholm : Tekniska högsk, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3224.
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Yu, Lu. "Electroless Deposition of Copper and Copper-Manganese Alloy for Application in Interconnect Metallization." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1396521217.
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Cui, Xiaoyun. "Electroless metallisation of glass for electrical interconnect applications." Thesis, Loughborough University, 2009. https://dspace.lboro.ac.uk/2134/10303.
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The microelectronics industry requires continuous advances due to ever-evolving technology and the corresponding need for higher density substrates with smaller features. Specifically, new dielectric materials with enhanced electrical properties are needed. At the same time, adhesion must be maintained in order to preserve package reliability and mechanical performance. As a result, this research investigates the use of thin glass sheets as an alternative substrate material as it offers a number of advantages including coefficient of thermal expansion similar to silicon, good dielectric properties and optical transparency to assist in the alignment of buried features. As part of this project it was necessary to deposit metallic coatings onto the glass sheets to create electrical tracks, pads and microvias. In order to meet these requirements, the metallisation of both smooth as received glass surfaces and surfaces roughened by laser machining using electroless copper and nickel deposition were investigated. This study resulted in a number of important conclusions about the roles of chemical bonding and mechanical anchoring in both the adhesion and catalyst adsorption, that are key factors in the electroless metallisation process.....
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Sun, Tik. "Classical Size Effect in Copper Thin Films: Impact of Surface and Grain Boundary Scattering on Resistivity." Doctoral diss., Orlando, Fla. : University of Central Florida, 2009. http://purl.fcla.edu/fcla/etd/CFE0002959.
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Longworth, Hai Pham. "Microstructural modification of thin films and its relation to the electromigration-limited reliability of VLSI interconnects." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/13114.
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Nowrozi, Mojtaba Faiz. "A systematic study of LPCVD refractory metal/silicide interconnect materials for very large scale integrated circuits." Diss., The University of Arizona, 1988. http://hdl.handle.net/10150/184396.
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Recently, refractory materials have been proposed as a strong alternative to poly-silicon and aluminum alloys as metallization systems for Very Large Scale Integrated (VLSI) circuits because of their improved performance at smaller Integrated Circuit (IC) feature size and higher interconnect current densities. However, processing and reliability problems associated with the use of refractory materials have limited their widespread acceptance. The hot-wall low pressure chemical vapor deposition (LPCVD) of Molybdenum and Tungsten from their respective hexacarbonyl sources has been studied as a potential remedy to such problems, in addition to providing the potential for higher throughput and better step coverage. Using deposition chemistries based on carbonyl sources, Mo and W deposits have been characterized with respect to their electrical, mechanical, structural, and chemical properties as well as their compatibility with conventional IC processing. Excellent film step coverage and uniformity were obtained by low temperature (300-350 C) deposition at pressures of 400-600 mTorr. As-deposited films were observed to be amorphous, with a resistivity of 250 and 350 microohm-cm for Mo and W respectively. On annealing at high temperatures in a reducing or inert atmosphere, the films crystallize with attendant reduction in resistivity to 9.3 and 12 microohm-cm for Mo and W, respectively. The average grain size also increases as a function of time and temperature to a maximum of 2500-3000 A. The metals and their silicides that are deposited, using silane as silicon source, are integratable to form desired metal-silicide gate contact structures. Thus, use of the low resistivity of the elemental metal coupled with the oxidation resistance of its silicide manifests the quality and economy of the process. MOS capacitors with Mo and W as the gate material have been fabricated on n-type (100) silicon. A work function of 4.7 +/- 0.1 eV was measured by means of MOS capacitance-voltage techniques. The experimental results further indicate that the characteristics of W-gate MOS devices related to the charges in SiO₂ are comparable to those of poly-silicon; while, the resistivity is about two orders of magnitude lower than poly-silicon. It is therefore concluded that hot-wall low pressure chemical vapor deposition of Mo and W from their respective carbonyl sources is a viable technique for the deposition of reliable, high performance refractory metal/silicide contact and interconnect structures on very large scale integrated circuits.
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Mistkawi, Nabil George. "Fundamental Studies in Selective Wet Etching and Corrosion Processes for High-Performance Semiconductor Devices." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/6.
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As multistep, multilayer processing in semiconductor industry becomes more complex, the role of cleaning solutions and etching chemistries are becoming important in enhancing yield and in reducing defects. This thesis demonstrates successful formulations that exhibit copper and tungsten compatibility, and are capable of Inter Layer Dielectric (ILD) cleaning and selective Ti etching. The corrosion behavior of electrochemically deposited copper thin films in deareated and non-dearated cleaning solution containing hydrofluoric acid (HF) has been investigated. Potentiodynamic polarization experiments were carried out to determine active, active-passive, passive, and transpassive regions. Corrosion rates were calculated from tafel slopes. ICP-MS and potentiodynamic methods yielded comparable Cu dissolution rates. Interestingly, the presence of hydrogen peroxide in the cleaning solution led to more than an order of magnitude suppression of copper dissolution rate. We ascribe this phenomenon to the formation of interfacial CuO which dissolves at slower rate in dilute HF. A kinetic scheme involving cathodic reduction of oxygen and anodic oxidation of Cu0 and Cu+1 is proposed. It was determined that the reaction order kinetics is first order with respect to both HF and oxygen concentrations. The learnings from copper corrosion studies were leveraged to develop a wet etch/clean formulation for selective titanium etching. The introduction of titanium hard-mask (HM) for dual damascene patterning of copper interconnects created a unique application in selective wet etch chemistry. A formulation that addresses the selectivity requirements was not available and was developed during the course of this dissertation. This chemical formulation selectively strips Ti HM film and removes post plasma etch polymer/residue while suppressing the etch rate of tungsten, copper, silicon oxide, silicon carbide, silicon nitride, and carbon doped silicon oxide. Ti etching selectivity exceeding three orders of magnitude was realized. Surprisingly, it exploits the use of HF, a chemical well known for its SiO2 etching ability, along with a silicon precursor to protect SiO2. The ability to selectively etch the Ti HM without impacting key transistor/interconnect components has enabled advanced process technology nodes of today and beyond. This environmentally friendly formulation is now employed in production of advanced high-performance microprocessors and produced in a 3000 gallon reactor.
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Sarvari, Reza. "Impact of size effects and anomalous skin effect on metallic wires as GSI interconnects." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/31636.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Meindl, James D.; Committee Member: Davis, Jeffrey A.; Committee Member: Gaylord, Thomas K.; Committee Member: Hess, Dennis W.; Committee Member: Peterson, Andrew F. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Gečys, Paulius. "Ultrashort pulsed laser processing of thin-films for solar cells." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2012. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2012~D_20121001_093555-45841.
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Present PhD thesis is the experimental and theoretical analysis of thin layer ultrashort pulsed laser ablation processes for photovoltaic devices. Experimental work was supported by modeling and simulation of energy coupling and dissipation inside the layers. The absorbed laser energy was transformed to localized transient heating inside the structure. Selectiveness of the ablation process was defined by optical and mechanical properties of the materials, and selection of the laser wavelength facilitated control of the structuring process. The 1064 nm wavelength was found optimal for the CIGS solar cell scribing in terms of quality and process speed. It is very positive result for industrial applications as the cost and the system complexity are decreased. The solar cell efficiency test revealed minor degradation in photo-electrical efficiency after the laser scribing was applied to the solar cell samples. Lock-in thermography measurements did not revealed any internal shunt formation during laser scribing with picosecond pulse duration. Picosecond lasers with fundamental harmonics and high repetition rates can be used to accomplish efficient and fast scribing process which is able to fit the demands for industrial solar cell scribing applications.Disertacijos darbo tikslas buvo, modeliuojant bei vykdant eksperimentus, suprasti plonų sluoksnių, naudojamų Saulės elementuose, abliacijos procesus ultratrumpais impulsais, siekiant juos pritaikyti integruotų jungčių fotovoltiniuose moduliuose formavimui. Eksperimento rezultatams pagrysti buvo vykdomas lazerio spinduliuotės sklidimo bei pasiskirstymo plonasluoksnėje Saulės elemento struktūroje modeliavimas. Sugerta lazerio energija lokaliai užkaitiną medžiagą. Kadangi lazerinio proceso selektyvumas priklauso nuo medžiagos optinių savybių, todėl yra itin svarbu parinkti tinkamą lazerio spinduliuotės bangos ilgį, norint sukaupti spinduliuotę reikiamame plonasluoksnės struktūros sluoksnyje. Nustatyta, kad fundamentinė pikosekundinio lazerio spinduliuotė (1064 nm) yra optimaliausia P3 tipo rėžio formavimui CIGS Saulės elemente. Pramonės taikymams tai yra itin svarbu, nes tokiu atveju mažėja industrinės lazerinės sistemos sudėtingumas bei kaina. Saulės elementų efektyvumo tyrimai parodė nežymų fotoelektrinio efektyvumo sumažėjimą po lazerinio apdirbimo ultra trumpais impulsais, tačiau nebuvo užfiksuota defektų generacijos lazeriais paveiktose kanalo kraštų zonose. Disertacijoje pasiūlyti ir išbandyti pluošto formavimo ir lygiagretaus sluoksnių raižymo metodai, didinantys proceso našumą ir raižymo kokybę. Pikosekundiniai, didelio impulsų pasikartojimo dažnio lazeriai gali būti panaudoti didelės spartos bei aukštos kokybės Saulės elementų raižymo procesuose.
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Arunagiri, Tiruchirapalli Natarajan. "Interfacial Electrochemistry of Metal Nanoparticles Formation on Diamond and Copper Electroplating on Ruthenium Surface." Thesis, University of North Texas, 2003. https://digital.library.unt.edu/ark:/67531/metadc5526/.
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An extremely facile and novel method called spontaneous deposition, to deposit noble metal nanoparticles on a most stable form of carbon (C) i.e. diamond is presented. Nanometer sized particles of such metals as platinum (Pt), palladium (Pd), gold (Au), copper (Cu) and silver (Ag) could be deposited on boron-doped (B-doped) polycrystalline diamond films grown on silicon (Si) substrates, by simply immersing the diamond/Si sample in hydrofluoric acid (HF) solution containing ions of the corresponding metal. The electrons for the reduction of metal ions came from the Si back substrate. The diamond/Si interfacial ohmic contact was of paramount importance to the observation of the spontaneous deposition process. The metal/diamond (M/C) surfaces were investigated using Raman spectroscopy, scanning electron microscopy (SEM), x-ray photoelectron spectroscopy (XPS) and x-ray diffractometry (XRD). The morphology (i.e. size and distribution) of metal nanoparticles deposits could be controlled by adjusting the metal ion concentration, HF concentration and deposition time. XRD data indicate the presence of textured and strained crystal lattices of Pd for different Pd/C morphologies, which seem to influence the electrocatalytic oxidation of formaldehyde (HCHO). The sensitivity of electrocatalytic reactions to surface crystal structure implies that M/C could be fabricated for specific electrocatalytic applications. The research also presents electroplating of Cu on ruthenium (Ru), which a priori is a promising barrier material for Cu interconnects in the sub 0.13 μm generation integrated circuits (ICs). Cu plates on Ru with over 90% efficiency. The electrochemical nucleation and growth studies using the potentiostatic current transient method showed a predominantly progressive nucleation of Cu on Ru. This was also supported by SEM imaging, which showed that continuous thin films of Cu (ca. 400 Å) with excellent conformity could be plated over Ru without dendrite formation. Scotch tape peel tests and SEM on Cu/Ru samples both at room temperature (RT) and after annealing at 800 oC, showed no sign of delamination of the Cu film from Ru indicating strong adhesion. XRD patterns from Cu/Ru samples at RT through 800 oC indicated Cu in its characteristic face centered cubic (fcc) form with (111) phase dominating. Most importantly no new XRD peak emerged, even after annealing to 800 oC showing Cu and Ru did not interact much. The excellent adhesion and lack of metallurgical interactions between Cu and Ru underscored the potential application of Ru as a new Cu diffusion barrier in the next generation ICs.
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Wirth, Alexandra. "Development of electrolessly deposited thin films for application in advanced interconnects : Cu seed-layer and seed-less ternary diffusion barriers." Université Louis Pasteur (Strasbourg) (1971-2008), 2002. http://www.theses.fr/2002STR13169.
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Le cuivre (Cu) a été choisi comme le métal destiné à remplacer les traditionnels alliages a base d'aluminium utilisés dans les interconnexions avances des circuits intégrés ULSI. Il a été sélectionné en raison de sa plus faible résistivité et de sa meilleure résistance à l'éléctromigration. L'architecture de cuivre est une structure damascène qui pose d'autres défis quant a la barrière et aux couches d'ensemencement. En raison de la constante diminution des motifs caractéristiques des circuits intégrés, des méthodes de dépôt électrochimique sont actuellement évaluées à titre alternatif, par exemples les dépôts electroless pour les couches d'accrochage ou les barrières de diffusion, en combinaison avec des dépôts électrochimiques (ECD) du Cu. Dans la première partie de cette thèse, nous avons étudié un procédé d'activation suivi par un dépôt electroless d'une couche d'accrochage de Cu sur des barrières TiN MOCVD. L'influence de la concentration des ions de palladium et la composition de la chimie du bain de dépôt en plus des surfaces de substrats différents et leur pré traitement respectif a été investigué. Dans la seconde partie de ce travail, différentes solutions ont été élaborées pour le dépôt electroless d'alliages polymétalliques par exemple du type NiMo-P, dans le but d'incorporer des concentrations élevées de métaux réfractaires. L'intégration de ces barrières ternaires avec une technologie Cu a été examinée en étudiant les aspects métallurgiques et morphologiques, l'uniformité de couverture, la résistivité et l'efficacité en tant que barrière de diffusion. De plus, la spectroscopie de résonance paramagnétique électronique (RPE) a été utilisée pour détecter soient des charges mobiles, soient des espèces localisées issues de défauts engendrés par des phénomènes de diffusion au travers des barrières à l'interface barrière/ SiO2/ SiCopper is adopted in advanced deep submicron ULSI metallisation applications due to its lower resistivity and better electromigration resistance compared to traditional Al compounds. It is integrated using damascene structures that introduce new challenges related to barrier and seed-layer deposition. Electroless plating methods together with direct Cu ECD on barriers (seed-less barriers) are being pursued as more extendible solutions for seed-layer and effective Cu diffusion barrier layer deposition, regarding the issue of superior conformality and improved thickness control in small feature sizes of the 65 nm and below technology node. In a first part of this work, an electroless Cu seed-layer deposition process on TiN MOCVD barrier layer is developed. Focus of interest is the increase of density and reduction of size of the Pd catalyst islands. The impact of Pd ion concentration and respective bath chemistry composition as well as the influence of different substrate surfaces and their respective pre-treatment is investigated. In a second part, various electrolessly deposited polymetallic alloy coatings, e. G. NiMo-P, incorporating high amounts of refractory metals are investigated as potential seed-less diffusion barriers. The polymetallic alloy thin films serve at the same time as efficient diffusion barrier, adhesion promoter and conductive layer for direct Cu ECD. Implementation of these types of barrier layers is evaluated regarding minimum efficient barrier thickness, microstructural requirements and integration aspects such as thin film resistivity impact when integrated in advanced multilevel Cu interconnect schemes. Highly sensitive electron spin resonance (ESR) characterisation technique is investigated for the detection of unpaired electron defects as possibly resulting from diffusion phenomena through the barriers
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Mukherjee, Tamal. "Investigation of Post-Plasma Etch Fluorocarbon Residue Characterization, Removal and Plasma-Induced Low-K Damage for Advanced Interconnect Applications." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849649/.
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Modern three-dimensional integrated circuit design is rapidly evolving to more complex architecture. With continuous downscaling of devices, there is a pressing need for metrology tool development for rapid but efficient process and material characterization. In this dissertation work, application of a novel multiple internal reflection infrared spectroscopy metrology is discussed in various semiconductor fabrication process development. Firstly, chemical bonding structure of thin fluorocarbon polymer film deposited on patterned nanostructures was elucidated. Different functional groups were identified by specific derivatization reactions and model bonding configuration was proposed for the first time. In a continued effort, wet removal of these fluorocarbon polymer was investigated in presence of UV light. Mechanistic hypothesis for UV-assisted enhanced polymer cleaning efficiency was put forward supported by detailed theoretical consideration and experimental evidence. In another endeavor, plasma-induced damage to porous low-dielectric constant interlayer dielectric material was studied. Both qualitative and quantitative analyses of dielectric degradation in terms of increased silanol content and carbon depletion provided directions towards less aggressive plasma etch and strip process development. Infrared spectroscopy metrology was also utilized in surface functionalization evaluation of very thin organic films deposited by wet and dry chemistries. Palladium binding by surface amine groups was examined in plasma-polymerized amorphous hydrocarbon films and in self-assembled aminosilane thin films. Comparison of amine concentration under different deposition conditions guided effective process optimization. A time- and cost-effective method such as current FTIR metrology that provides in-depth chemical information about thin films, surfaces, interfaces and bulk layers can be increasingly valuable as critical dimensions continue to scale down and subtle process variances begin to have a significant impact on device performance.
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Li, Kecheng. "Direct Liquid Evaporation Chemical Vapor Deposition(DLE-CVD) of Nickel, Manganese and Copper-Based Thin Films for Interconnects in Three-Dimensional Microelectronic Systems." Thesis, Harvard University, 2016. http://nrs.harvard.edu/urn-3:HUL.InstRepos:33493366.
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Electrical interconnects are an intrinsic part of any electronic system. These interconnects have to perform reliably under a wide range of environmental conditions and survive stresses induced from thermal, mechanical, corrosive and electrical factors. Semiconductor technology is predominantly planar in nature, posing a severe limitation to the degree of device integrations into systems such as micro-processors or memories. 3D transistor FinFET (Fin type Field Effect Transistors) has been used by Intel since the advent of its 22 nm technology node, and has now advanced further down to 14 nm. While the technology nodes have consistently been shrinking in line with Moore’s law, increasing difficulties in scaling down the feature sizes in transistors is urging the industry to seek alternative fabrication approaches for the extension of Moore’s law. The most promising solution thus far is 3D heterogeneous integration, which will stack logical and analog chips together to enable multi functions chip without the need to scale the size of transistors with Moore’s law. Furthermore, as wearable electronics are fast growing in the next big wave in consumer electronics after the smartphone era, interconnects face the unique challenge of having to be embedded into fashion and withstand the mechanical stresses from everyday activity. This makes the role interconnects even more important as well as making it the main bottleneck to unleashing the full performance of the 3D microelectronics systems.
This thesis explores the fabrication, characterization and application of Nickel, Manganese, Copper based thin films for the interconnects of 3D microelectronics systems. Direct Liquid Evaporation-Chemical Vapor Deposition (DLE-CVD) technique has been proven to be a high-throughput process for high-quality Nickel, Manganese, Copper based thin films with excellent conformality in complex architectures as the interconnects for state-of-the-art 3D microelectronics systems.
Chapter 2 introduces the advantages of DLE-CVD process and its application in deposition of Nickel, Manganese and Copper based thin films. DLE-CVD process is used to deliver consistent and high vapor concentrations of Nickel, Manganese and Copper precursors to coat nanostructures with high aspect ratios.
Chapter 3 demonstrates the atom probe tomography (APT) as an effective method for understanding the 3D microstructure and compositional properties in thin films at an atomic scale. 3D compositional information of DLE-CVD NiNx, NiSi thin films from inside and outside regions of the trench structures have been investigated using APT. The APT characterization technique provides a unique tool that can be applied both to the design of 3D nanostructured microelectronic devices and to the further understanding of the fundamental physical properties.
Chapter 4 highlights the application of DLE-CVD manganese and copper based thin film process in the complex nanostructures for 3D microelectronic systems. Narrow trenches with width under 30 nm are the key nanostructure in the local interconnects in 3D FINFET with technology node smaller than 14 nm for use in microelectronic chips. It can be filled with DLE-CVD copper and copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. An ultrathin manganese nitride layer (~ 3 nm) acts as a diffusion barrier and an adhesion layer. Through-silicon vias (TSVs) plays a crucial role in advancing the 3D integration of semiconductor devices by improving the performances of interconnections between chips. Using DLE-CVD processes, conformal, smooth and continuous copper/copper-manganese seed layers can be prepared in TSVs with aspect ratio greater than 25:1. manganese Nitride film is deposited via the DLE-CVD process to serve as an adhesion and barrier layer. Dow Chemicals achieved void-free TSV filling through the electroplating process.
Chapter 5 shows the application of the DLE-CVD manganese and copper based thin film process in the metallization of polyaramids for the application in the interconnects embedded in wearable electronic systems. Conformal and conductive coatings of copper-manganese have been successfully deposited on Kevlar fibers using the DLE-CVD process with complete film coverage. The mechanical resistance of copper-manganese coated Kevlar was tested via our in-house robotic arm system, demonstrating how the electrical resistance of the wire remains unchanged despite being flexed repeatedly to a bend of 5mm radius for half a million times.Engineering and Applied Sciences - Applied Physics
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Gečys, Paulius. "Plonasluoksnių saulės elementų apdirbimas ultratrumpais lazerių impulsais." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2012. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2012~D_20121001_093544-75615.
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Disertacijos darbo tikslas buvo, modeliuojant bei vykdant eksperimentus, suprasti plonų sluoksnių, naudojamų Saulės elementuose, abliacijos procesus ultratrumpais impulsais, siekiant juos pritaikyti integruotų jungčių fotovoltiniuose moduliuose formavimui. Eksperimento rezultatams pagrysti buvo vykdomas lazerio spinduliuotės sklidimo bei pasiskirstymo plonasluoksnėje Saulės elemento struktūroje modeliavimas. Sugerta lazerio energija lokaliai užkaitiną medžiagą. Kadangi lazerinio proceso selektyvumas priklauso nuo medžiagos optinių savybių, todėl yra itin svarbu parinkti tinkamą lazerio spinduliuotės bangos ilgį, norint sukaupti spinduliuotę reikiamame plonasluoksnės struktūros sluoksnyje. Nustatyta, kad fundamentinė pikosekundinio lazerio spinduliuotė (1064 nm) yra optimaliausia P3 tipo rėžio formavimui CIGS Saulės elemente. Pramonės taikymams tai yra itin svarbu, nes tokiu atveju mažėja industrinės lazerinės sistemos sudėtingumas bei kaina. Saulės elementų efektyvumo tyrimai parodė nežymų fotoelektrinio efektyvumo sumažėjimą po lazerinio apdirbimo ultra trumpais impulsais, tačiau nebuvo užfiksuota defektų generacijos lazeriais paveiktose kanalo kraštų zonose. Disertacijoje pasiūlyti ir išbandyti pluošto formavimo ir lygiagretaus sluoksnių raižymo metodai, didinantys proceso našumą ir raižymo kokybę. Pikosekundiniai, didelio impulsų pasikartojimo dažnio lazeriai gali būti panaudoti didelės spartos bei aukštos kokybės Saulės elementų raižymo procesuose.Present PhD thesis is the experimental and theoretical analysis of thin layer ultrashort pulsed laser ablation processes for photovoltaic devices. Experimental work was supported by modeling and simulation of energy coupling and dissipation inside the layers. The absorbed laser energy was transformed to localized transient heating inside the structure. Selectiveness of the ablation process was defined by optical and mechanical properties of the materials, and selection of the laser wavelength facilitated control of the structuring process. The 1064 nm wavelength was found optimal for the CIGS solar cell scribing in terms of quality and process speed. It is very positive result for industrial applications as the cost and the system complexity are decreased. The solar cell efficiency test revealed minor degradation in photo-electrical efficiency after the laser scribing was applied to the solar cell samples. Lock-in thermography measurements did not revealed any internal shunt formation during laser scribing with picosecond pulse duration. Picosecond lasers with fundamental harmonics and high repetition rates can be used to accomplish efficient and fast scribing process which is able to fit the demands for industrial solar cell scribing applications.
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Zhang, Yuelan. "Synthesis and Characterization of Nanostructured Electrodes for Solid State Ionic Devices." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14000.
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The demands for advanced power sources with high energy efficiency, minimum environmental impact, and low cost have been the impetus for the development of a new generation of batteries and fuel cells. One of the key challenges in this effort is to develop and fabricate effective electrodes with desirable composition, microstructure and performance. This work focused on the design, fabrication, and characterization of nanostructured electrodes in an effort to minimize electrode polarization losses.
Solid-state diffusion often limits the utilization and rate capability of electrode materials in a lithium-ion battery, especially at high charge/discharge rates. When the fluxes of Li+ insertion or extraction exceed the diffusion-limited rate of Li+ transport within the bulk phase of an electrode, concentration polarization occurs. Further, large volume changes associated with Li+ insertion or extraction could induce stresses in bulk electrodes, potentially leading to mechanical failure. Interconnected porous materials with high surface-to-volume ratio were designed to suppress the stress and promote mass transport. In this work, electrodes with these unique architectures for lithium ion batteries have been fabricated to improve the cycleability, rate capability and capacity retention.
Cathodic interfacial polarization represents the predominant voltage loss in a low-temperature SOFC. For the first time, regular, homogeneous and bimodal porous MIEC electrodes were successfully fabricated using breath figure templating, which is self-assembly of the water droplets in polymer solution. The homogeneous macropores promoted rapid mass transport by decreasing the tortuosity. And mesoporous microstructure provided more surface areas for gas adsorption and more TPBs for the electrochemical reactions. Moreover, composite electrodes were developed with a modified sol-gel process for honeycomb SOFCs. The sol gel derived cathodes with fine grain size and large specific surface area, showed much lower interfacial polarization resistances than those prepared by other existing processing methods.
Nanopetals of cerium hydroxycarbonate have been synthesized via a controlled hydrothermal process in a mixed water-ethanol medium. The formation of the cerium compound depends strongly on the composition of the precursors, and is attributed to the favored ethanol oxidation by Ce(IV) ions over Ce(IV) hydrolysis process. Raman studies showed that microflower CeO2 preferentially stabilizes O2 as a peroxide species on its surface for CO oxidation.
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Choi, Chulchae. "Thin-film VCSEL and optical interconnection layer fabrications for fully embedded board level optical interconnects." Thesis, 2003. http://hdl.handle.net/2152/502.
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Choi, Chulchae Chen Ray T. "Thin-film VCSEL and optical interconnection layer fabrications for fully embedded board level optical interconnects." 2003. http://repositories.lib.utexas.edu/bitstream/handle/2152/502/choicc039.pdf.
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Lin, Lei Chen Ray T. "Integration of thin film GaAs MSM photodetector in fully embedded board-level optoelectronic interconnects." 2004. http://repositories.lib.utexas.edu/bitstream/handle/2152/2070/linl042.pdf.
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Lin, Lei. "Integration of thin film GaAs MSM photodetector in fully embedded board-level optoelectronic interconnects." Thesis, 2004. http://hdl.handle.net/2152/2070.
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Wei, Bor-Jou, and 魏伯州. "Studies on the Low-k Dielectric and High Reliability Thin Film Materials for Interconnects." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/97492674923759991673.
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博士國立中興大學
材料科學與工程學系所
100
In order to integrated circuit (IC) industry following Moore’s law, for scal-ing downing the device the multilevel interconnect had used to increase the densities of circuits on a chip, interconnect delay is becoming predominant over device delay time. As the device dimensions continue to shrink, interconnect delay becomes a lim-iting factor for increasing circuit device speed. The multilevel interconnect basically consists of metal layers, inter-layer dielectric (ILD) and inter-metal dielectric (IMD). As the device dimensions continue to shrink, interconnect delay becomes a limiting factor for increasing circuit device speed. Since interconnect delay is the product of the resistance in metal interconnect and the capacitance between the metal lines, the minimization of the parasitic capacitance and the resistance in interconnect is required. Incorporation of low-dielectric-constant materials in multilevel interconnect can ef-fectively reduce parasitic capacitance, thus decreasing the transmission delay. In this study, several kinds of low dielectric constant and resistors materials are investigated, including fluorine-silicate-glass (FSG), carbon-doped organo-silicate glass using trimethylsilane (3MS) and diethoxymethylsilane (DEMS) as precursors, and Ti/TiN thin films. The effects of the low-k dielectric constant materials on the in-tegration issue are studied to evaluate the compatibility of low-k materials on semi-conductor process. Moreover, the reliability of Ti/TiN thin film resistors were demon-strated no wear out issue below 311oC. As N2 is added in the FSG films by high-density-plasma chemical vapor deposition (HDP-CVD) method, higher fluorine concentration, reduced dielectric constant and improved gap filling ability of the deposited films have been achieved. It is proposed that the improvement of stability is correlated with the reduction of unstable fluorine bonds in the N-FSG films. Furthermore, the thermal stability of the N-FSG films was also identified by Al wiring delamination check. After annealing, the blister was observed only in non-N2 FSG film with 5.5 % Si-F concentration, while no blisters or delamination were observed when N2 is introduced into the FSG process. Therefore, the N-FSG film, deposited by HDP-CVD, is a good candidate for interconnects dielectric application. Lower dielectric constant as well as higher mechanical strength of plasma en-hanced chemical vapor deposition (PE-CVD) low-k films is required for IC speed and package. Both low-k films deposited using 3MS and DEMS precursors have similar elemental composition, but different bonding structures, leading to different integra-tion results. DEMS-based low-k films have a lower dielectric constant, higher hard-ness, and higher chemical and thermal stability than 3MS-based low-k films. From the results of blanket films and four-level interconnect test devices, the DEMS-based films were found to have superior electrical performance than that of the 3MS-based films. Ti/TiN thin film resistors were characterized by making electrical and reliability measurements. The results demonstrate that the Ti/TiN thin film resistor has an ex-cellent thermal stability up to 350oC. Based on electrical measurement and stress, the Ti layer has a lower electrical resistance than the TiN layer. Furthermore, the main failure mechanism of the Ti/TiN thin film resistors is thermally activated by Joule-heating. The thermal activation energy for failure is determined to be 1.8 eV for the Ti layer and 1.2 eV for the TiN layer. Based on this result, Ti/TiN thin film resis-tors exhibit no significant change in resistance during a lifetime of ten years if their temperature remains below 311oC.
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Da-JiunWang and 王大鈞. "Graphene Synthesis by Copper Thin Film and the Study on Electrical and Diffusion Barrier Properties in Graphene-Coated Copper Nanowires for Interconnects." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/85906280814906208761.
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碩士國立成功大學
機械工程學系
104
Copper nanowires are made by bi-layer liftoff process using e-beam lithography and e-beam evaporation. Graphene-coated copper nanowires are synthesized by the rapid thermal process with 900℃ growth temperature for 3 minute and control cooling rate until 750℃ . The raman spectrum show the G and 2D band, and the I _D / I _G is near 2. It represent that there is graphene with defects on the copper nanowires. The XPS spectrum show the sp2 bonded which represent the carbon-carbon bonded of graphene at binding energy 284.6 eV. With the direct current-voltage measurent, we find that graphene reduce the resistivity of copper nanowires about 21.5%, compared to the no graphene-coated sample. It represent graphene reduce the surface scattering of electrons at the copper nanowires surface. For the purpose of analyzing the barrier property, we deposite 350nm silicon oxide layer on the sample by HDPCVD, and anneal at 200, 350, 500℃ for two hours. Using leakage current and EDS line scan measurement to analyze the barrier property. We find that the graphene will fail to diffusion barrier until 350 to 500℃ .
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Thompson, Carl V. "Research on Polycrystalline Films for Micro- and Nano-Systems." 2003. http://hdl.handle.net/1721.1/3670.
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Polycrystalline films are used in a wide array of micro- and nano-scale devices, for electronic, mechanical, magnetic, photonic and chemical functions. Increasingly, the properties, performance, and reliability of films in these systems depend on nano-scale structure. In collaborative research with a number of SMA Fellows, Associates, and students, our group is carrying out research focused on probing, modeling and controlling nano-scale structural evolution during both vapor-phase and solid-phase polycrystalline film formation. In particular, high-sensitivity in-situ and real-time stress measurements are being used to study atomic scale forces and to characterize structure formation and evolution at the nano-scale. In other collaborative research, the affects of controlled structure and multi-film architectures on properties, such as piezoelectric characteristics and electromigration-limited reliability, are being explored. Through these interrelated activities, basic principles of the science and engineering of nano-scale materials are emerging.Singapore-MIT Alliance (SMA)
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Pham, Daniel Thanh Khac. "Carbon nanotube thin film transistor on flexible substrate and its applications as switches in a phase shifter for a flexible phased-array antenna." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2222.
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In this dissertation, a carbon nanotube thin-film transistor is fabricated on a flexible substrate. Combined printing and stamping techniques are used for the fabrication. An ink-jet printing technique is used to form the gate, source, and drain electrodes as well as the dielectric layer. A self aligned carbon nanotube (CNT) thin film is formed by using a new modified dip coat technique before being transferred to the device substrate. This novel modified dip-coat technique utilizes the capillary effect of a liquid solution rising between gaps to coat CNT solution on a large area of the substrate while consuming minimal CNT solution. Several key solutions are addressed to solve the fabrication problems. (1) The source/drain contact with the CNT channel is developed by using droplets of silver ink printed on the source/drain areas prior to applying CNT thin. The wet silver ink droplets allow the silver to "wet" the CNT thin-film area and enable good contact with the source and drain contact after annealing. (2) A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This thin Kapton film is also used as the media for transferring the aligned CNT thin-film on the device substrate. Using this technique, printing the passivation layer can be avoided, and it prevents the inter-diffusion of the liquid dielectric into the CNT porous thin-film. (3) A simple and cost effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior bonding on the first substrate. Ink-jet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the on the bottom layer, followed by an anneal process. High drain current of 0.476mA was obtained when V[subscript G]= -3V and source-drain voltage (V[subscript DS]) was -1.5V. A bending test was performed on the CNT TFT showing less than a 10% variation in performance. A bending test was also performed on via structures, which yielded less than a 5% change in resistance. The developed CNT TFT is used to form a switch in a phase shifter for a flexible phased-array antenna (PAA). Four element 1-dimensional and 2-dimensional phased-array antennae are fabricated and characterized. Multilayer metal interconnects were used to make a complete PAA system. For a 2-bit 1x4 PAA system, by controlling the ON/OFF states of the transistors, beam steering of a 5.3GHz signal from 0° to -27° has been demonstrated. The antenna system also shows good stability and tolerance under different bending radii of curvature. A 2-bit 2x2 PAA system was also fabricated and demonstrated. Two dimensional beam steering of a 5.2GHz signal at an angle of [theta]=20.7° and [phi]=45° has been demonstrated. The total efficiency of the 1-dimensional and 2-dimensional PAA systems are 42% and 46%, respectively.text
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Thompson, Carl V. "Processing, Structure, Properties, and Reliability of Metals for Microsystems." 2002. http://hdl.handle.net/1721.1/3984.
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Research on the processing, structure, properties and reliability of metal films and metallic microdevice elements is reviewed. Recent research has demonstrated that inelastic deformation mechanisms of metallic films and microelements are a function of temperature, encapsulation, and dimension. Reduced dimension can lead to strengthening or softening, depending on the temperature and strain rate. These results will help in the analysis and prediction of the stress state of films and microelements as a function of their thermal history. Experimental characterization and modeling of stress evolution during film formation has also been undertaken. New microelectromechanical devices have been developed for in situ measurements of stress during processing, and experiments relating stress and structure evolution are underway for electrodeposition and reactive film formation as well as vapor deposition. Experiments relating current-induced stress evolution (electromigration) to the reliability of Cu based interconnects are also being carried out.Singapore-MIT Alliance (SMA)
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Li, Yan-Way, and 李延煒. "Thin Film Preparation and Characterization of Carbon-based Dielectrics for ULSI Interconnect Technology." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/569vwa.
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博士國立交通大學
材料科學與工程系所
92
The purpose of this work is research the dielectric properties of a-C and a-SiC:H films, deposited respectively by using gridless ion beam deposition (GIBD) and plasma-enhanced chemical vapour deposition (PECVD), to evaluate the possibility for using in the etching-stop layer of copper interconnect technology. Amorphous hydrogenated carbon (a-C:H) films were deposited from gas mixtures of acetylene (C2H2) and argon (Ar) in a GIBD system supplied with dc power. Vacuum annealing and hydrogen plasma treatment were performed on the a-C:H films and their effects on the physical and electrical characteristics of the films were investigated. The structure and properties of the film were investigated as functions of the C2H2 flow rate, using Raman spectroscopy. The Raman spectra revealed that the Raman ID/IG ratio and D peak position decreases with C2H2 flow rate, indicating more diamond-like character of the films. Otherwise, the annealed a-C:H films exhibited that the Raman ID/IG ratio increases with annealing temperature, but the film density decreases simultaneously, indicating more graphite-like character for the annealed films as the annealing temperature was increased. The dielectric constant of the annealed a-C:H films was reduced from 3.8 to 2.9, but the leakage current density was obviously increased while the annealing temperature was increased from 200℃ to 300℃. However, the leakage current density and dielectric constant of the hydrogen-plasma-treated a-C:H films were clearly lower than those of the as-deposited a-C:H films. Amorphous SiC:H films were deposited from a mixture of silane and methane gases, using PECVD. Reducing the ratio of the silane flow rate decreased the deposition rate of the a-SiC:H films, decreasing the refractive index and dielectric constant, but increasing the optical band gap and the hydrophobicity of the surface. It has a minimum refractive index (1.76), dielectric constant (3.6), leakage current density (1.79×10-8 A/cm2 at the electric field of 1MV/cm) and deposition rate (1.32 Å/s) for the concentration of silane, which is 5% in the mixture gas. XPS data indicate that the carbon concentration of the a-SiC:H films declined as the methane flow rate increased, but the silicon concentration increased. Carbon-rich films were treated with hydrogen and ammonia plasma for various periods, but were then converted into films with higher silicon content. Increasing the ammonia or hydrogen plasma treatment duration roughened the surface, even though the original film had a smooth surface, with a roughness of 0.231 nm. Ammonia plasma treated film has larger roughness (1.741 nm) than that of by using hydrogen plasma treated films (0.829 nm). The ammonia ionization species reacted with Si to promote the formation of silicon nitride. Accordingly, the leakage current density of a-SiC:H films declined as the ammonia plasma treatment time decreased, but the dielectric constant slightly increased. As expected, the leakage current density and the dielectric constant of a-SiC:H films declined as the hydrogen plasma treatment period increased.
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Chien-JuKuo and 郭蒨如. "Channel Cracking and Interfacial Delamination Analyses for Thin Film and Interconnect Structures Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/78288771768886357278.
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碩士國立成功大學
機械工程學系碩博士班
98
Microsystem devices are composed of multi-layered thin films with different material properties and structural thickness, and are connected with each other via metallic interconnect structures. However, during fabrication, the therm-mechanical mismatch between materials generates high stresses, which cause the generation of stress-induced voiding, cracks, as well as the possible channel cracks and interface delaminations. These defects strongly affect the reliability of integrated circuit devices. As a result, the reliability of thin films and interconnect structures becomes one major concern of modern microelectronics. The aim of this study is to address the reliability of interconnect structures and thin films through a systematic failure analysis, and to provide effective methods to improve the reliability of IC and MEMS devices. This theses utilizes mechanics of materials, fracture mechanics, and finite element method to analysis channel cracking and interfacial delamination of thin films and interconnect structures, as well as for estimating that the stress and energy release rate within the structures. Parametric studies for investigating the sensitivity of each physical parameter on the stress generation, strain energy release rate, and crack growth are presented. The results show that high stress could generate stress-induced voiding and cracking, and select the low-k materials that lower Young's modulus and coefficient of thermal expansion could avoid cause high stress. Lower processing temperature could improve the reliability of interconnect structures, and a smaller residual stress could avoid interfacial delamination of thin films. Using this systematic failure analysis method, it is possible to provide an efficient method to analysis fracture problems, and the study results should be useful for providing engineers the the conceptual design structure reliability access of thin film and interconnect structures, and to reduce development time.
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Chen, Jia-meng, and 陳佳盟. "A study of thin film as protective coating by plasma-sputtering on SOFC interconnect." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/63818972828020640565.
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碩士國立中央大學
機械工程研究所
95
In this study, the five commercial metallic materials Crofer22, CS ZMG-232, SS-304, SS-430 and Inconel 718 were investigated. The La0.67Sr0.33MnO3( LSMO ) thin film was coated on those materials using pulsed DC magnetron sputtering. The film was amorphous but converted to perovskite structure after annealing. It was used as protection layer on metallic interconnects in SOFC to prevent the growth of oxide and the diffusion of Cr element. SEM and XRD made use of observing the crystal structure of thin film after annealing. Using GID method and XPS inspects the Cr diffusion and Cr-oxide of LSMO in the high-temperature oxidation environment. The result shows the LSMO thin film on Crofer22 and CS ZMG-232 were good for compaction and adhesion. Thus, it could prevent the growth of oxide and the diffusion of Cr element to avoid poison of cathode and decline of conductivity in SOFC in high temperature. Besides, the coated Crofer22 and CS ZMG-232 proceed ASR measurement in 800℃ for 1150hrs to observe the variation of contact resistance. After ASR measurement, the ASR is 12.42 mohm.cm2 and 62.79 mohm.cm2 respectively.
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Chen, Ya-Ling, and 陳雅齡. "Microstructure Analysis And Sputtering Thin Film Properties of Al-Sc Alloys Target for FPD Interconnect Application." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/qv6942.
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碩士國立臺北科技大學
材料及資源工程系所
93
Aluminum alloy are currently being considered as terget materials for large scale LCD to prepare driving circuit layers or interconnection. This type of target material requires to possess some properties such as high conductivity, good adhesion to adjacent layers, resistance to electromigration and hillocks, controllable deposition, as well as low cost etc. Therefore, the goal of this study is to develop a novel type wrought aluminum target, utilized in the TFT-LCD circuit layers or interconnection materials field, that possess some advantageous characteristics such as high purity, whole unity forming, large scale, and recyclable. These characteristics can be achieved by combination of vacuum melting process and subsequently hot working process as well as alloying system design. This study aims to investigate the effect of scandium content or 0.5 wt% rubidium on the microstructure, precipitates composition, phase transformation, and sputtering thin film characterization (i.e., electric properties, thermal properties optical properties, and surface morphology) of the binary Al-Sc alloys and ternary Al-1wt%Sc-0.5wt%Nd alloy sputtered targets, respectively. Experimental results were compared with the results of a commercial Al-Nd alloy target. The experimental data indicate that the transition element scandium is an effective grain refiner and modifier for the Al-Sc alloy targets. The effect of adding minor Sc on the microstructure of the as-cast Al-Sc targets shows that the grain size can be controlled below 50μm and have a uniform size after vacuum melting process. Microstructure analysis and phase characterizations indicates that the Al-Sc alloy targets have an high purity matrix with an fine equiaxed grain structure as well as a fine and high thermal stability precipitates, Al3Sc, is uniformly dispersed in the matrix after casting. The thin film characterization of the Al-Sc alloys is summarized as follows: (i) Al alloy films containing scandium shows an excellent resistance to hillock formation. The effect in suppressing the hillock formation of the Al-Sc alloys system films is superior to the commercial Al-Nd alloy film. (ii) The measurement results of electrical resistivity show that the residual resistivity of the Al-Sc alloys films decreases below a value, 4μΩcm, after annealing treatment at temperature above 300 C, and the value is remarkably low as compared with 10μΩcm, which is the electrical resistivity requirement for large scale TFT-LCD. The electrical resistivity of Al-Sc alloys films increases with increasing scandium element content. Especially, the electrical resistivity substantially increases at scandium content to exceed 1.5wt%. (iii) The optical reflectivity of Al-Sc alloy thin films with the scandium below 1.5wt% is about 83% at visible light band before and after annealing treatment. The experimental evidences shows that the Al-Sc type alloy targets and their sputtering film are very suitable as interconnections of TFT-LCD driving circuits or as high reflectivity metal film of photoelectric devices.
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Henderson, Lucas Benjamin. "Deposition and properties of Co- and Ru-based ultra-thin films." 2009. http://hdl.handle.net/2152/7836.
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Future copper interconnect systems will require replacement of the materials that currently comprise both the liner layer(s) and the capping layer. Ruthenium has previously been considered as a material that could function as a single material liner, however its poor ability to prevent copper diffusion makes it incompatible with liner requirements. A recently described chemical vapor deposition route to amorphous ruthenium-phosphorus alloy films could correct this problem by eliminating the grain boundaries found in pure ruthenium films. Bias-temperature stressing of capacitor structures using 5 nm ruthenium-phosphorus film as a barrier to copper diffusion and analysis of the times-to-failure at accelerated temperature and field conditions implies that ruthenium-phosphorus performs acceptably as a diffusion barrier for temperatures above 165 °C. The future problems associated with the copper capping layer are primarily due to the poor adhesion between copper and the current Si-based capping layers. Cobalt, which adheres well to copper, has been widely proposed to replace the Si-based materials, but its ability to prevent copper diffusion must be improved if it is to be successfully implemented in the interconnect. Using a dual-source chemistry of dicobaltoctacarbonyl and trimethylphosphine at temperatures from 250-350 °C, amorphous cobalt-phosphorus can be deposited by chemical vapor deposition. The films contain elemental cobalt and phosphorus, plus some carbon impurity, which is incorporated in the film as both graphitic and carbidic (bonded to cobalt) carbon. When deposited on copper, the adhesion between the two materials remains strong despite the presence of phosphorus and carbon at the interface, but the selectivity for growth on copper compared to silicon dioxide is poor and must be improved prior to consideration for application in interconnect systems. A single molecule precursor containing both cobalt and phosphorus atoms, tetrakis(trimethylphosphine)cobalt(0), yields cobalt-phosphorus films without any co-reactant. However, the molecule does not contain sufficient amounts of amorphizing agents to fully eliminate grain boundaries, and the resulting film is nanocrystalline.text
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Liu, Chi-Jen, and 劉啟人. "Characteristics of Cu alloy thin films and their applications as the interconnect materials in integrated circuits." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/18575489585537883346.
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博士國立成功大學
材料科學及工程學系碩博士班
93
In this study, the characteristics of Cu alloy thin films and their applications as the materials of interconnect in integrated circuits were explored. Thin films of pure Cu and Cu along with Ti, Ta, and Zr with two different concentrations were deposited on SiO2/Si by magnetic co-sputtering. After deposition, all films were subsequently annealed at 500-800 oC in vacuum. The dissociated behaviors of various Cu alloy films on SiO2 was explored by Auger electron spectroscopy (AES), Rutherford backscattering spectrometry (RBS) and X-ray photoelectron spectroscopy (XPS). The microstructural evolution between Cu and Cu alloy films were examined by θ-2θ X-ray diffraction (XRD), glancing incident angle X-ray diffraction (GIAXRD), scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Simultaneously, the resistivity of all films, before and after annealing in vacuum, was calculated from the sheet resistance measured at room-temperature with a four-point probe and the film thickness. The adhesion between various Cu alloy films and SiO2 was determined by the scotch tape test. In addition, after the oxidation test, Cu and Cu alloy films were analyzed by the normalized sheet resistance and GIAXRD. In addition, to understand the leakage current, the current-voltage (I-V) cureves of various MOS capacitors with different metal gates were measured by using picoammeter/dc voltage. The experimental result reveals that Ti, Ta and Zr additives in Cu would diffuse outward to the free surface and the Cu alloy/SiO2 interface, and react with O2 to form an additional oxide layer upon annealing. However, the dissociated behaviors of 700 oC annealed Cu(3.90 at.% Ti), Cu(2.28 at.% Ta) and Cu(2.45 at.% Zr) thin films are different. The Ti and Zr additives in Cu would mainly diffuse outward to the free surface and the Cu alloy/SiO2 interface. On the contrary, the majority of the Ta additives would remain within the Cu layer. In addition, compared to the annealed pure Cu films, all the Cu alloy films showed less diffusion of Cu into SiO2 when annealing at 700 oC. Furthermore, the adhesion between film and SiO2 is better in Cu alloy samples than in pure Cu ones. The current-voltage measurement using metal-oxide-semiconductor (MOS) capacitor structure reveals low leakage current (10-8 A/cm2) for capacitors with as-deposited Cu(0.03 at.% Ti) and pure Cu metal gates. However, after annealing at 700 °C in vacuum, leakage current of MOS capacitors using pure Cu gate exhibits a dramatic increase of leakage current, while leakage current of capacitors with Cu(0.03 at.% Ti) gate remains at ~10-7 A/cm2, indicating that the Cu(0.03 at.% Ti)/SiO2 system possesses a superior reliability to the Cu/SiO2 system. The microstructural result shows that the surface morphology of Cu alloy films is superior to pure Cu films after annealing. The extent of void and grain growth decreases as the additives increases. Among all annealed Cu alloy films, the annealed Cu(2.28 at.% Ta) film shows the lowest degree of void and grain growth, but Cu(3.90 at.% Ti) and Cu(2.45 at.% Zr) films present higher degree of Cu(111) texture. According to the results of the oxidation test, the Cu alloy films pre-annealed at 700 °C reveal a superior oxidation resistance when annealed at 200 °C in air, especially for the pre-annelaed Cu(3.90 at.% Ti) and Cu(2.45 at.% Zr) films. In addition, the room-temperature resistivity of various Cu alloy films is higher than that of pure Cu films, but decreases as the annealing temperature increases. However, the room-temperature resistivity of all annealed Cu alloy films is still larger than that of pure Cu films with the same treatment. The relations between the resistivity variation and segregation of additives/surface morphology are also discussed.
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Cheng, Hsin-Chi, and 鄭新基. "On Nano- Indentation of Thin Films for Wafers with Interconnect in Deep Submicron:An Experimental and Theoretical Study." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/93417191612393474869.
Full textAbstract:
碩士國立中正大學
機械系
92
The mechanical property at nano-scale is central for the development of nanoscience and technology. Over the years, nanoindentation has evolved into a powerful means of determine the mechanical properties of thin films and surfaces in nanometer regimes. Up to now, most of the applications of nanoindentation have limited the indentation depth in the order of micro meters . Howere, the need for the development of nanoindentation with indentation depth in the order of nano meter is imminent. A case in point is the wafers with interconnect in deep submicron where thin films used is ultra thin. In wafers with interconnect in deep submicron, copper are used for interconnect, tantalum and tantalum nitride are the best isolation materials, chromium is commonly is commonly used in semiconductor industry for photo mask and photo resistor. This study is aimed to using nano indentation technology to measure mechanical property of Cu, Cr, Ta, and TaN thin films with indentation depth in the order of nano meter. Theoretical studies using atomic static approach and non-linear finite element formulation were conducted. Our findings indicate that in nanoindentation measurement, thin film and substrate should be regard as a system. For soft thin film on hard substrate, when indentation depth is within 20% of thin film thickness, the substrate effect is insignificant. Whereas the hard film on soft substrate should be treat as a measurement for a system where substrate effect is always significant. Our results also show profound indentation size effect for thin films with thickness below 100nm. This depth dependence phenomenon is due to the break down of Oliver and Pharr formula derived from continuum mechanics for ultra shallow indentation depth.
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吳定曄. "Application of a new seed template on tantalum nitride barrier layers to electroless plating of copper thin films and interconnects." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/65396338576903156200.
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Chang, Chih-Chieh, and 張智傑. "Plasma-Enhanced Atomic Layer Deposited Thin Films as Diffusion Barriers on Porous Ultralow-k Dielectrics for Cu Interconnect Technology." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36382520693494328737.
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博士國立交通大學
材料科學與工程學系
99
With the dimensional shrinkage of microelectronic devices, atomic layer deposition (ALD) becomes a very attractive method for the deposition of ultrathin films. Beacuse ALD can deposit uniform ultrathin thin films on substrates with high aspect ratio structures, it has been implemented in the Cu interconnect process, whcin requires diffusion barriers of high conformality and precise thickness. In addition, ALD also meets challenging requirements in many other IC processes, such as the deposition of high quality dielectrics to fabricate trench capacitors for DRAM. We use plasma-enhanced ALD (PEALD) to deposit TaNx diffusion barriers on mesoporous SiO2 low-k dielectrics. The self-limiting nature of the surface reactions can produce uniform TaNx films of high thermal stability on the mesoporous SiO2 low-k dielectrics. However, the porous nature of the porous dielectrics leads to a difficulty for the integration of the dielectrics into Cu interconnect technology. Surface pores are penetration pathway of adverse impurities into the porous dielectrics, such as moisture uptake during cleaning and plasma species diffusion during etching. O2 and Ar plasmas were used to modify the surface of the mesoporous dielectric in a high density plasma chemical vapor deposition (HDP-CVD) system, and both of the treatments produced a densified oxide layer a few nanometer thick. The pore sealing treatment could effectively prevent metallic atoms from diffusing into the mesoporous dielectric during the PEALD process and enhance retardation of moisture uptake. Adhesion properties of PEALD diffusion barriers with the Cu interconnect were also studied. The TaNx nitride barrier usually exhibit good diffusion barrier properties, but they often has a poor mechanical strength at the interface with the Cu layer. In the study, we used hydrogen plasma treatment and rapid thermal annealing (RTA) in hydrogen ambient to reduce the nitrogen content in the surface layer of the PEALD-TaNx barrier layer. The surface treatment greatly improved adhesion of the TaNx barrier layer with Cu and the thermal stability of the TaNx/Cu film stack. We also deposited Ru/RuNx bilayer barriers on mesoporous SiO2 dielectrics by an in situ two-step PEALD process for the application of seedless Cu electroplating. Ru is a stable transition metal in air and has low electrical resistivity, but it has worse diffusion barrier properties than RuNx. We sequentially deposited 3.5 nm thick RuNx and 0.5 nm thick metallic Ru on the mesoporous dielectric by PEALD. The metallic Ru capping layer can retard thermal decomposition of the underlying RuNx layer and provides the barrier surface a low electrical resistance for direct Cu electroplating. The Ru/RuNx bilayer exhibits satisfactory thermal stability and electrical characteristics, and is suitable for the seedless Cu electroplating process in nanometer scale interconnect technology.
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Shin, Jinhong 1972. "Growth and characterization of CVD Ru and amorphous Ru-P alloy films for liner application in Cu interconnect." Thesis, 2007. http://hdl.handle.net/2152/3684.
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Copper interconnect requires liner materials that function as a diffusion barrier, a seed layer for electroplating, and an adhesion promoting layer. Ruthenium has been considered as a promising liner material, however it has been reported that Ru itself is not an effective Cu diffusion barrier due to its microstructure, which is polycrystalline with columnar grains. The screening study of Ru precursors revealed that all Ru films were polycrystalline with columnar structure, and, due to its strong 3D growth mode, a conformal and ultrathin Ru film was difficult to form, especially on high aspect ratio features. The microstructure of Ru films can be modified by incorporating P. Amorphous Ru(P) films are formed by chemical vapor deposition at 575 K using a single source precursor, cis-RuH₂(P(CH₃)₃)₄, or dual sources, Ru₃(CO)₁₂ and P(CH₃)₃ or P(C6H5)₃ The films contain Ru and P, which are in zero-valent states, and C as an impurity. Phosphorus dominantly affects the film microstructure, and incorporating > 13% P resulted in amorphous Ru(P) films. Metastable Ru(P) remains amorphous after annealing at 675 K for 3 hr, and starts recrystallization at ~775 K. The density of states analysis of the amorphous Ru(P) alloy illustrates metallic character of the films, and hybridization between Ru 4d and P 3p orbitals, which contributes to stabilizing the amorphous structure. Co-dosing P(CH)₃ with Ru₃(CO)₁₂ improves film step coverage, and the most conformal Ru(P) film is obtained with cis-RuH2(P(CH₃)₃)₄; a fully continuous 5 nm Ru(P) film is formed within 1 µm deep, 8:1 aspect ratio trenches. First principles density functional theory calculations illustrate degraded Cu/Ru adhesion by the presence of P at the interface, however, due to the strong Ru-Cu bonds, amorphous Ru(P) forms a stronger interface with Cu than Ta and TaN do. Cu diffusion studies at 575 K suggests improved barrier property of amorphous Ru(P) films over polycrystalline PVD Ru.