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Десятниченко, Алексей Владимирович. "Электромагнитно-акустический толщиномер для контроля металлоизделий с диэлектрическими покрытиями." Thesis, НТУ "ХПИ", 2015. http://repository.kpi.kharkov.ua/handle/KhPI-Press/17117.
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Диссертация на соискание ученой степени кандидата технических наук по специальности 05.11.13 – приборы и методы контроля и определения состава веществ. – Национальный технический университет "Харьковский политехнический институт", Харьков, 2015.
Диссертация посвящена решению важной научно-практической задачи обеспечения ультразвукового контроля толщины металлоизделий электромагнитно-акустическим методом при наличии диэлектрических покрытий (зазоров) толщиной до 10 мм. В работе выполнен анализ существующих акустических методов и устройств для измерения толщины, которые широко используются в отечественной и зарубежной промышленности, рассмотрены основные их преимущества и недостатки. Методы разделяются по типу контакта датчика с объектом контроля на два основные класса: контактные и бесконтактные. Бесконтактные на сегодняшний день являются наиболее перспективными. К ним относятся методы, основанные на: воздушно акустической связи, термо- и оптико-акустическом эффектах, а также на эффектах электрического и электромагнитного полей. По результатам анализа недостатков приведенных методов, выделен наиболее перспективный – ЭМА метод. Рассмотрены вопросы выбора оптимального сигнала для возбуждения акустических колебаний ЭМА методом. Приведены расчеты принимаемой энергии для общего случая при зеркальной схеме контроля, когда передающий и приемный датчики не располагаются соосно по высоте изделия. Рассмотрены модели расчетов для зеркально теневой схемы контроля, отдельно для режимов излучения ЭМАП в виде длинных и коротких импульсов. Дан анализ целесообразности использования вариантов зондирующего сигнала с различными соотношениями длины импульсов и расстояний между ними. Рассмотрена электрическая модель выходного каскада усилителя зондирующего сигнала и датчика, описаны особенности ее работы. Приведены результаты экспериментальных исследований и разработок, направленных на повышение качества и производительности контроля толщины с использованием ЭМА метод возбуждения и приема акустических колебаний. Представлена конструкция макета ЭМА преобразователя для контроля металлоизделий при наличии зазора между датчиком и изделием. Рассмотрены вопросы построения передающего и приемного аналоговых трактов, приведены схемотехнические и конструктивные решения. Приведены результаты исследований зависимости амплитуды сигнала на генерирующей обмотке ЭМАП от напряжения питания усилителя. Проведены исследования зависимости уровня полезного сигнала он напряжения на передающей обмотке датчика. Исследовано влияния зазора на уровень полезного сигнала. Приведены результаты зависимости длительности «мертвой» зоны от зазора и способы ее снижения. Определены факторы, влияющие на точность контроля. Разработан толщиномер основанный на электромагнитно акустическом методе возбуждения и приема акустических волн, приведены результаты этой разработки. Рассмотрены особенности построения его составных частей. Рассмотрены алгоритмы цифровой обработки принятого сигнала. Проведена оценка метрологических характеристик разработанного прибора, изготовлен контрольный образец для метрологического обеспечения толщиномера. Приведено сравнение нового прибора с существующими аналогами.Thesis for granting the Degree of Candidate of Technical sciences in speciality 05.11.13 – Devices and methods of testing and materials structure determination. – National technical university "Kharkiv Politechnical Institute", Kharkiv, 2015. Thesis is devoted to solution of important theoretical and practical task to ensure ultrasound control of the metal products thickness by using electromagnetic-acoustical method in cases of dielectric coatings (gaps) with thickness up to 10 mm. Work includes analysis of existing acoustic methods and devices for thickness measurement, their main advantages and disadvantages are reviewed. Based on the results of analysis of the given disadvantages, the most advanced ways was set off - electromagnetic-acoustical (EMA) method. The problems of selection of the optimal signal agitate sonorous vibrations by EMA method were reviewed. Calculations of the taken energy are given for the analysis of the practicability to use variants of probing signal. Electric model of amplifier output stage of probing signal and sensor is reviewed, peculiarities of its operation are described. Results of researches and developments dedicated to increase thickness measurement quality and efficiency are given. Matters to build of the transmitting and receiving analog tracts are reviewed. The signal level dependence on voltage research on sensor's transmitting winding are conducted. Impact of a gap on the signal level was examined. Results of the dependence of dead spot length on a gap and methods to its reduction are given. Factors affecting accuracy of control are determined. EMA thickness gauge was designed. The main factors of design are examined. The digital processing algorithm of the received data was reviewed. Metrological characteristics of the developed device were made.
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Десятніченко, Олексій Володимирович. "Електромагнітно-акустичний товщиномір для контролю металовиробів з діелектричними покриттями." Thesis, НТУ "ХПІ", 2015. http://repository.kpi.kharkov.ua/handle/KhPI-Press/17045.
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Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.11.13 – прилади і методи контролю та визначення складу речовин. – Національний технічний університет "Харківський політехнічний інститут", Харків, 2015.
Дисертація присвячена вирішенню важливої науково-практичної задачі, яка полягає у забезпеченні ультразвукового контролю товщини металовиробів електромагнітно-акустичним методом при наявності діелектричних покриттів (зазорів) товщиною до 10 мм.
У роботі виконано аналіз існуючих акустичних методів і пристроїв для вимірювання товщини, розглянуті основні їх переваги та недоліки. За результатами аналізу недоліків наведених методів, виділений найбільш перспективний – ЕМА метод.
Розглянуто питання вибору оптимального сигналу для збудження акустичних коливань ЕМА методом. Наведено розрахунки прийнятої енергії. Дано аналіз доцільності використання різних варіантів сигналу зондування. Розглянуто електричну модель вихідного каскаду підсилювача сигналу зондування і датчика, описано особливості її роботи.
Наведено результати експериментальних досліджень і розробок спрямованих на підвищення якості та продуктивності контролю товщини. Представлена конструкція макета ЕМА перетворювача для контролю металовиробів при наявності зазору між датчиком і об'єктом. Розглянуто питання побудови передавального і приймального аналогових трактів, наведені конструктивні рішення. Досліджено залежність амплітуди сигналу на генеруючої обмотці ЕМАП від напруги живлення підсилювача. Проведено дослідження залежності рівня корисного сигналу він напруги на передавальній обмотці датчика. Досліджено впливу зазору на рівень корисного сигналу. Наведено результати залежності тривалості "мертвої" зони від зазору і способи її зниження. Визначено фактори, що впливають на точність контролю.
Розроблено ЕМА товщиномір, розглянуті особливості побудови та питання схемотехніки його складових частин. Розглянуто алгоритми цифрової обробки прийнятого сигналу. Наведено опис виготовленого контрольного зразка для метрологічного забезпечення толщиномера.Thesis for granting the Degree of Candidate of Technical sciences in speciality 05.11.13 – Devices and methods of testing and materials structure determination. – National technical university "Kharkiv Politechnical Institute", Kharkiv, 2015. Thesis is devoted to solution of important theoretical and practical task to ensure ultrasound control of the metal products thickness by using electromagnetic-acoustical method in cases of dielectric coatings (gaps) with thickness up to 10 mm. Work includes analysis of existing acoustic methods and devices for thickness measurement, their main advantages and disadvantages are reviewed. Based on the results of analysis of the given disadvantages, the most advanced ways was set off - electromagnetic-acoustical (EMA) method. The problems of selection of the optimal signal agitate sonorous vibrations by EMA method were reviewed. Calculations of the taken energy are given for the analysis of the practicability to use variants of probing signal. Electric model of amplifier output stage of probing signal and sensor is reviewed, peculiarities of its operation are described. Results of researches and developments dedicated to increase thickness measurement quality and efficiency are given. Matters to build of the transmitting and receiving analog tracts are reviewed. The signal level dependence on voltage research on sensor's transmitting winding are conducted. Impact of a gap on the signal level was examined. Results of the dependence of dead spot length on a gap and methods to its reduction are given. Factors affecting accuracy of control are determined. EMA thickness gauge was designed. The main factors of design are examined. The digital processing algorithm of the received data was reviewed. Metrological characteristics of the developed device were made.
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Bhuiya, Md Omar F. "DESIGN AND OPTIMIZATION OF A STRIPLINE RESONATOR SENSOR FOR MEASUREMENT OF RUBBER THICKNESS IN A MOVING WEB." University of Akron / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=akron1164650416.
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Berggren, Amanda. "Long-term results regarding healing andcomplications after 25-gauge pars planavitrectomy for large full-thickness macularholes." Thesis, Örebro universitet, Institutionen för medicinska vetenskaper, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:oru:diva-93339.
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Introduction A full-thickness macular hole (FTMH) is a round deformity in the fovea that involve alllayers of the neurosensory retina. The condition is usually symptomatic and is associatedwith a decreased visual acuity (VA). Large FTMHs are associated to a larger decrease in VA.To treat FTMH pars plana vitrectomy (PPV) is performed to repair the hole. There aredifferent dimensions of instruments in PPV but limited information on the outcome usingeach dimension. Aim This study aims to assess the healing rate of large FTMHs after 25-gauge vitrectomy. Methods The study is a retrospective record review. Patients were identified through the surgicalintervention registry at the Department of Ophthalmology, USÖ. The study included largeFTMHs (diameter > 400 μm) who underwent 25-gauge PPV at USÖ between 2015-2017. Results After 25-gauge PPV 19 (82.6%) out of 23 included eyes healed. No significant difference inhealing rate between subgroups of different sized FTMHs was discovered. Out of 4 eyes thatfailed to heal, 1 patient underwent a reoperation and the other 3 either chose not to or it wasdeemed not indicated. A statistically significant increase in mean VA postoperatively wasobserved. The most reported complications postoperatively were gas cataract and atemporary increase in intraocular pressure. In 7 cases the PPV led to an accelerateddevelopment of cataract and cataract surgery. Conclusion The majority of FTMHs healed after 25-gauge PPV and the mean VA increased after surgery.The most common complications were secondary cataract and temporary increase in IOP.
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Rennie, Michael. "Characterisation of molecular nitrogen implanted silicon for multiple thicknesses of gate oxide in a 0.5μm CMOS process." Thesis, University of Edinburgh, 1996. http://hdl.handle.net/1842/11294.
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The continuing scaling of CMOS devices for performance advantages has resulted in an accompanying thinning of the gate oxide insulator and an increase in the level of hot carrier effects for a fixed power supply voltage. Nitrogen incorporated into the gate oxide through the nitridation of silicon oxide from a gas source has been extensively studied to improve the robustness of devices to hot carrier effects. Although reduced growth rates have been observed with nitrided oxides, there has not been a comprehensive study of MOS device performance utilising this mechanism to selectively grow gate oxides with different thicknesses. One of the advantages is their potentially improved hot carrier robustness through the incorporation of nitrogen. The dry oxidation kinetics of silicon implanted with low dose (1014-1015 cm-2) molecular nitrogen has been extensively studied in this work to establish the possibility of using the implanted nitrogen for adjusting the oxidation rate of silicon. This work established that the oxidation rate is determined by the pile-up of nitrogen at the silicon oxide-silicon interface in a surface reaction rate limited process. The nitrogen implanted silicon technique has been incorporated into a 0.5μm CMOS process to determine the feasibility of growing multiple thicknesses of gate oxide during a single oxidation step. In this work, the gate oxide is grown after direct implantation of molecular nitrogen into both NMOS and PMOS device areas. This allows for easy integration into an existing process as the implantation is carried out during the same step as threshold adjustment implants. The hot carrier reliability and boron penetration properties of gate oxides grown under high nitrogen dose conditions are improved in a similar way to nitridation from a gas source. Increased nitrogen dose in the silicon however, shows a deterioration of the MOS device mobility and gate oxide integrity. The localised thinning of the gate oxide is shown to be responsible and the inhomogeneous redistribution of nitrogen is attributed to the deterioration of the device characteristics. Sufficient device performance and reliability however can be achieved using low dose molecular nitrogen such that the simultaneous growth of 150Å and 90Å gate oxides can be realised on a CMOS technology microprocessor chip for 3.3V and 5V power supply interface applications.
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Civín, Adam. "Stanovení zbytkové napjatosti metodou vrtání otvoru s využitím MKP." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2008. http://www.nusl.cz/ntk/nusl-228325.
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Residual state of stress in structural materials affect positively or negatively behaviour of component parts. The goal of this scope is not to deal with possible process of creating residual stresses neither about elimination of residual stress, but is focused how to determine magnitude of residual stress by hole-drilling method. We need to know magnitude and direction (angular orientation) of principal stresses to determine how residual state of stress affects behaviour of specimen. The most widely used modern technique for measuring residual stresses is hole-drilling strain-gage method. Hole-drilling method is in scope of this paper and is restricted only for measuring uniform residual stresses of steel specimens with finite dimensions. Structural, linear, elastic and isotropic material model is used with material properties =0,3 and E=2,1[10]^5 MPa. For correct application of this method we need to determine calibration coefficients “a“ and “b“ first. These coefficients are used to determine magnitude and direction of residual stresses in specific depth and diameter of drilled hole for materials with finite dimensions. Geometry and shape of model is simply represented by block with planar faces. Note that numerical determination of calibration coefficients is useful only for one type of strain gauge rosette RY 61 S. Main goals of this thesis are motivation and request to clearly report effectiveness, accuracy and applicability of calibration coefficients in relation to thickness of specimen, dimensions of drilled hole, condition of “through” or “blind” hole and number of drilled increments. High quality and accuracy of created numerical model is necessary too. Numerical simulation of residual stresses by MKP needs to be done to obtain requested results. All results are presented by 3D, 2D graphs and tables and compared with analytical results or results from other authors. Although is this publication focused on numerical modeling using FEM, hole-drilling method has many significant restrictions. The most substantial of them is influence of eccentricity of drilled hole, creation of stress concentration near drilled area and subsequent plastification, influence of geometrical inaccuracy of hole, etc. All these aspects have significant influence of determining calibration coefficients and can not be included into numerical simulation. These problems are closely discussed in background research. All obtained results should be helpful for practical use of calculated calibration coefficients to determine uniform residual stresses of specimens with various thickness and drilled hole. All these results are also applicable only for one type of strain gauge rosette, which is RY 61 S.
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Hénaux, Stéphane. "Contribution à l'amélioration des méthodes de caractérisation électrique des matériaux Silicium Sur Isolant (SOI)." Université Joseph Fourier (Grenoble), 1998. http://www.theses.fr/1998GRE10116.
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L'essor actuel des technologies soi est lie a la production d'un materiau de depart de qualite, dont le juge final est le comportement electrique des circuits integres. Cette these decrit des ameliorations et de nouvelles idees pour l'evaluation des proprietes electriques des materiaux soi. Les methodes presentees sont appliquees en priorite au nouveau materiau unibond. Nous donnons d'abord une vue d'ensemble des technologies soi et des methodes de caracterisation disponibles. Nous exposons ensuite notre contribution en commencant par la mesure electrique d'epaisseur du film de silicium dans un dispositif mos, pour laquelle nous proposons une extension d'une methode existante. La duree de vie des porteurs dans le film de silicium est ensuite etudiee par les techniques recentes des transitoires de courant de drain dans des transistors mos. Nous montrons la necessite d'une approche statistique pour comparer entre eux divers materiaux soi. Nous presentons ensuite des methodes de caracterisation rapide, ne necessitant pas la fabrication de dispositifs. L'oxyde enterre et le substrat silicium sous-jacent sont etudies par sonde a mercure, apres elimination du film de silicium par voie chimique. Pour la mesure du dopage residuel du film mince soi, nous evaluons les possibilites du pseudo-transistor mos. Nous proposons par ailleurs une nouvelle methode pour determiner tres rapidement et sans ambiguite le type, applicable aux tres faibles dopages. La derniere partie est consacree a l'oxyde de grille des technologies mos-soi. Une etude en time dependent dielectric breakdown sur dispositifs mos nous permet de montrer que le comportement en claquage intrinseque est identique sur soi et sur silicium massif. Pour s'affranchir du cout et de la longueur d'une telle etude, nous proposons une nouvelle methode simple de caracterisation d'oxyde de grille sur soi, ne necessitant pas d'autre etape technologique que la realisation de l'oxyde lui-meme.
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Fan, Kung Ming, and 范恭鳴. "Multiple-gate-oxide-thickness Process Development by NH3 Plasma Nitridation." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/61329243704455919302.
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碩士長庚大學
半導體研究所
90
Abstract According to the ITRS prediction, the equivalent oxide thickness (EOT) will be scale to 0.9-1.4nm in the 90nm technology node. As the oxide thickness less than 3nm, the gate leakage current and boron penetration through oxide are more seriously. Replace the SiO2 by High-k dielectric materials and nitrogen implant in the silicon surface or dielectrics are the most popular approaches to overcome these two issues. SOC is the current trend for the future CMOS processes, but it increases the process complexity, one of these challenges is the multiple gate oxide thickness, which in order to have lower power consumption, high speed and circuit stability. Oxidation growth rate can be reduced by nitrogen implant in the silicon substrate and have being widely employed. In this thesis, nitrogen incorporated in the silicon surface by NH3 plasma. We discussed its oxidation growth rate and electrical characteristics of MOS capacitors. The oxidation growth rate can be reduced maximum about 80﹪compare to the control sample. Besides, we improved its oxide quality by NH3 plasma treatment compared to the direct rapid thermal (RT) N2O oxidation. We find that the low charge trapping, low bulk trap densities, higher immunity to SILC and higher charge to soft-breakdown by NH3 plasma treatment before RT N2O oxidation. In this experiment, gate voltage shift has a minimum value of 10 mV in constant current stress and negligible hysteresis effects of C-V characteristic, the flatband voltage shift is 8.5 mV. This process could achieve both multiple gate oxide thickness and improve oxide reliability.
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Yen, Yuh-Ren, and 顏育仁. "Study on Thickness Uniformity of Rapid Thermal Thin Gate Oxide." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/49874845421521239969.
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碩士國立臺灣大學
電機工程學研究所
89
Two main topics are discussed in this thesis. One is about the electrical characteristics of MOS capacitor with non-uniform gate oxide and the other is the uniformity improvement of gate oxide prepared by Rapid Thermal Processor(RTP). In order to investigate the influence of non-uniform gate oxide on the electrical characteristics of MOS capacitors, we intentionally grow a non-uniform thickness oxide by putting a quartz ring beneath the monitored wafer. A thinner oxide is grown on the regions contacted with the quartz ring since heat is conducted by the contact quartz. The result oxide is a hill-shape structure. The Si beneath the thinner and thicker oxide of this structure was found to sense a tensile stress while a compressive stress exists on the Si beneath the moderate thickness oxide. We adopt this oxide structure as the gate oxides of our MOS capacitors. The measured I-V curves of these MOS capacitors show that there is a relation between the stress on Si and the reverse-saturation current. The MOS capacitor with a tensile stress on Si will have a lower revers-saturation current. This is quite important to the thin gate oxide reliability in ULSI. The reason why tensile stress leads to lower reverse-saturation current is also given in this thesis. With the ability to perform heat cycles on a wafer rapidly and with low thermal budget, RTP has become a key technology in the fabrication of advanced semiconductor devices. However, the most common criticisms of RTP are about the thermal non-uniformity, and this problem becomes earnest as oxide thickness shrinks for the need of ULSI devices. A great deal of effort has been put into improvement of radiant uniformity. For high thermal uniformity systems, however, heat convection does play an important role. From simulation result of flow filed, we see that the cold gas flow toward the wafer surface where exhibits a lower pressure due to the flow away of gas by the buoyancy at the wafer center. Our work is to suppress the upward gas flow by putting a quartz cap above the monitored wafer. Since this setting prevents the cold gas drawn form wafer edge to wafer center gas, we suppose that the temperature uniformity can be improved. This supposition is proven to be true from both simulation and experimental results. Furthermore, since natural convection tends to balance the temperature variation, the non-uniform temperature is self-compensated by the gas flowing in the gap between the wafer and the cap.
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Kun, Huang Tao, and 黃道坤. "The impact of poly gate sidewall oxide thickness on MOSFET’s gate-induced drain leakage behavior." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/12981841264445016012.
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碩士長庚大學
電子工程研究所
93
The leakage in the drain region is a crucial issue for scaling of the MOSFET. The off-state gate-induced drain leakage (GIDL) current is one of the major contributors to the overall MOSFET leakage. GIDL is induced by band-to-band tunneling (BTBT) effect in the depletion region and generated in the gate to drain overlap region with high electric field. GIDL leakage is a function of many process parameters such as spacer material, spacer width, gate oxide thickness, doped concentration; anneal temperature, and poly re-oxidation conditions etc. Devices used in this work consist of a gate oxide of 4nm or 6nm, and a spacer width of 25nm. Three different poly re-oxidation conditions result in 3 gate sidewall oxide thicknesses of 4nm, 6nm, and 8nm, measured on the shallow trench isolation processed wafers in the experiments. The impact of different gate sidewall oxide thicknesses (4nm, 6nm and 8nm) on device threshold voltage (Vt), overlap capacitance (Cgd), and off-state GIDL leakage current was investigated. This study shows that the use of thin sidewall oxidation thickness further increases GIDL leakage current, getting high overlap capacitance, and decrease threshold voltage (Vt). Finally, a comparison of GIDL behavior in n-poly gate surface-channel NMOS and n-poly gate buried channel PMOS is summarized.
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Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ernet.in/2005/3489.
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Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally efficient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, efficient compact models for these new transistors are required for their successful utilization in integrated circuits.
Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational efficiency at the same level. Such effort aims to generalize the compact model and also to capture the oxide thickness asymmetry effect, which might prevail in practical devices due to process uncertainties and thus affects the device performance significantly.
However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work effort has been put to include Non-Quasistatic (NQS) effects, different small-geometry effects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry effects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.
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Chen, Hui-Yen, and 陳慧燕. "Improved the uniformity of Gate Oxide Thickness of High Voltage Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/41002387735940640452.
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碩士國立交通大學
工學院半導體材料與製程設備學程
101
The purpose of this study is to improve the uniformity of gate oxide thickness in 0.15μm high voltage device. Thermal oxidation process was used to fabricate this gate oxide. During oxidation process, gate oxide needs overcome the thermal stress distribution caused from the Si substrate. In this paper, the uniformity of gate oxide thickness was improved through investigation of the position of the wafer, oxidation method, annealing method and “sacrifice etching” of oxide layer. Change annealing method from RTA to furnace can improve this issue but the thermal budget concerned high voltage device. The sacrifice etching of oxide is the final solution.
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Huang, Yao-De, and 黃耀德. "Study on the Relation Between Gate Thickness and Molding Parameters Using PVT Diagram." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/wstz2h.
Full textAbstract:
碩士中原大學
機械工程研究所
106
Before the product enters actual mass production, a production tool trial is often required, because a brand new mold is difficult to produce the finished product of the required specifications directly. At this time, the molded product usually has some disparities with the expected size. Traditionally, these disparities are supplemented by factory’s experienced workers relying on their personal experience to adjust the molding parameters or modify the mold appropriately instead of regulating product quality in a standardized process and this process takes a lot of time and cost. Consequently, a new mold design with movable gate was established in this study to investigate the effect of gate thickness on the filling and packing, and PVT monitoring technology was used to record the temperature, pressure and specific volume in the cavity during the molding process. And through the molding experiment, the influence of the thickness of the gate on the temperature, pressure and specific volume during molding was acknowledged to establish the application basis of the movable gate mold. In this study, in order to build a movable gate in the mold, the servo motor was used as the power source and composed with mechanism design so that the gate can move backward and forward to change the gate thickness. At the same time, three temperature sensors were buried in the mold cavity, and three pressure sensors were buried in the mold core to establish a PVT monitoring system. The experimental materials used ABS (PA-756), and experiment was conducted by using the movable gate mold with three gate thicknesses of 1 mm, 2 mm, and 3 mm and experimental parameters include melt temperature, mold temperature, filling time, packing pressure, packing time, and cooling time. The results show that increasing the gate thickness contributes to pressure transmission and maintenance and reduces shear heat generation under different experimental parameters, thus reducing the shrinkage of the product. The result is 3mm in gate thickness, 220°C melting temperature, 30°C mold temperature, 0.5 second filling time, 480% packing pressure, sufficient packing time (10.52 seconds for gate thickness 3mm), and 15.1 seconds cooling time have the best product quality.
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Wu, Jiunn-Pey, and 吳俊沛. "Analysis on Gate-Oxide Thickness Dependence of Hot-Carrier- Induced Degradation in Submicrometer LDD nMOSFET's." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/44807502258254042698.
Full textAbstract:
碩士國立交通大學
電子研究所
83
In this thesis, gate-oxide thickness dependecnce of hot- carrier-induced degradation is investigated for LDD nMOSFET' s. It is shown that a thinner gate oxide LDD nMOSFET's causes larger drain current degradation under the same bias stress condition. However, it has been reported that a thinner gate oxide conventional nMOSFET shows smaller degradation. Since the dominant degradation mechanism for the LDD device differ from the conventional device, due to the spacer-induced degradation, an improved drain linear-current degradation model is developed in order to investigate the degradation mechanism in LDD MOSFET. A new degradation mechanism is introduced to account for the increasing of resistance in the n- region due to the generation of interface states. Further, since the effective channel length and the source-drain series resistance of an LDD device are gate-voltage dependent, the paired Vg method is used to extract the effective channel length and the series resistance. It can be found that this generalized drain current degradation model gives a good agreement to the measured data for different gate oxide thickness. Based on this model, the gate-oxide thickness dependence of degradation can be well analyzed.
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Yu, Li-Wei, and 游禮維. "A Study on Channel Thickness Effect of Double-Gate Polycrystalline-Silicon Junctionless Thin-Film Transistors." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/4j5mnq.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
107
In this paper, the effect of different channel thickness on the Junctionless Thin Film Transistor is discussed, and also the upper gate and double gate are concerned. The channel thickness is divided into three channel thicknesses: 10nm, 8nm and 5nm. According to the measurement results, the thickness of the 10 nm channel is not controlled by upper gate, and it is necessary to use the double gate to improve. Therefore, the 8 nm and 5 nm channel thickness would be discussed subsequently in the later discussion. The on/off characteristics, the drain-induced barrier lowering, the short channel effect, and the leakage current characteristics are discussed in the devices of channel thickness 8 nm and 5 nm, respectively. It can be found that the channel thickness of 8nm and 5nm devices can improve the subthreshold swing by using double gate. This is because the gate control capability is improved, and the better the gate control capability can be seen when the channel is thinned to 5nm. Therefore, it is known that the device of channel thickness 5 nm and using double gate have the best immunity to short channel effect.
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Tan, Yu-De, and 談昱德. "Effect of Gate Metal Thickness on The 2-State Characteristics of MOS Structure with Ultrathin Oxide." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/59894679539440376075.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
103
In this work, we study the effect of the thickness of gate metal on the characteristics of Metal-Oxide-Semiconductor capacitor (MOSCAP) device with ultrathin oxide layer. The embedded Dynamic Random Access Memory (eDRAM) becomes more and more important in semiconductor industry with application of System on Chip (SoC) and Application Specific Integrated Circuit (ASIC). The pattern of the device is a long strap connected to a square contact pad in this work, which is designed for higher gate resistance with ultrathin gate metal. The device has two operation modes, i.e., current mode and capacitance mode. For current mode operation, the device exhibits 2-state characteristic with opposite readout current sign, which we define as ‘1’-state and ‘-1’-state. The device has retention time constant of about 210ms, which matches the specification of ITRS. And it has endurance of at last one million cycle of write operation. For capacitance mode operation, the device shows CV hysteresis with thinner gate metal and thin oxide layer. The level of CV hysteresis is sensitive to sweeping range and stress holding time. And the two factors are tradeoff for high sensitivity. The capacitance 2-state characteristic of the MOSCAP device has the potential to evolve into transistor memory. The device discussed in this work has advantage of simple structure, smaller feature size, CMOS process compatible, and low operation power consumption.
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Chang, Po-Kai, and 張博凱. "Determination of Ultrathin Gate Oxide Thickness (＜2.0 nm) Using Low Dissipation Factor Regions of C－V Measurements." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/97235682268489213225.
Full textAbstract:
碩士臺灣大學
電子工程學研究所
95
With the expeditious development of modern CMOS technology, the equivalent oxide thickness (EOT) of gate dielectric is systematically downscaled into the ultrathin range (＜2.0 nm) and becomes a key factor in the precise determination of many device parameters, such as electron/hole mobility, oxide charge density, interface trap density, breakdown field strength, etc. However, C－V curves of ultrathin oxides near the accumulation region show a disposition to roll off abruptly due to exponentially-increasing leakage current and series resistance; hence the two-frequency correction method was proposed to work out an empirical solution based on three-element circuit model. Once the oxide thickness shrank down below 2.0 nm, the error of measured capacitance could be dreadfully large, unless the two frequencies were chosen with caution. In this work, a new approach to the estimation of ultrathin oxide thickness from C－V measurement has been demonstrated. By choosing an adequate interval on the C－V curve where the dissipation factor is low enough, we can perform a simple linear regression, then comparing the experimental slope with theoretical values to find out the actual oxide thickness. This technique is valid for a 1.6 nm SiO2 capacitor, while the two-frequency correction method can hardly determine the correct value.
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Lee, Jung-Ming, and 李榮明. "A optimization study of SiNx film thickness and uniformity for TFT-LCD isolation gate by Taguchi Method." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/42740817691997066339.
Full textAbstract:
碩士國立高雄第一科技大學
機械與自動化工程研究所
102
Time of high-pixel , high-resolution of large-size LCD panel is coming . LCD process technology requires constant innovation , in order to achieve large output , low cost and product quality optimization . Taguchi method has been extensively improves the single product , quality optimization in this field . However , the influence factors of the product process are two or more than two quality characteristics , and the design parameter only relying on professional engineer’s experience of choosing the control factors . It is easy to cause uncertainty and fuzziness , due to engineers’ recognizes are different . Besides , it is a tough decision for engineers to choose best selection of combination , considering of each quality characteristic is relevance . In view of this subject , the research firstly uses Taguchi Method by processing one single quality ; calculate separately the S/N Ration . Finally , it unifies the Analysis of Variance to find the S/N Ration , the highest data is best , to determine the process optimization . For demonstrating the effectiveness and the usability of the research , using the case – The study of Film Thickness Uniform Optimal Parameters for Gate Isolation Layer Process by Fuzzy - Based Taguchi Method to analysis the Pattern of numerical of LCD . Demonstrating the best parameter, combination so that it can achieve three goals ; shorten the experimental duration , reduce the experimental cost , and promote the optimization of the product quality .
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Yang, Deng-Wei, and 楊登偉. "Local Strain Effects on pMOSFETs by Different Gate Structures and Nitride Thicknesses." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/08928482545974405925.
Full textAbstract:
碩士逢甲大學
產業研發碩士班
96
Strain is a kind of mobility enhancement technologies for device performance enhancement. It is considered as a simplest method to improve device characteristics and easy to integrated in modern process. We have investigated the local strain effects on pMOSFETs with the traditional poly-Si、poly-SiGe and the stack of poly-SiGe and amorphous Si (poly-stack) gates by different thicknesses of silicon nitride (SiN) capping. In this experiment, the traditional poly-Si gated pMOSFETs with SiN capping present the better performance. Introducing compressive strain by PECVD SiN capping into the traditional poly-Si gated pMOSFETs are more effective than other counterparts. There is a compensation of strain existing in poly-stack gated pMOSFETs leading to the poorer performance enhancement. The poor quality of silicon dioxide and worse device characteristics are found in poly-SiGe gated pMOSFETs. It presents that poly-SiGe is not suitable for depositing on SiO2 directly. In addition, the mobility enhancement is not in proportion to the thicknesses of SiN capping. The stress introduced by SiN capping saturates as the thicknesses achieves 100nm in this experiment.
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Liang, Chia-Lin, and 梁佳琳. "Effects of Tiny Grain and Channel Thickness on the Performance Variation of the Vertical Gate SONOS Memory Cell." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/75226969442873966923.
Full textAbstract:
碩士國立交通大學
電子工程學系 電子研究所
104
Three-dimensional (3D) memory structure has been the main trend of NAND flash memory in industry. The grain size, grain number, and grain boundaries of the poly-Si channel may affects the memory characteristics. In this work, we fabricated the vertical gate thin film transistor SONOS (VG TFT SONOS) devices with different grain sizes and different channel thicknesses, and study their on the fresh state, Fowler-Nordeim (FN) programming and erasing speed, and the variations. In the previous research, we found that the grain boundary containing lots of trapping centers may have smaller band bending than the region without grain boundary; thus, the voltage drop on the tunneling oxide at grain boundary will be higher than the other region, and then the programming speed can be enhanced. While the grain number increases in the channel, the speed and the number of electrons being injected into the nitride layer will be increased. However, the smallest grain size in previous work is comparable with the channel length, so the Vth variation and the S.S. variation are large. Therefore, we reduce the grain size to 19 nm and study the effects of such a tiny grain. In the comparison of Fowler-Nordeim programming speed and erasing speed, as the grain size becomes far smaller than channel length, the device not only have faster operate speed because of the large number of grain boundaries but also exhibits smaller Vth variation and S.S variation which are dominated by grain number and the variation of grain boundary trap density. Increasing the total thickness of the stacked layers would increase the process hardness. Furthermore, due to the etching technology limitation, the profiles of topmost device and the bottommost device may differ a lot. Hence, we considered to reduce the channel thickness to increase the stacked layers in the same etching depth. In this work, it is observed that while the channel thickness comes thinner, the grains of the cross section of the poly-Si channel becomes columnar. This reduces the probability that carriers be trapped or be scattered by grain boundary trap, and then the device will have higher on-current. The Fowler-Nordeim programming speed and erasing speed will have obviously improve as the channel thickness gets thinner. According to the TCAD simulation, devices with thinner channel thickness has stronger electric field on the tunnel oxide than devices with thicker channel thickness. The stronger electric field provides faster programming and erasing speed. The S.S. variation of the short channel devices is larger than that of the long channel devices. We suspected that the grain number of short channel devices is few, 4 to 6 grains, so that the grain boundary trap density variation would dominate the S.S. variation. By improving the processes, the protrusion of channel corner is reduced from 13 nm to 6.4 nm. Although this is a notable improvement, the corner effect still degrade the memory endurance seriously. After 100 P/E cycles, the memory window closes and the S.S. becomes progressively worse. This is because of the protruded corner which induces huge numbers of electrons be injected into the corner region and cannot be erased completely. After times of cycle, the un-erased electrons cumulate more and more which may cause non-uniform charge distribution. Also, because of the poor initial quality of tunneling oxide, a lot of interface traps are generated after P/E cycles; thus, the two reasons will deteriorate the electrical characteristics. According to these observations, it is concluded that reducing the grain size to much smaller than the channel length can enhance the program/erasing speed and also improve the uniformity of device characteristics. Decreasing the channel thickness can also enhance the programming/erasing speed. However, it seems that the endurance would be degraded due to the corner effect. Further investigation on the corner effect is suggested.
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Teo, L. W., Van Tai Ho, M. S. Tay, Wee Kiong Choi, Wai Kin Chim, Dimitri A. Antoniadis, and Eugene A. Fitzgerald. "Dependence of nanocrystal formation and charge storage/retention performance of a tri-layer memory structure on germanium concentration and tunnel oxide thickness." 2003. http://hdl.handle.net/1721.1/3799.
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The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO₂ co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer.Singapore-MIT Alliance (SMA)
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Chen, Chi-Chih, and 陳吉智. "The characteristics of n-channel lateral diffused metal-oxide-semiconductor (LDMOS) field effect transistors with different gate oxide thickness." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/85234330301321003481.
Full textAbstract:
碩士國立成功大學
微電子工程研究所碩博士班
92
In this thesis, the characteristics of Lateral Diffused Metal-Oxide-Semi- conductor (LDMOS) field effect transistors based on 1.0μm technology with different gate oxide thickness are investigated. The characteristics of LDMOS transistors with different gate oxide thicknesses are examined. The temperature dependence of device parameters is studied under elevated operating temperature. Constant voltage stress is performed on devices with different gate oxide thickness to see the impact of gate oxide thickness on parameter degradation. Different degradation behavior was found that the maximum degradation of thick gate oxide device increases with gate stress voltage. While in thin gate oxide device, the maximum degradation remains at peak substrate current condition.
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Cheng, Chieh-Fang, and 鄭捷方. "Effect of Oxide Thickness on The Two-State haracteristics in MIS(p) Tunnel Diode with Ultra-thin Metal Surrounded Gate." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/upbe79.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
107
In this thesis, ultrathin metal surrounded gate Metal-Insulator-Semiconductor (UTMSG MIS) tunnel diodes with various oxide thicknesses were fabricated. The transient two-state characteristics of targeting devices can be magnified. In chapter 2, the electrical characteristics and transient two-state characteristics in the UTMSG MIS and the regular gate Metal-Insulator-Semiconductor (RG MIS) tunnel diodes with various oxide thickness were demonstrated that the UTMSG MIS devices can maintain larger two-state current window within appropriate oxide thicknesses range. The electrical properties of the UTMSG MIS devices are very sensitive to oxide thickness. Besides, the I-V hysteresis is closely related to the transient two-state characteristics because of RC delay at edge. In chapter 3, the optimal oxide thickness (29 Å) for transient characteristics in the UTMSG MIS devices was studied by comparing the RG MIS devices. Transient relaxation proves the existence of the RC delay. Also, the retention time of the UTMSG MIS device reaches a value of 190 ms, which fulfills the requirement of the DRAM applications. In chapter 4, by modulating ultrathin metal area and programming operation, transient responses have been enlarged during bias operation. Other relationship should be further investigated in more detail.
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Lin, Wen-yan, and 林文彥. "Study of Reliability in the Local Strained n-channel MOSFET by Different Thickness of Poly-Si Gate and Nitride Capping Layer." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/55965071158238051577.
Full textAbstract:
碩士國立雲林科技大學
電子與資訊工程研究所
93
In this study, a local strained n-channel MOSFET has been fabricated by utilizing a heavy mechanical stress SiNx-capping layer, and further improves the carrier mobility to achieve the purpose of high operation speed. We investigate the local strained effects on nMOSFETs by different Poly-Si and nitride thicknesses. Therefore, the study focuses on the relation of reliability and strain. After hot carrier stress, the devices with 250-nm SiNx show the largest ΔVth shift and transconductance degradation whereas 170-nm devices show better reliability. As we supply the different drain voltage or operation temperature, the reliability of devices will be change. SILC is an increase in gate oxide leakage current resulting from the application of a stress voltage or current. It is an important concern in scaling gate oxide thickness. As the device dimension continues to scale down, the local strain technology in future CMOS application will be more respected.
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Lee, Kun-Yu, and 李昆育. "The Study of Sub-Nanometer Equivalent Oxide Thickness of MBE and ALD Grown High κ Gate Dielectrics on Silicon and In0.53Ga0.47As Substrates." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/32141202705303068548.
Full textAbstract:
博士國立清華大學
材料科學工程學系
96
Metal oxide semiconductor (MOS) capacitors that incorporated high κ materials of HfO2 and Al2O3 are fabricated by Molecular beam epitaxy (MBE) and Atomic layer deposition (ALD) on Silicon and InGaAs substrates. The achievements in this work are to minimize the thickness of the interfacial layer at oxide/semiconductor and attain sub-nanometer equivalent oxide thickness (EOT) value in the MOS diodes. In Silicon phase, MBE grown high κ dielectrics of Al2O3 and HfO2 are employed as templates to suppress effectively the oxide/Si interfacial layer formation during the subsequent ALD Al2O3 and HfO2 growth. The nearly absence of the interfacial layer was confirmed using angle-resolved x-ray photoelectron spectroscopy (AR-XPS) and high resolution transmission electron microscopy (HR-TEM). The first two composite films consisting of ALD-Al2O3(1.9nm)/MBE-Al2O3(1.4nm) and ALD-Al2O3(3.0nm)/ MBE-HfO2(2.0nm) showed overall dielectric constant (κ) of 9.1, 11.5; EOT of 1.41, 1.7nm; interface trap density (Dit) of 2.2, 2×1011 cm-2eV-1; and a leakage current density of 2.4×10-2 A/cm2 at VFB-1V and 1.1×10-4 A/cm2 at VFB+1V, respectively. In addition, to further enhance the dielectric constant and reduce the EOT value of gate oxide, the ultra-thin composite film with structure of ALD-HfO2(1.4nm)/MBE-HfO2(1.5nm) has been employed and demonstrated a κ value of 16.2, an EOT of 0.7 nm with a leakage current density of 5.3×10-1 A/cm2 at VFB-1V and Dit value of 3.6×1011 cm-2eV-1 at mid-gap calculated by conductance method. The attainment of high dielectric constants in these composite oxides suggests that no low κ capacitor in series near the oxide/Si interface. In III-V phase, ALD grown high κ dielectric HfO2 films on air-exposed In0.53Ga0.47As/InP (100), using Hf(NCH3C2H5)4 (TEMAH) and H2O as the precursors,were found to have an atomically sharp interface free of arsenic oxides, an important aspect for Fermi level un-pinning. A careful and thorough probing, using high-resolution AR-XPS with synchrotron radiation, however, observed the existence of Ga2O3, In2O3, and In(OH)3 at the interface. The current transport of the metal-oxide-semiconductor capacitor for an oxide 7.8 nm thick follows the Fowler-Nordheim tunneling mechanism and shows a low leakage current density of ~10-8 A/cm2 at VFB+1V. Well behaved frequency-varying capacitance-voltage curves were measured and an interfacial density of states of 2×1012 cm-2eV-1 was derived. A conduction-band offset of 1.8±0.1 eV have been determined using the current transport data. A capacitive effective thickness value (CET) of 1.0 nm has been achieved in ALD high κ dielectrics HfO2 on In0.53Ga0.47As/InP. The key is a short air exposure under 10 min between removal of the freshly grown semiconductor epi-layers and loading to the ALD reactor. This has led to minimal formation of the interfacial layer thickness, as confirmed using HR-XPS and HR-TEM. The measured electrical characteristics of metal-oxide-semiconductor diodes of Au/Ti/HfO2(4.5nm)/In0.53Ga0.47As showed a low leakage current density of 3.8x10-4 A/cm2 at VFB+1V,which is about 8 order of magnitudes lower than that of SiO2 with a same CET. The capacitance-voltage curves show an overall κ value of 17-18, a nearly zero flat band shift, and an interfacial density of states Dit of 2×1012 cm-2eV-1 at mid-gap.
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Wang, Jia-Yi, and 王家儀. "A Study on Channel Thickness Effect of Double-Gate Polycrystalline-Silicon Thin-Film Transistors for Application of Monolithic Three-Dimensional Integrated Circuits." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/vbmjke.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
107
In this thesis, we successfully fabricated the double gate thin film transistors. In order to compare the device characteristic of single and double gate devices, we use different kinds of method to measure them. The double gate thin film transistors have better gate controllability than single gate devices. It can efficiently improve the on-state current, subthreshold swing, on/off ratio, and threshold voltage. And the different channel thickness devices of double gate have the relatively improved. The thinner channel thickness devices can have the off-state current and suppress the junction leakage; the thicker channel thickness devices have excellent on-state current since they not only have larger grain size and mobility, but also double the structure. In the study of short channel effect, the thinner channel thickness devices with double gate structure can effectively improve the Vth roll-off effect, and decrease the sensitivity to drain voltage in channel potential. Therefore, devices can continually be scaled down and achieve a better electrical characteristic. To sum up, 15-nm channel thickness devices have higher on-state current and subthreshold swing; While 10-nm channel thickness devices have lower off-state current and better on/off ratio. Moreover, by using double gate structure and thinning the channel thickness, we can get better device characteristic. Consequently, it is suitable for the development and application of AMLCD and Monolithic 3-D ICs.
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LIN, WEN-CHIN, and 林文欽. "The Device Performance and Reliability Study on N-type Multi-Fin FinFET Structure by Adopting Metal Gate Multi Work Function Thickness Engineering." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/wyhsn6.
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Chen, Ying-ya, and 陳映雅. "The Investigation of Characteristic for N-Type FinFETs with Different Thicknesses of TaN Metal Gate and Different Fin Numbers." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/72275242059061517411.
Full textAbstract:
碩士國立高雄大學
電機工程學系碩士班
103
With the scaling of device, FinFET has considered as one of the most promising options for future devices to replace planner MOSFETs. N-type tri-gate FinFETs were utilized in this work. The FinFET devices with various TaN thicknesses were used at first to study the influence on electric characteristics and reliability. It could be observed that the thick TaN device shows the larger threshold voltage, drain saturation current and better subthreshold swing for the flash device. After hot carrier injection, it could be found that the thicker TaN device shows larger subthreshold swing increasing and mobility degradation but the smaller VTH variation. It meant that the interface defect dominates the degeneration. The degeneration of the thinner TaN device is due to the oxide traps. The devices with various fin numbers were also studied in this work. We found that the 40-fin device shows the better characteristic for the flash device. After hot carrier injection, the 40-fin device shows the smaller variations on VTH, subthreshold swing and drain current degradation than the 1-fin device. It indicates that the degradation was induced less by interface defect charges.