Journal articles: 'Thermal transistor'

1

Timoshenkov, V. P., A. I. Khlybov, D. V. Rodionov, and A. I. Panteleev. "Research of Influence of Power RF GaN Transistor Constructions on it's Thermal Mode." Nano- i Mikrosistemnaya Tehnika 22, no. 8 (October 23, 2020): 415–21. http://dx.doi.org/10.17587/nmst.22.415-421.

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This paper shows influence of power RF GaN transistors construction on it's thermal mode. Field GaN transistor (with field plate) was researched. The influence of field-plate on transistor thermal mode was analysed and compared to other constructions.

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Amar, Abdelhamid, Bouchaïb Radi, and Hami El Abdelkhalak. "Electrothermal Reliability of the High Electron Mobility Transistor (HEMT)." Applied Sciences 11, no. 22 (November 13, 2021): 10720. http://dx.doi.org/10.3390/app112210720.

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The main objective of our paper is to propose an approach to studying the mechatronic system’s reliability through the reliability of their high electron mobility transistors (HEMT). The operating temperature is one of the parameters that influences the characteristics of the transistor, especially the electron mobility that represents an advantage over other transistor’s families. Several factors can influence this temperature. Thanks to thermal modeling, it is possible to determine the factors representing a great impact on the operating temperature, such as the power dissipation at the active area of the transistor and the reference temperature above the substrate. In our reliability study, these analytical methods, such as First and Second Order Reliability Methods (FORM and SORM, respectively), were used to analyze the HEMT reliability. Thanks to the coupling between two models—the reliability model coded on Matlab and the thermal modeling with Comsol multiphysics software—the reliability index and the failure probability of the studied system were evaluated.

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Oh, Se Young, Sun Kak Hwang, Young Do Kim, Jong Wook Park, and In Nam Kang. "Effects of Post Thermal Annealing on the Electrical Properties of Vertical Type Organic Thin Film Transistors Using Poly(3-hexylthiophene) and Its Application in Organic Light Emitting Transistor." Journal of Nanoscience and Nanotechnology 8, no. 9 (September 1, 2008): 4881–84. http://dx.doi.org/10.1166/jnn.2008.ic66.

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We have fabricated the vertical type organic thin film transistor (OTFT) using electrically conductive poly(3-hexylthiophene) (P3HT) as a p-type organic material. Effects of post thermal annealing and thickness of active layer on the performance of vertical type transistors were investigated. Especially, the correlation between carrier mobility of P3HT after post thermal annealing and static characteristics of the transistor was studied. Carrier mobility was calculated by space charge limited current (SCLC) model from the I–V curves of the prepared device. The vertical type OTFT after post thermal annealing at 120 °C (Tg) showed high current of 0.383 mA and on–off ratio of 22.5 at a low gate voltage of +2.0 V. Additionally, we report on emission characteristics from the vertical type transistor using P3HT.

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4

Roberts, J., T. MacElwee, and L. Yushyna. "The Thermal Integrity of Integrated GaN Power Modules." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000061–68. http://dx.doi.org/10.4071/hiten-mp12.

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In this paper the authors describe GaN (gallium nitride) power switching transistors that use copper post and substrate via interconnect techniques. These transistors can be matrixed to allow a parallel array of the devices to provide very low on-resistance and high operating voltages. At 150 °C the basic building block which is a 2 × 2 mm die, provides 1200 V / 14 A. A 2×2 matrix array of these transistors provides for example, 1200 V / 56 A operation. The overall GaN device size is 4 × 4 mm. This high current density is achieved by using a unique castellated island topology. This provides short fingers that are not required to carry high current. No high current tracks are provided on-chip because on-chip metal is typically less than 3 microns thick. The die has 12 copper posts on the source islands that carry the current to the CMOS driver device. The CMOS driver is used in a cascode configuration which allows the normally-on GaN transistor to be operated with convenient normally-off functionality. The two devices are combined in a modular assembly. The paper provides a thermal analysis of the assembly. The objective of the design is to keep the ‘junction’ temperature of the GaN transistor below 150 °C.

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Пашковский, А. Б., И. В. Куликова, В. Г. Лапин, В. М. Лукашин, Н. К. Приступчик, Л. В. Манченко, В. Г. Калина, М. И. Лопин, and А. Д. Закурдаев. "Поверхностный тепловой интерфейс для мощных арсенид-галлиевых гетероструктурных полевых транзисторов." Журнал технической физики 89, no. 2 (2019): 252. http://dx.doi.org/10.21883/jtf.2019.02.47079.2493.

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AbstractApplication of heat-conducting coatings for cooling of high-power FETs based on heterostructures with arsenide–gallium substrate is theoretically analyzed. When the basic technology for manufacturing of transistors is employed in the absence of additional efforts aimed at a decrease in the thermal resistance of the substrate, the application of an additional thermal interface that represents a heat-conducting dielectric coating makes it possible to substantially decrease the overheating of the transistor channel. A several-fold decrease in such overheating can be reached using variations in the thickness of the coating and modification of the transistor structure and working regimes.

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Njawah Achiri, Humphrey Mokom, Vaclav Smidl, Zdenek Peroutka, and Lubos Streit. "Least Squares Method for Identification of IGBT Thermal Impedance Networks Using Direct Temperature Measurements." Energies 13, no. 14 (July 21, 2020): 3749. http://dx.doi.org/10.3390/en13143749.

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State-of-the-art methods for determining thermal impedance networks for IGBT (Insulated Gate Bipolar Transistor) modules usually involves the establishment of the relationship between the measured transistor or diode voltage and temperature under homogenous temperature distribution across the IGBT module. The junction temperature is recomputed from the established voltage–temperature relationship and used in determining the thermal impedance network. This method requires accurate measurement of voltage drop across the transistors and diodes under specific designed heating and cooling profiles. Validation of the junction temperature is usually done using infrared camera or sensors placed close to the transistors or diodes (in some cases and open IGBT module) so that the measured temperature is as close to the junction as possible. In this paper, we propose an alternative method for determining the IGBT thermal impedance network using the principles of least squares. This method uses measured temperatures for defined heating and cooling cycles under different cooling conditions to determine the thermal impedance network. The results from the proposed method are compared with those obtained using state-of-the-art methods.

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Ron Liu, D., K. Chen, and E. Jih. "Observation of Microstructural Evolution of Aluminum Bonding Wires in Power Electronic Package." Microscopy and Microanalysis 5, S2 (August 1999): 876–77. http://dx.doi.org/10.1017/s1431927600017700.

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Power electronic circuits are used in electric vehicle or hybrid electric vehicle to drive the main electric motor. All the transistors and diodes in a sealed power electronic package will experience repeated high current cycling during their service life. The aluminum bonding wires which connect these devices to the rest of the circuit will experience repeated thermal strain cycling. When design a power electronic package, the thermal fatigue durability of these bonding wires would be a concern. A power electronic module with pure aluminum bonding wires of 0.5mm in diameter from a vendor was power cycled with the following schedule. Each transistor in the circuit was on for 10 seconds with the current at 400 Amperes followed by the transistor being off for 30 seconds. The wires from the diodes to the copper trace lines are about twice as long as those from the transistors to the copper trace lines.

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8

Vachhani, M. G., and P. N. Gajjar. "Influence of Chain Length of 1D Thermal Transistor on Thermal Amplification Factor." Advanced Materials Research 1141 (August 2016): 72–76. http://dx.doi.org/10.4028/www.scientific.net/amr.1141.72.

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We study the influence of chain length of our 1D model of thermal transistor on thermal amplification factor. Here, we varied the length of drain and source segments for different simulation experiment and found that the maximum value of thermal amplification factor influenced with chain length. The thermal amplification factor of the thermal transistor is found to be dependent on gate temperature. We also calculated the switching efficiency and working region of the thermal transistor and better results are obtained in comparison to previous study.

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9

Hamana, Yoshiki, and Takahide Oya. "Improvement of Performance of Paper Transistor Using Carbon-Nanotube-Composite Paper and its Application to Logic Circuit." Advances in Science and Technology 95 (October 2014): 32–37. http://dx.doi.org/10.4028/www.scientific.net/ast.95.32.

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We propose development of an advanced type of "paper transistor" by using carbon-nanotube (CNT) composite papers (CNTCPs) and aim to apply our paper transistors to the construction of logic circuits. It is known that CNTs have many functions such as high electrical and thermal conductivities and metallic and semiconducting properties. Our CNTCP, which has various functions held by CNTs despite being paper, can be fabricated easily by scooping up and drying materials from a mixture of CNT and pulp (paper materials) dispersions. The CNTs have metallic or semiconducting properties, so metallic and semiconducting CNTCPs can be fabricated. By preparing such CNTCPs and normal paper as an insulator, we can produce the paper transistor. In previous work, we confirmed our prototype paper transistor could operate as a p-type transistor. However, the sample had problems, e.g., the internal resistance was rather high. In this study, we aim to overcome the problems by using a novel method for making the CNTCP. As the result of experiments, we succeeded in obtaining new paper transistors with better performance in comparison with the previous one. Moreover, we succeeded in finding a potential use as an n-type paper transistor by using an n-type doping material for semiconducting CNTCPs.

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10

Bunea, Gabriela E., S. T. Dunham, and T. D. Moustakas. "Modeling of a GaN Based Static Induction Transistor." MRS Internet Journal of Nitride Semiconductor Research 4, S1 (1999): 697–702. http://dx.doi.org/10.1557/s1092578300003276.

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Static induction transistors (SITs) are short channel FET structures which are suitable for high power, high frequency and high temperature applications. GaN has particularly favorable properties for SIT operation. However, such a device has not yet been fabricated. In this paper we report simulation studies on GaN static induction transistors over a range of device structures and operating conditions. The transistor was modeled with coupled drift-diffusion and heat-flow equations. We found that the performance of the device depends sensitively on the thermal boundary conditions, as self-heating effects limit the maximum voltage swing.

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11

Shafranjuk, S. E. "Graphene thermal flux transistor." Nanoscale 8, no. 46 (2016): 19314–25. http://dx.doi.org/10.1039/c6nr07246a.

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12

Chen, Liang. "The Effect of Thermal Resistans on I_C-V_BE Fly-Back Characteristic of Power SiGe Heterojunction Bipolar Transistor." Applied Mechanics and Materials 701-702 (December 2014): 1177–80. http://dx.doi.org/10.4028/www.scientific.net/amm.701-702.1177.

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The effect of thermal resistans onIC-VBEfly-back characteristic of power SiGe heterojunction bipolar transistor is studied through theoretical analysis, computer simulations, and experimental measurements. It is found that a suitable thermal resistans can make the collector current achieve the second fly-back point before transistors are burned-out, and then returns to a stable situation. Such a thermal resistans is beneficial to the thermal stability. When the thermal resistans is small, the curve ofIC-VBEfly-back characteristic of HBT has no fly-back point. While the thermal resistans increases, the curve ofIC-VBEfly-back characteristic of HBT has two fly-back points.

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13

WANG, LEI, and BAOWEN LI. "HEAT SWITCH AND MODULATOR: A MODEL OF THERMAL TRANSISTOR." International Journal of Modern Physics B 21, no. 23n24 (September 30, 2007): 4017–20. http://dx.doi.org/10.1142/s0217979207045128.

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A model of a thermal transistor to control heat flow is reported. Like its electronic counterpart, the thermal transistor is a three-terminal device with the important feature that the heat current through two terminals can be switched or modulated by the temperature of the third terminal. The thermal transistor model is possible because of the negative differential thermal resistance.

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14

Zhu, Miao, Xiaoyun Wei, Jupeng Cao, Wei Xie, Changwei Zou, Yanxiong Xiang, and Hong Meng. "High-k Boron Nitride Sheets/Polyimide Hybrid Dielectric Layers for the Fabrication of Flexible Organic Transistors on Commercial Graphite Paper." Nano 15, no. 11 (October 29, 2020): 2050145. http://dx.doi.org/10.1142/s1793292020501453.

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Organic transistors are crucial components in future flexible electronics due to their excellent properties and ease of circuit integration. Previously, we demonstrated that flexible organic (polyimide) thermal transistors could be prepared using commercial graphite paper as the substrate. These materials exhibited excellent temperature sensitivity, linearity and recoverability due to the intrinsically high thermal conductivity of graphite. In this study, boron nitride (BN) sheets/polyimide hybrid dielectric layers were synthesized for the fabrication of flexible organic transistors using a commercial graphite paper. Under test, the results showed that the introduction of BN sheets was beneficial in improving the mobility and transistor characteristics of the device, as well as enhancing the overall stability. The as-fabricated transistors virtually exhibited no hysteresis at all BN contents.

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15

Bhardwaj, Bishwajeet, Takeshi Sugiyama, Naoko Namba, Takayuki Umakoshi, Takafumi Uemura, Tsuyoshi Sekitani, and Prabhat Verma. "Raman Spectroscopic Studies of Dinaphthothienothiophene (DNTT)." Materials 12, no. 4 (February 18, 2019): 615. http://dx.doi.org/10.3390/ma12040615.

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The application of dinaphthothienothiophene (DNTT) molecules, a novel organic semiconductor material, has recently increased due to its high charge carrier mobility and thermal stability. Since the structural properties of DNTT molecules, such as the molecular density distribution and molecular orientations, significantly affect their charge carrier mobility in organic field-effect transistors devices, investigating these properties would be important. Here, we report Raman spectroscopic studies on DNTT in a transistor device, which was further analyzed by the density functional theory. We also show a perspective of this technique for orientation analysis of DNTT molecules within a transistor device.

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16

Li, Baowen, Lei Wang, and Giulio Casati. "Negative differential thermal resistance and thermal transistor." Applied Physics Letters 88, no. 14 (April 3, 2006): 143501. http://dx.doi.org/10.1063/1.2191730.

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17

Pop, Eric, and Kenneth E. Goodson. "Thermal Phenomena in Nanoscale Transistors." Journal of Electronic Packaging 128, no. 2 (June 1, 2006): 102–8. http://dx.doi.org/10.1115/1.2188950.

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As CMOS transistor gate lengths are scaled below 45nm, thermal device design is becoming an important part of microprocessor engineering. Decreasing dimensions lead to nanometer-scale hot spots in the drain region of the device, which may increase the drain series and source injection electrical resistances. Such trends are accelerated with the introduction of novel materials and nontraditional transistor geometries, like ultrathin body, surround-gate, or nanowire devices, which impede heat conduction. Thermal analysis is complicated by subcontinuum phenomenan including ballistic electron transport, which reshapes the hot spot region compared with classical diffusion theory predictions. Ballistic phonon transport from the hot spot and between material boundaries impedes conduction cooling. The increased surface to volume ratio of novel transistor designs also leads to a larger contribution from material boundary thermal resistance. In this paper we survey trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems.

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18

Khlybov, A. I., D. V. Rodionov, A. I. Panteleev, P. V. Timoshenkov, and N. V. Guminov. "Simulation of Power RF GaN Transistors Thermal Parameters in Pulse Mode." Nano- i Mikrosistemnaya Tehnika 23, no. 4 (August 20, 2021): 179–85. http://dx.doi.org/10.17587/nmst.23.179-185.

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This paper contains research results of thermal process in power GaN RF transistor in silicon substrate for pulse mode. Thermal mode research was done using computer simulation. Authors developed methodic allows significant decrease computational complexity. The dependences of maximum transistor channel temperature and thermal resistance as function of pulse width (with constant duty cycle) were done. Thermal simulation was done for power GaN RF transistor with overall gate width 2.1 mm.

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Maguire, Luke, Masud Behnia, and Graham Morrison. "Heat Spreading Enhancement in High Power Amplifier Heat Sinks – Comparison of Measurements with Numerical Predictions." Journal of Microelectronics and Electronic Packaging 1, no. 3 (July 1, 2004): 117–26. http://dx.doi.org/10.4071/1551-4897-1.3.117.

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A comprehensive study has been undertaken to better understand the thermal conditions within high power, radio frequency (r.f.) signal amplifiers. The majority of the heat generated is dissipated from four high power transistors, mounted directly to a large extruded aluminum heat sink measuring 300mm long × 220mm wide × 72mm high. The transistors each dissipate up to 130W across a footprint of only 1.96cm2 and as such, act as high flux, point heat sources across the heat sink base. At maximum power levels the transistor junction temperatures have been shown to approach the manufacturers rated limit of 200°C [1] when ambient temperatures reach 60°C. The prohibitively high cost of replacing the electronic circuits and cooling air delivery system across the entire transmitter network means that design changes to the heat sink that will reduce device temperatures and can be implemented on a retrofit basis are extremely attractive. Numerical and experimental methods have been used to assess the incorporation of high thermal conductivity materials into the heat sink design to improve cooling performance. Numerical simulation of a copper heat spreader embedded into the base of the existing aluminum heat sink predicted a reduction of transistor junction temperatures of up to 11°C. However, in experiments, a maximum temperature drop of only 5°C was achieved due to the introduction of an additional thermal resistance at the copper/aluminum interface.

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Liu, Yu-Qiang, Deng-Hui Yu, and Chang-Shui Yu. "Common Environmental Effects on Quantum Thermal Transistor." Entropy 24, no. 1 (December 24, 2021): 32. http://dx.doi.org/10.3390/e24010032.

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Quantum thermal transistor is a microscopic thermodynamical device that can modulate and amplify heat current through two terminals by the weak heat current at the third terminal. Here we study the common environmental effects on a quantum thermal transistor made up of three strong-coupling qubits. It is shown that the functions of the thermal transistor can be maintained and the amplification rate can be modestly enhanced by the skillfully designed common environments. In particular, the presence of a dark state in the case of the completely correlated transitions can provide an additional external channel to control the heat currents without any disturbance of the amplification rate. These results show that common environmental effects can offer new insights into improving the performance of quantum thermal devices.

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21

Hikita, Masahiro, Hiroaki Ueno, Hisayoshi Matsuo, Tetsuzo Ueda, Yasuhiro Uemoto, Kaoru Inoue, Tsuyoshi Tanaka, and Daisuke Ueda. "Status of GaN-Based Power Switching Devices." Materials Science Forum 600-603 (September 2008): 1257–62. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1257.

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State-of-the-art technologies of GaN-based power switching transistors are reviewed, in which normally-off operation and heat spreading as technical issues. We demonstrate a new operation principle of GaN-based normally-off transistor called Gate Injection Transistor (GIT). The GIT utilizes hole-injection from p-AlGaN to AlGaN/GaN hetero-junction which increases electron density in the depleted channel resulting in dramatic increase of the drain current owing to conductivity modulation. The fabricated GIT on Si substrate exhibits the threshold voltage of +1.0V with high maximum drain current of 200mA/mm. The obtained on-state resistance (Ron·A) and off-state breakdown voltage (BVds) are 2.6mΩ·cm2 and 800V, respectively. These values are the best ones ever reported for GaN-based normally-off transistors. In addition, we propose the use of poly-AlN as surface passivation. The AlN has at least 200 times higher thermal conductivity than conventional SiN so that it can effectively reduce the channel temperature.

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Mao, Yu Dong, and Ming Tian Xu. "Thermal Transport in Hotspots Using the Lattice Boltzmann Method with Application to Silicon-on-Insulator Transistors." Advanced Materials Research 960-961 (June 2014): 337–40. http://dx.doi.org/10.4028/www.scientific.net/amr.960-961.337.

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Silicon-on-insulator (SOI) transistors have been widely used in the micro-electronic devices. The Lattice Boltzmann method (LBM) is employed to simulate the heat conductions of hotspots appeared in a SOI transistor. The results show that a thermal wave effect is appeared in micro-region, and it can not be found in Fourier prediction. Comparing the results obtained by the Fourier law and LBM, we find that the LBM solution shows approximately 22% higher energy density than the Fourier prediction. When two thermal waves form different hotspots meet together, a significant energy enhancement will be appeared.

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23

Vachhani, M. G., Tarika K. Patel, and P. N. Gajjar. "Thermal characteristics of a microscopic model of thermal transistor." International Journal of Thermal Sciences 108 (October 2016): 159–64. http://dx.doi.org/10.1016/j.ijthermalsci.2016.05.008.

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24

Zainal Badri, Asmaa Nur Aqilah, Norlaili Mohd Noh, Shukri Bin Korakkottil Kunhi Mohd, Asrulnizam Abd Manaf, Arjuna Marzuki, Mohd Tafir Mustaffa, and Mohamed Fauzi Packeer Mohamed. "Development of Accurate BSIM4 Noise Parameters for CMOS 0.13-µm Transistors in Below 3-GHz LNA Application." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 3 (June 1, 2018): 925. http://dx.doi.org/10.11591/ijeecs.v10.i3.pp925-933.

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Accurate transistor thermal noise model is crucial in IC design as it allows accurate selection of transistors for specific frequency application. The accuracy of the model is represented by the similarity between the simulated and the measured noise parameters (NPs). This work was based on a problem faced by a foundry concerning the dissimilarities between the measured and simulated NPs, especially minimum noise figure (NF<sub>min</sub>) for frequencies below 3 GHz.

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Wu, Jerry, Yin-Lin Shen, Kitt Reinhardt, Harold Szu, and Boqun Dong. "A Nanotechnology Enhancement to Moore's Law." Applied Computational Intelligence and Soft Computing 2013 (2013): 1–13. http://dx.doi.org/10.1155/2013/426962.

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Intel Moore observed an exponential doubling in the number of transistors in every 18 months through the size reduction of transistor components since 1965. In viewing of mobile computing with insatiate appetite, we explored the necessary enhancement by an increasingly maturing nanotechnology and facing the inevitable quantum-mechanical atomic and nuclei limits. Since we cannot break down the atomic size barrier, the fact implies a fundamental size limit at the atomic/nucleus scale. This means, no more simple 18-month doubling, but other forms of transistor doubling may happen at a different slope. We are particularly interested in the nano enhancement area. (i) 3 Dimensions: If the progress in shrinking the in-plane dimensions is to slow down, vertical integration can help increasing the areal device transistor density. As the devices continue to shrink into the 20 to 30 nm range, the consideration of thermal properties and transport in such devices becomes increasingly important. (ii) Quantum computing: The other types of transistor material are rapidly developed in laboratories worldwide, for example, Spintronics, Nanostorage, HP display Nanotechnology, which are modifying this Law. We shall consider the limitation of phonon engineering fundamental information unit “Qubyte” in quantum computing, Nano/Micro Electrical Mechanical System (NEMS), Carbon Nanotubes, single-layer Graphenes, single-strip Nano-Ribbons, and so forth.

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SAMIAN, R. S., A. ABBASSI, and J. GHAZANFARIAN. "THERMAL INVESTIGATION OF COMMON 2D FETs AND NEW GENERATION OF 3D FETs USING BOLTZMANN TRANSPORT EQUATION IN NANOSCALE." International Journal of Modern Physics C 24, no. 09 (August 18, 2013): 1350064. http://dx.doi.org/10.1142/s0129183113500642.

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The thermal performance of two-dimensional (2D) field-effect transistors (FET) is investigated frequently by solving the Fourier heat diffusion law and the Boltzmann transport equation (BTE). With the introduction of the new generation of 3D FETs in which their thickness is less than the phonon mean-free-path it is necessary to carefully simulate the thermal performance of such devices. This paper numerically integrates the BTE in common 2D transistors including planar single layer and Silicon-On-Insulator (SOI) transistor, and the new generation of 3D transistors including FinFET and Tri-Gate devices. In order to decrease the directional dependency of results in 3D simulations; the Legendre equal-weight (PN-EW) quadrature set has been employed. It is found that if similar switching time is assumed for 3D and 2D FETs while the new generation of 3D FETs has less net energy consumption, they have higher hot-spot temperature. The results show continuous heat flux distribution normal to the silicon/oxide interface while the temperature jump is seen at the interface in double layer transistors.

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Alhmoud, Lina, and Ali Khudhair Al-Jiboory. "Insulated-gate bipolar transistor junction temperature estimation based on ℋ∞ robust controller in wind energy applications." Wind Engineering 44, no. 5 (September 27, 2019): 548–58. http://dx.doi.org/10.1177/0309524x19877645.

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This article presents lifetime estimation using robust control based on thermal path degradation condition of insulated-gate bipolar transistor wind power modules. Online measurements of the on-state voltage [Formula: see text] are considered to be a promising method for obtaining a thermal-sensitive electrical parameter for wire-bond lift-off. This parameter demonstrates a good correlation with junction temperature. Due to the harsh environment, disturbances and uncertain parameters are founded within the compact set of wind energy generation systems. The uncertainty sacrifices some degree of accuracy of junction temperature measurements. Hence, robust control theory has been utilized to synthesize [Formula: see text] controller for the thermal impedance of high-power insulated-gate bipolar transistors. To study this reliability problem, an integrated model of wind energy generation system is built in MATLAB/Simulink for the closed-loop system. Simulation results show the benefit of the designed controller compared to the open-loop system in terms of thermal cycles of junction temperature and lifetime estimation.

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Gryglewski, Daniel, Wojciech Wojtasiak, Eliana Kamińska, and Anna Piotrowska. "Characterization of Self-Heating Process in GaN-Based HEMTs." Electronics 9, no. 8 (August 13, 2020): 1305. http://dx.doi.org/10.3390/electronics9081305.

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Thermal characterization of modern microwave power transistors such as high electron-mobility transistors based on gallium nitride (GaN-based HEMTs) is a critical challenge for the development of high-performance new generation wireless communication systems (LTE-A, 5G) and advanced radars (active electronically scanned array (AESA)). This is especially true for systems operating with variable-envelope signals where accurate determination of self-heating effects resulting from strong- and fast-changing power dissipated inside transistor is crucial. In this work, we have developed an advanced measurement system based on DeltaVGS method with implemented software enabling accurate determination of device channel temperature and thermal resistance. The methodology accounts for MIL-STD-750-3 standard but takes into account appropriate specific bias and timing conditions. Three types of GaN-based HEMTs were taken into consideration, namely commercially available GaN-on-SiC (CGH27015F and TGF2023-2-01) and GaN-on-Si (NPT2022) devices, as well as model GaN-on-GaN HEMT (T8). Their characteristics of thermal impedance, thermal time constants and thermal equivalent circuits were presented. Knowledge of thermal equivalent circuits and electro–thermal models can lead to improved design of GaN HEMT high-power amplifiers with account of instantaneous temperature variations for systems using variable-envelope signals. It can also expand their range of application.

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Joulain, Karl, Younès Ezzahri, and Jose Ordonez-Miranda. "Quantum Thermal Rectification to Design Thermal Diodes and Transistors." Zeitschrift für Naturforschung A 72, no. 2 (February 1, 2017): 163–70. http://dx.doi.org/10.1515/zna-2016-0350.

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AbstractWe study in this article how heat can be exchanged between two-level systems, each of them being coupled to a thermal reservoir. Calculations are performed solving a master equation for the density matrix using the Born–Markov approximation. We analyse the conditions for which a thermal diode and a thermal transistor can be obtained as well as their optimisation.

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d’Alessandro, Vincenzo, Antonio Pio Catalano, Ciro Scognamillo, Markus Müller, Michael Schröter, Peter J. Zampardi, and Lorenzo Codecasa. "Experimental Determination, Modeling, and Simulation of Nonlinear Thermal Effects in Bipolar Transistors under Static Conditions: A Critical Review and Update." Energies 15, no. 15 (July 28, 2022): 5457. http://dx.doi.org/10.3390/en15155457.

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This paper presents a comprehensive overview of nonlinear thermal effects in bipolar transistors under static conditions. The influence of these effects on the thermal resistance is theoretically explained and analytically modeled using the single-semiconductor assumption. A detailed review of experimental techniques to extract the thermal resistance as a function of backside temperature and/or dissipated power from DC measurements is provided; advantages, underlying approximations, and limitations of all methods are clarified, and guidelines for their correct application are given. Accurate FEM thermal simulations of an InGaP/GaAs and a Si/SiGe HBT are performed to verify the accuracy of the single-semiconductor theory. The thermal resistance formulations employed in the most popular compact bipolar transistor models for circuit simulators are investigated, and it is found that they do not properly describe nonlinear thermal effects. Alternative implementations of the more accurate single-semiconductor theory are then proposed for the future versions of the compact models.

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Shaheen, Saleh, Gady Golan, Moshe Azoulay, and Joseph Bernstein. "A comparative study of reliability for finfet." Facta universitatis - series: Electronics and Energetics 31, no. 3 (2018): 343–66. http://dx.doi.org/10.2298/fuee1803343s.

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The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integrated Circuit (IC) density and performance. The emergence of FinFET technology has brought with it the same reliability issues as standard CMOS with the addition of a new prominent degradation mechanism. The same mechanisms still exist as for previous CMOS devices, including Bias Temperature Instability (BTI), Hot Carrier Degradation (HCD), Electro-migration (EM), and Body Effects. A new and equally important reliability issue for FinFET is the Self -heating, which is a crucial complication since thermal time-constant is generally much longer than the transistor switching times. FinFET technology is the newest technological paradigm that has emerged in the past decade, as downscaling reached beyond 20 nm, which happens also to be the estimated mean free path of electrons at room temperature in silicon. As such, the reliability physics of FinFET was modified in order to fit the newly developed transistor technology. This paper highlights the roles and impacts of these various effects and aging mechanisms on FinFET transistors compared to planar transistors on the basic approach of the physics of failure mechanisms to fit to a comprehensive aging model.

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Firek, Piotr, and Bartłomiej Stonio. "Influence of AlN etching process on MISFET structures." Microelectronics International 36, no. 3 (July 1, 2019): 109–13. http://dx.doi.org/10.1108/mi-12-2018-0081.

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Purpose The purpose of this paper is to present the influence of gate dielectric etching on obtained MISFET (metal insulator semiconductor field effect transistor) structures. Because of its properties, aluminum nitride (AlN) layers can be successfully used in a large area of applications. In addition, AIN has a wide bandgap (6.2eV) and high thermal conductivity (3.2 W/cm * K). Its melting temperature is greater than 2,000°C. The relative permittivity is about 9. All these features (especially high power, high temperature and high-frequency) make AlN a useful material in the fields of electronic, optical and acoustic applications. Design/methodology/approach To fabricate n-channel transistors, silicon technology was used. The 50-nm thick AlN films were deposited using the magnetron sputtering. After preparation of SiO2/AlN stack as the gate dielectric, the optimization processes of dry etching in plasma environment by Taguchi method were realized. In the next step, three methods of AlN etching were selected and used to MISFET device fabrication. Atomic force microscopy and scanning electron microscopy allowed to surfacing of the state observation after etching process. The current–voltage (I–V) output and transfer characteristics of structures with modified etch technology were measured. Keithley SMU 236/237/238 measurement set was used. Findings In this research work, a method of AlN etching in a field effect transistor technology was developed and improved. Current−voltage characteristics of obtained MISFET structures were measured and compared. Influence of etching procedure on transistors properties was examined. Originality/value The obtained results allow improving the MISFET technology based on AlN film as a gate dielectric. The complete research work will allow using the developed technologies to implement in highly sensitive ion-sensitive field effect transistor (ISFET) structures in the future. The improvement of the etching element in the technology strongly influences the detection capabilities and operating range of the transistor.

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Ukita, Yasunari, Kazuki Tateyama, Masao Segawa, Yoshihiko Tojo, Hideyuki Gotoh, and Katsuhisa Oosako. "Lead Free Die Mount Adhesive Using Silver Nanoparticles Applied To Power Discrete Package." Journal of Microelectronics and Electronic Packaging 2, no. 3 (July 1, 2005): 217–22. http://dx.doi.org/10.4071/1551-4897-2.3.217.

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Lead-free materials are required to replace conventional lead-containing solder for environmental protection. The Pb-rich solder die mount material in a high-power transistor package is required to be replaced by a silver adhesive paste. The silver paste has disadvantages such as low thermal conductivity and high electrical resistivity, since conduction paths are achieved only by mechanical contacts between silver particles. Recently, a new conductive paste containing silver particles and silver nanoparticles with a particle size of 3–7 nm in diameter was developed. The paste shows very low electrical resistivity of 6×10−6 ohm.cm, since the silver nanoparticles can be fused at temperatures below 200°C. We have been studying the possibility of the paste as a die mount material for high-power transistor packages. It was confirmed that the paste had a very high thermal conductivity of 51 W/mK. We fabricated a high-power transistor package using this paste. As a result, the package showed lower thermal resistance than that fabricated using silver paste or lead-containing solder. Moreover, the package is sufficiently reliable that it passed the thermal cycle and pressure cooker tests. This paste can be applied to a high-power transistor package in place of lead-containing solder.

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34

Górecki, Krzysztof. "Influence of the Semiconductor Devices Cooling Conditions on Characteristics of Selected DC–DC Converters." Energies 14, no. 6 (March 17, 2021): 1672. http://dx.doi.org/10.3390/en14061672.

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The problem of an influence of cooling conditions of power semiconductor devices on properties of selected DC–DC converters is considered. The new version of electrothermal average model of a diode-transistor switch for SPICE (Simulation Program with Integrated Circuit Emphasis) is used in the investigations. This model makes it possible to take into account thermal inertia of semiconductor devices as well as mutual thermal interactions between these devices. The investigations are performed for boost and buck converters containing the power MOS (Metal-Oxide-Semiconductor) transistor and the diode. Computational results obtained using the proposed model are shown and discussed. Particularly, an influence of thermal phenomena in the diode and the power MOS transistor on the converters output voltage and internal temperature of the semiconductor devices is considered. The correctness of the selected results of computations was verified experimentally.

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35

Kanoh, Hiroshi, and Masakiyo Matsumura. "Thermal-CVD Amorphous-Silicon Thin-Film Transistor." IEEJ Transactions on Fundamentals and Materials 110, no. 10 (1990): 667–69. http://dx.doi.org/10.1541/ieejfms1990.110.10_667.

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36

Kim, Sangrak. "Thermal transistor behavior of a harmonic chain." Journal of the Korean Physical Society 71, no. 5 (September 2017): 269–74. http://dx.doi.org/10.3938/jkps.71.269.

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37

Prod'homme, Hugo, Jose Ordonez-Miranda, Younes Ezzahri, Jeremie Drevillon, and Karl Joulain. "Optimized thermal amplification in a radiative transistor." Journal of Applied Physics 119, no. 19 (May 21, 2016): 194502. http://dx.doi.org/10.1063/1.4950791.

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38

Chung Lo, Wei, Lei Wang, and Baowen Li. "Thermal Transistor: Heat Flux Switching and Modulating." Journal of the Physical Society of Japan 77, no. 5 (May 15, 2008): 054402. http://dx.doi.org/10.1143/jpsj.77.054402.

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39

Behnia, S., and R. Panahinia. "Molecular thermal transistor: Dimension analysis and mechanism." Chemical Physics 505 (April 2018): 40–46. http://dx.doi.org/10.1016/j.chemphys.2018.02.018.

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40

Kazalieva, E., and A. R. Shakhmaeva. "Improving the thermal properties of the device in the process of forming a contact with the collector region of a silicon transistor." Herald of Dagestan State Technical University. Technical Sciences 49, no. 3 (November 7, 2022): 6–13. http://dx.doi.org/10.21822/2073-6185-2022-49-3-6-13.

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Objective. The objective of the study is to increase the reliability of the contact of the semiconductor transistor crystal to the body and the reproducibility of the technological process.Method. A method for obtaining multilayer metallization of the reverse side of the crystal has been developed and the most optimal technological modes of its formation have been selected. The parameters of the reliability of the connection of the crystal to the body of the transistor were checked.Results. Layer-by-layer metallization has been obtained, which provides a strong contact to the collector region of the transistor and a reliable fit of the crystal to the base of the case.The control of technological operations showed 100% distribution of solder over the surface of the crystal, the absence of pores in the solder, the improvement in the output characteristics of the device and the increase in the percentage of output usable transistors.Conclusion. An analysis of the experimental results showed that in order to create a reliable contact and remove heat from the collector junction of power semiconductor transistors on the reverse side of the plates, it is necessary to form a metallization in one technological cycle, consisting of four layers of metals (Cr-Ni-Sn-Ag). The technical result of the research is to improve the quality of fit by obtaining a uniform distribution of the layer of Cr-Ni-Sn-Ag metals in a single technological cycle.

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41

Mandarino, Antonio. "Quantum Thermal Amplifiers with Engineered Dissipation." Entropy 24, no. 8 (July 26, 2022): 1031. http://dx.doi.org/10.3390/e24081031.

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A three-terminal device, able to control the heat currents flowing through it, is known as a quantum thermal transistor whenever it amplifies two output currents as a response to the external source acting on its third terminal. Several efforts have been proposed in the direction of addressing different engineering options of the configuration of the system. Here, we adhere to the scheme in which such a device is implemented as a three-qubit system that interacts with three separate thermal baths. However, another interesting direction is how to engineer the thermal reservoirs to magnify the current amplification. Here, we derive a quantum dynamical equation for the evolution of the system to study the role of distinct dissipative thermal noises. We compare the amplification gain in different configurations and analyze the role of the correlations in a system exhibiting the thermal transistor effect, via measures borrowed from the quantum information theory.

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Górecki, Krzysztof, and Krzysztof Posobkiewicz. "Influence of a Cooling System on Power MOSFETs’ Thermal Parameters." Energies 15, no. 8 (April 15, 2022): 2923. http://dx.doi.org/10.3390/en15082923.

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In the current paper, an analysis of the influence of cooling system selection on the thermal parameters of two thermally coupled power MOSFETs is presented. The required measurements of the thermal parameters were performed using the indirect electrical method at different values of power dissipated in the investigated transistors and various supply conditions for the active parts of their cooling systems. The results of the investigations are analysed and discussed. Functions modelling the observed dependences of thermal parameters of the investigated MOSFETs on the power that was dissipated in them as well as the supply conditions of the active parts of their cooling systems are proposed. A good agreement between the results of the measurements and the computations was obtained. It is shown that the use of active cooling systems makes it possible to reduce the value of the thermal resistance of the tested transistor up to 20 times. In each of the tested systems, the self- and transfer-thermal resistances decreased with an increase in the dissipated power and the rotational speed of the fan.

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43

Min, Jin-Gi, Dong-Hee Lee, Yeong-Ung Kim, and Won-Ju Cho. "Implementation of Ambipolar Polysilicon Thin-Film Transistors with Nickel Silicide Schottky Junctions by Low-Thermal-Budget Microwave Annealing." Nanomaterials 12, no. 4 (February 13, 2022): 628. http://dx.doi.org/10.3390/nano12040628.

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In this study, the efficient fabrication of nickel silicide (NiSix) Schottky barrier thin-film transistors (SB-TFTs) via microwave annealing (MWA) technology is proposed, and complementary metal-oxide-semiconductor (CMOS) inverters are implemented in a simplified process using ambipolar transistor properties. To validate the efficacy of the NiSix formation process by MWA, NiSix is also prepared via the conventional rapid thermal annealing (RTA) process. The Rs of the MWA NiSix decreases with increasing microwave power, and becomes saturated at 600 W, thus showing lower resistance than the 500 °C RTA NiSix. Further, SB-diodes formed on n-type and p-type bulk silicon are found to have optimal rectification characteristics at 600 W microwave power, and exhibit superior characteristics to the RTA SB-diodes. Evaluation of the electrical properties of NiSix SB-TFTs on excimer-laser-annealed (ELA) poly-Si substrates indicates that the MWA NiSix junction exhibits better ambipolar operation and transistor performance, along with improved stability. Furthermore, CMOS inverters, constructed using the ambipolar SB-TFTs, exhibit better voltage transfer characteristics, voltage gains, and dynamic inverting behavior by incorporating the MWA NiSix source-and-drain (S/D) junctions. Therefore, MWA is an effective process for silicide formation, and ambipolar SB-TFTs using MWA NiSix junctions provide a promising future for CMOS technology.

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44

Mądzik, Mateusz Tomasz, Elangovan Elamurugu, Raquel Flores, and Jaime Viegas. "Impact of glycerol on Zinc Oxide based thin film transistors with Indium Molybdenum Oxide electrodes." MRS Advances 1, no. 4 (2016): 265–68. http://dx.doi.org/10.1557/adv.2016.26.

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ABSTRACTThin-film transistors (TFT) were fabricated at a room-temperature (RT) with zinc oxide (ZnO) channel and indium molybdenum oxide (IMO) electrodes. To isolate the gate oxide and gate electrode influence on the device performance, common gate configuration on a commercial substrate with thermal SiO2 (100 nm) was selected. A threshold voltage (VTh) of 10 V and ION/IOFF ratio of 1 × 10-5 were obtained. Once the reference data was taken transistors were exposed to glycerol. Temporary changes in device characteristics were observed due to the influence of glycerol, a low conductivity medium. To exclude the possibility of sugar alcohol being the main conductor, measurement on dummy transistor electrode was performed retaining the distance between probes. The TFT device under test revealed ten times higher drain current but also a change in threshold voltage and leakage current. Transistors under glycerol influence were always open with the positive gate bias.

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45

El Boukili, Abderrazzak. "New physically based model for thermal induced initial stress in 3D for silicon germanium films after deposition." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 33, no. 6 (October 28, 2014): 2121–38. http://dx.doi.org/10.1108/compel-11-2013-0390.

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Purpose – The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel. Design/methodology/approach – During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature. Findings – Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry. Practical implications – Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch. Originality/value – The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.

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46

Vorona, Mikhail Y., Nathan J. Yutronkie, Owen A. Melville, Andrew J. Daszczynski, Jeffrey S. Ovens, Jaclyn L. Brusso, and Benoît H. Lessard. "Developing and Comparing 2,6-Anthracene Derivatives: Optical, Electrochemical, Thermal, and Their Use in Organic Thin Film Transistors." Materials 13, no. 8 (April 22, 2020): 1961. http://dx.doi.org/10.3390/ma13081961.

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Anthracene-based semiconductors have attracted great interest due to their molecular planarity, ambient and thermal stability, tunable frontier molecular orbitals and strong intermolecular interactions that can lead to good device field-effect transistor performance. In this study, we report the synthesis of six anthracene derivatives which were di-substituted at the 2,6-positions, their optical, electrochemical and thermal properties, and their single crystal structures. It was found that 2,6-functionalization with various fluorinated phenyl derivatives led to negligible changes in the optical behaviour while influencing the electrochemical properties. Furthermore, the choice of fluorinated phenyl moiety had noticeable effects on melting point and thermal stability (ΔTm < 55 °C and ΔTd < 65 °C). Bottom-gate top-contact (BGTC) organic thin transistors (OTFTs) were fabricated and characterized using the 2,6-anthracene derivatives as the semiconducting layer. The addition of fluorine groups on the phenyl groups led to a transition from p-type behaviour to n-type behaviour in BGBC OTFTs.

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47

Górecki, Krzysztof, and Paweł Górecki. "Modelling dynamic characteristics of the IGBT with thermal phenomena taken into account." Microelectronics International 34, no. 3 (August 7, 2017): 160–64. http://dx.doi.org/10.1108/mi-11-2016-0082.

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Purpose This paper aims to propose the electrothermal dynamic model of the insulated gate bipolar transistors (IGBT) for SPICE. Design/methodology/approach The electrothermal model of this device (IGBT), which takes into account both electrical and thermal phenomena, is described. Particularly, the sub-threshold operation of this device is considered and electrical, and thermal inertia of this device is taken into account. Attention was focused on the influence of electrical and thermal inertia on waveforms of terminal voltages of the considered transistor operating in the switching circuit and on waveforms of the internal temperature of this device. Findings The correctness of the presented model is verified experimentally and a good agreement of the calculated and measured electrical and thermal characteristics of the considered device is obtained. Research limitations/implications The presented model can be used for different types of IGBT, but it is dedicated for SPICE software only. Originality/value The form of the worked out model is presented and the results of experimental verification of this model are shown.

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FLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.

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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that VT matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

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Kalemai, Gion, Nikolaos Vagenas, Athina Giannopoulou, and Panagiotis Kounavis. "Band Bending and Trap Distribution along the Channel of Organic Field-Effect Transistors from Frequency-Resolved Scanning Photocurrent Microscopy." Electronics 11, no. 11 (June 6, 2022): 1799. http://dx.doi.org/10.3390/electronics11111799.

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The scanning photocurrent microscopy (SPCM) method is applied to pentacene field-effect transistors (FETs). In this technique, a modulated laser beam is focused and scanned along the channel of the transistors. The resulting spatial photocurrent profile is attributed to extra free holes generated from the dissociation of light-created excitons after their interaction with trapped holes. The trapped holes result from the local upward band bending in the accumulation layer depending on the applied voltages. Thus, the photocurrent profile along the conducting channel of the transistors reflects the pattern of the trapped holes and upward band bending under the various operating conditions of the transistor. Moreover, it is found here that the frequency-resolved SPCM (FR-SPCM) is related to the interaction of free holes via trapping and thermal release from active probed traps of the first pentacene monolayers in the accumulation layer. The active probed traps are selected by the modulation frequency of the laser beam so that the FR-SPCM can be applied as a spectroscopic technique to determine the energy distribution of the traps along the transistor channel. In addition, a crossover is found in the FR-SPCM spectra that signifies the transition from empty to partially empty probed trapping states near the corresponding trap quasi-Fermi level. From the frequency of this crossover, the energy gap from the quasi-Fermi Etp level to the corresponding local valence band edge Ev, which is bent up by the gate voltage, can be estimated. This allows us to spatially determine the magnitude of the band bending under different operation conditions along the channel of the organic transistors.

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Konishi, Nobutake, and Kenji Miyata. "Polycrystalline-Silicon Thin Film Transistor by Thermal Annealing." IEEJ Transactions on Fundamentals and Materials 110, no. 10 (1990): 670–74. http://dx.doi.org/10.1541/ieejfms1990.110.10_670.

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Journal articles on the topic 'Thermal transistor'

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