Relevant bibliographies by topics / Thermal transistor

Academic literature on the topic 'Thermal transistor'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Thermal transistor"

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Timoshenkov, V. P., A. I. Khlybov, D. V. Rodionov, and A. I. Panteleev. "Research of Influence of Power RF GaN Transistor Constructions on it's Thermal Mode." Nano- i Mikrosistemnaya Tehnika 22, no. 8 (October 23, 2020): 415–21. http://dx.doi.org/10.17587/nmst.22.415-421.

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This paper shows influence of power RF GaN transistors construction on it's thermal mode. Field GaN transistor (with field plate) was researched. The influence of field-plate on transistor thermal mode was analysed and compared to other constructions.
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Amar, Abdelhamid, Bouchaïb Radi, and Hami El Abdelkhalak. "Electrothermal Reliability of the High Electron Mobility Transistor (HEMT)." Applied Sciences 11, no. 22 (November 13, 2021): 10720. http://dx.doi.org/10.3390/app112210720.

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The main objective of our paper is to propose an approach to studying the mechatronic system’s reliability through the reliability of their high electron mobility transistors (HEMT). The operating temperature is one of the parameters that influences the characteristics of the transistor, especially the electron mobility that represents an advantage over other transistor’s families. Several factors can influence this temperature. Thanks to thermal modeling, it is possible to determine the factors representing a great impact on the operating temperature, such as the power dissipation at the active area of the transistor and the reference temperature above the substrate. In our reliability study, these analytical methods, such as First and Second Order Reliability Methods (FORM and SORM, respectively), were used to analyze the HEMT reliability. Thanks to the coupling between two models—the reliability model coded on Matlab and the thermal modeling with Comsol multiphysics software—the reliability index and the failure probability of the studied system were evaluated.
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Oh, Se Young, Sun Kak Hwang, Young Do Kim, Jong Wook Park, and In Nam Kang. "Effects of Post Thermal Annealing on the Electrical Properties of Vertical Type Organic Thin Film Transistors Using Poly(3-hexylthiophene) and Its Application in Organic Light Emitting Transistor." Journal of Nanoscience and Nanotechnology 8, no. 9 (September 1, 2008): 4881–84. http://dx.doi.org/10.1166/jnn.2008.ic66.

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We have fabricated the vertical type organic thin film transistor (OTFT) using electrically conductive poly(3-hexylthiophene) (P3HT) as a p-type organic material. Effects of post thermal annealing and thickness of active layer on the performance of vertical type transistors were investigated. Especially, the correlation between carrier mobility of P3HT after post thermal annealing and static characteristics of the transistor was studied. Carrier mobility was calculated by space charge limited current (SCLC) model from the I–V curves of the prepared device. The vertical type OTFT after post thermal annealing at 120 °C (Tg) showed high current of 0.383 mA and on–off ratio of 22.5 at a low gate voltage of +2.0 V. Additionally, we report on emission characteristics from the vertical type transistor using P3HT.
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Roberts, J., T. MacElwee, and L. Yushyna. "The Thermal Integrity of Integrated GaN Power Modules." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000061–68. http://dx.doi.org/10.4071/hiten-mp12.

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In this paper the authors describe GaN (gallium nitride) power switching transistors that use copper post and substrate via interconnect techniques. These transistors can be matrixed to allow a parallel array of the devices to provide very low on-resistance and high operating voltages. At 150 °C the basic building block which is a 2 × 2 mm die, provides 1200 V / 14 A. A 2×2 matrix array of these transistors provides for example, 1200 V / 56 A operation. The overall GaN device size is 4 × 4 mm. This high current density is achieved by using a unique castellated island topology. This provides short fingers that are not required to carry high current. No high current tracks are provided on-chip because on-chip metal is typically less than 3 microns thick. The die has 12 copper posts on the source islands that carry the current to the CMOS driver device. The CMOS driver is used in a cascode configuration which allows the normally-on GaN transistor to be operated with convenient normally-off functionality. The two devices are combined in a modular assembly. The paper provides a thermal analysis of the assembly. The objective of the design is to keep the ‘junction’ temperature of the GaN transistor below 150 °C.
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Пашковский, А. Б., И. В. Куликова, В. Г. Лапин, В. М. Лукашин, Н. К. Приступчик, Л. В. Манченко, В. Г. Калина, М. И. Лопин, and А. Д. Закурдаев. "Поверхностный тепловой интерфейс для мощных арсенид-галлиевых гетероструктурных полевых транзисторов." Журнал технической физики 89, no. 2 (2019): 252. http://dx.doi.org/10.21883/jtf.2019.02.47079.2493.

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AbstractApplication of heat-conducting coatings for cooling of high-power FETs based on heterostructures with arsenide–gallium substrate is theoretically analyzed. When the basic technology for manufacturing of transistors is employed in the absence of additional efforts aimed at a decrease in the thermal resistance of the substrate, the application of an additional thermal interface that represents a heat-conducting dielectric coating makes it possible to substantially decrease the overheating of the transistor channel. A several-fold decrease in such overheating can be reached using variations in the thickness of the coating and modification of the transistor structure and working regimes.
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Njawah Achiri, Humphrey Mokom, Vaclav Smidl, Zdenek Peroutka, and Lubos Streit. "Least Squares Method for Identification of IGBT Thermal Impedance Networks Using Direct Temperature Measurements." Energies 13, no. 14 (July 21, 2020): 3749. http://dx.doi.org/10.3390/en13143749.

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State-of-the-art methods for determining thermal impedance networks for IGBT (Insulated Gate Bipolar Transistor) modules usually involves the establishment of the relationship between the measured transistor or diode voltage and temperature under homogenous temperature distribution across the IGBT module. The junction temperature is recomputed from the established voltage–temperature relationship and used in determining the thermal impedance network. This method requires accurate measurement of voltage drop across the transistors and diodes under specific designed heating and cooling profiles. Validation of the junction temperature is usually done using infrared camera or sensors placed close to the transistors or diodes (in some cases and open IGBT module) so that the measured temperature is as close to the junction as possible. In this paper, we propose an alternative method for determining the IGBT thermal impedance network using the principles of least squares. This method uses measured temperatures for defined heating and cooling cycles under different cooling conditions to determine the thermal impedance network. The results from the proposed method are compared with those obtained using state-of-the-art methods.
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Ron Liu, D., K. Chen, and E. Jih. "Observation of Microstructural Evolution of Aluminum Bonding Wires in Power Electronic Package." Microscopy and Microanalysis 5, S2 (August 1999): 876–77. http://dx.doi.org/10.1017/s1431927600017700.

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Power electronic circuits are used in electric vehicle or hybrid electric vehicle to drive the main electric motor. All the transistors and diodes in a sealed power electronic package will experience repeated high current cycling during their service life. The aluminum bonding wires which connect these devices to the rest of the circuit will experience repeated thermal strain cycling. When design a power electronic package, the thermal fatigue durability of these bonding wires would be a concern. A power electronic module with pure aluminum bonding wires of 0.5mm in diameter from a vendor was power cycled with the following schedule. Each transistor in the circuit was on for 10 seconds with the current at 400 Amperes followed by the transistor being off for 30 seconds. The wires from the diodes to the copper trace lines are about twice as long as those from the transistors to the copper trace lines.
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Vachhani, M. G., and P. N. Gajjar. "Influence of Chain Length of 1D Thermal Transistor on Thermal Amplification Factor." Advanced Materials Research 1141 (August 2016): 72–76. http://dx.doi.org/10.4028/www.scientific.net/amr.1141.72.

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We study the influence of chain length of our 1D model of thermal transistor on thermal amplification factor. Here, we varied the length of drain and source segments for different simulation experiment and found that the maximum value of thermal amplification factor influenced with chain length. The thermal amplification factor of the thermal transistor is found to be dependent on gate temperature. We also calculated the switching efficiency and working region of the thermal transistor and better results are obtained in comparison to previous study.
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Hamana, Yoshiki, and Takahide Oya. "Improvement of Performance of Paper Transistor Using Carbon-Nanotube-Composite Paper and its Application to Logic Circuit." Advances in Science and Technology 95 (October 2014): 32–37. http://dx.doi.org/10.4028/www.scientific.net/ast.95.32.

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We propose development of an advanced type of "paper transistor" by using carbon-nanotube (CNT) composite papers (CNTCPs) and aim to apply our paper transistors to the construction of logic circuits. It is known that CNTs have many functions such as high electrical and thermal conductivities and metallic and semiconducting properties. Our CNTCP, which has various functions held by CNTs despite being paper, can be fabricated easily by scooping up and drying materials from a mixture of CNT and pulp (paper materials) dispersions. The CNTs have metallic or semiconducting properties, so metallic and semiconducting CNTCPs can be fabricated. By preparing such CNTCPs and normal paper as an insulator, we can produce the paper transistor. In previous work, we confirmed our prototype paper transistor could operate as a p-type transistor. However, the sample had problems, e.g., the internal resistance was rather high. In this study, we aim to overcome the problems by using a novel method for making the CNTCP. As the result of experiments, we succeeded in obtaining new paper transistors with better performance in comparison with the previous one. Moreover, we succeeded in finding a potential use as an n-type paper transistor by using an n-type doping material for semiconducting CNTCPs.
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Bunea, Gabriela E., S. T. Dunham, and T. D. Moustakas. "Modeling of a GaN Based Static Induction Transistor." MRS Internet Journal of Nitride Semiconductor Research 4, S1 (1999): 697–702. http://dx.doi.org/10.1557/s1092578300003276.

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Static induction transistors (SITs) are short channel FET structures which are suitable for high power, high frequency and high temperature applications. GaN has particularly favorable properties for SIT operation. However, such a device has not yet been fabricated. In this paper we report simulation studies on GaN static induction transistors over a range of device structures and operating conditions. The transistor was modeled with coupled drift-diffusion and heat-flow equations. We found that the performance of the device depends sensitively on the thermal boundary conditions, as self-heating effects limit the maximum voltage swing.
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Dissertations / Theses on the topic "Thermal transistor"

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Liu, Wei. "Electro-thermal simulations and measurements of silicon carbide power transistors." Doctoral thesis, Stockholm, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-86.

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Lim, Dan J. "Characterization of thermal dissipation within integrated gate bipolar transistor (IGBT) layered packaging structure." Thesis, University of Hull, 2008. http://hydra.hull.ac.uk/resources/hull:1681.

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Integrated Gate Bipolar Transistors (IGBTs) generally have a high output power and generate significant amounts of heat, which needs to be removed from the chip to ensure continued operation. Since IGBT chips are commonly mounted on a layered assembly structure which is in turn mounted onto a heat sink assembly, the thermal dissipation properties of the layered structure are crucial in keeping temperatures within operational boundaries. Traditionally, the selection of materials for the layered structure has been largely influenced by the thermal conductivity for heat dissipation, the similarity of the coefficient of thermal expansion for physical integrity of the structure and to a lesser extent, the weight of the material. These principles of material selection are indeed adequate for steady state operation of IGBTs. However, IGBTs are often installed in applications where they are subjected to pulsed operation, which is predominantly transient. During transient operation, it was found that thermal conductivity was not necessarily the best criterion to use for material selection within the layered structure. In certain instances, materials that absorbed heat rather than conducting it yielded lower temperatures and higher cooling rates, which in turn resulted in lower start temperatures in the next pulse. This study therefore proposes an additional material selection criterion, one based on the density-specific heat capacity product that should be used in conjunction with thermal conductivity to guide the material selection process, opening the door to material combinations for specific applications that could enhance chip lifespan and reduce deliamination. Materials with high density-specific heat capacity products could also potentially be used to compensate for the thermal "bottlenecking" effect. This study was conducted with numerous simulations based on the well validated Transmission Line Matrix Modelling method.
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Baylis, Charles Passant II. "Improved Current-Voltage Methods for RF Transistor Characterization." Scholar Commons, 2004. https://scholarcommons.usf.edu/etd/950.

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In the development of a nonlinear transistor model, several measurements are used to extract equivalent circuit parameters. The current-voltage (IV) characteristic of a transistor is one of the measurement data sets that allows the nonlinear model parameters to be extracted. The accuracy of the IV measurement greatly influences the accuracy of the large-signal model. Numerous works have reported the inadequacy of traditional static DC IV measurements to accurately predict radio-frequency (RF) behavior for many devices. This inaccuracy results from slow processes in the device that do not have time to completely respond to the quick changes in terminal conditions when the device is operating at high frequencies; however, these slow processes respond fully to reach a new steady-state condition in the DC sweep measurement. The two dominant processes are self-heating of the device and changes in trap occupancy. One method of allowing the thermal and trap conditions to remain in a state comparable to that of RF operation is to perform pulsed IV measurements to obtain the IV curves. In addition, thermal correction can be used to adjust the IV curves to compensate for self-heating in the case that the predominant effect in the device is thermal. To gain a better understanding of pulsed IV measurement techniques, measurement waveforms of a commercially available pulsed IV analyzer are examined in the time domain. In addition, the use of bias tees with pulsed IV measurement is explored; such a setup may be desired to maintain stability or to enable simultaneous pulsed S-parameter and pulsed IV measurement. In measurements with bias tees, the pulse length setting must be long enough to allow the voltage across the inductor to change before the measurement is made. In many circumstances, it is beneficial to compare different sets of IV curves for a device. The comparison of pulsed and static IV measurements, measured and modeled IV measurements, as well as two measurements with identical settings on the same instrument (to ascertain instrument repeatability) can be performed using the proposed normalized difference unit (NDU). This unit provides a comparison that equally weights the two sets of data to be compared. Due to the normalization factor used, the value of the NDU is independent of the size of the device for which the IV curves are compared. The variety of comparisons for which this unit can be used and its ability to present differences quantitatively allow it to be used as a robust metric for comparing IV curves. Examples of the use of the NDU shown include determination of measurement repeatability, comparison of pulsed and static IV data, and a comparison of model fits. The NDU can also be used to isolate thermal and trapping processes and to give the maximum pulse length that can be used for pulsed IV measurement without contamination by each of these processes. Plotting the NDU comparing static and pulsed IV data versus pulse length shows this maximum pulse length that can be used for each effect, while a plot of the NDU comparing pulsed IV data for two quiescent bias points of equal power dissipation reveals only differences due to trapping effects. In this way, trapping effects can be distinguished from thermal effects. Electrothermal modeling has arisen as a method of correcting for self-heating processes in a device with predominantly thermal effects. A parallel RC circuit is used to model channel temperature as a function of ambient temperature and power dissipated in the channel or junction. A technique is proposed for thermal resistance measurement and compared with a technique found in the literature. It is demonstrated that the thermal time constant can be measured from a plot of the NDU versus pulse length, and the thermal capacitance is then obtained using the thermal resistance and time constant. Finally, the results obtained through the thermal resistance measurement procedures are used to thermally correct static IV curves. Because trapping effects are negligible, it is shown that IV curves corresponding to different quiescent bias points for a Si LDMOSFET can be synthesized from three sets of static IV data taken at different ambient temperatures. The results obtained from this correction process for two quiescent bias points are compared to the pulsed IV results for these quiescent bias points and found to be quite accurate. Use of the methods presented in this work for obtaining more accurate transistor IV data data should assist in allowing more accurate nonlinear models to be obtained.
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Dhombres, Stéphanie. "Étude d'un protocole de régénération thermique de composants électroniques soumis à un rayonnement ionisant." Thesis, Montpellier, 2015. http://www.theses.fr/2015MONTS228.

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De nos jours, les caméras sont de plus en plus utilisées lors de missions spatiales ou en centrale nucléaire pour des missions d'observations (civiles ou militaires) et de surveillance (vérification du déploiement de panneaux solaires, opérations extravéhiculaires, accident nucléaire, site de stockage). L'environnement spatial, les réacteurs civils nucléaires ou les lieux de stockage de déchets radioactifs sont des milieux radiatifs qui peuvent très fortement perturber les composants électroniques et les systèmes. Dans ces environnements, les rayonnements ionisants dégradent les paramètres électriques des composants électroniques. La dose totale ionisante conduit à l'apparition d'un nombre significatif de charges dans les oxydes des matériaux constituant les composants électroniques, modifiant leurs propriétés électriques. Il en résulte qu'une exposition à la dose totale ionisante peut entraîner une défaillance partielle ou totale d'un composant voire d'un système électronique embarqué.Dans le cadre de cette thèse, nous proposons une méthode de régénération pour guérir les paramètres électriques dégradés par la dose totale ionisante de composants électroniques soumis aux rayonnements ionisants. Cette méthode consiste à appliquer des cycles de recuit isothermes à un composant électronique. Dans un premier temps, cette méthode est appliquée sur des transistors MOS, et une étude est menée sur l'impact des différents paramètres clés du recuit (polarisation, température, durée de recuit, pas en dose entre chaque recuit). Dans un second temps, nous nous intéressons à des composants plus intégrés et plus récents tels que des capteurs d'images de type CMOS APS. Nous montrons expérimentalement l'impact d'un recuit sur ce type de composant et enfin, nous adaptons la méthode de régénération pour l'appliquer à ces capteurs APS afin d'augmenter leur durée de vie
Nowadays, cameras are more and more used in space missions or nuclear plant for observation (civil or military) and monitoring missions (checking the deployment of solar panels, extravehicular operations, nuclear accident, and area storage). The space environment, nuclear reactors or radioactive waste storage areas are radiative environments that can greatly disturb electronic components and systems. In these environments, ionizing radiation degrades the electrical parameters of electronic components. The total ionizing dose induces significant charge build-up in oxides, degrading the electrical properties of the materials of electronic devices. That can result in the loss of functionality of the entire electronic system.In this thesis, we propose a regeneration method to recover the electrical parameters degraded by total ionizing dose of electronic components subjected to ionizing radiation. In this method isothermal annealing cycles are applied to electronic devices. In a first step, this method is applied on MOS transistors, and a study is conducted on the impact of various key parameters of annealing (bias, annealing temperature, annealing time, dose step between each annealing). In a second step, we focus on components more integrated and newer such as CMOS APS image sensors. We experiment what is the impact of annealing on this type of component and finally, the regeneration method is modified to be suitable on these APS sensors to increase their lifetime
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Uesugi, Y., T. Imai, K. Kawada, and S. Takamura. "Fundamental and Third Harmonic Operation of SIT Inverter and its Application to RF Thermal Plasma Generation." IEEE, 2002. http://hdl.handle.net/2237/7175.

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Najjari, Hamza. "Power Amplifier Design Based on Electro-Thermal Considerations." Thesis, Bordeaux, 2019. http://www.theses.fr/2019BORD0422.

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L’objectif de ce travail de recherche est de concevoir un amplificateur de puissance sur la base de considérations électrothermiques. Il décrit la question du dynamique EVM et du « paquet long » lors de la conception de l’amplificateur avec des transistors bipolaires à hétérojonctions. Basé sur le comportement électrothermique du circuit, une méthode d’optimisation de l’EVM statique et dynamique est proposée. Un frontend RF complet (amplificateur de puissance + coupleur + interrupteur + amplificateur faible bruit) est conçu pour le dernier standard WLAN : le Wi-Fi 6. La distribution de temperature dynamique dans le circuit est analysée. Son effet sur les performances de la puce est quantifié. Enfin, une polarisation adaptative programmable a été conçue pour garder des performances optimales sur toute la plage de température. Les mesures du circuit montre tout l’effet bénéfique de cette compensation, permettant de garder le dynamique EVM en dessous de -47 dB sur la plage de température ambiante de -40 à 85°C
The aim of this work is to design a power amplifier based on electrothermal considerations. It describes the Dynamic Error Vector Magnitude challenge and long packet issue when designing a power amplifier with hetero-junction bipolar transistors. Based on the circuit electrothermal behavior, an optimization method of both the static and dynamic linearity is proposed. A complete RF front-end (PA + coupler + switch + LNA) is designed for the latest WLAN standard: the Wi-Fi 6. The dynamic temperature distribution in the circuit is analyzed. It’s impact on the performances is quantified. Finally, a programmable temperature dependent bias is designed to compensate for performance degradation. The measurements show a significant linearity improvement with this compensation, allowing the PA to maintain the DEVM lower than -47dB at 14.5 dBm output power, over a large ambient temperature range from -40°C to 85°C
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Dia, Hussein. "Contribution à la modélisation électrothermique : Elaboration d'un modèle électrique thermosensible des composants MOS de puissance." Thesis, Toulouse, INSA, 2011. http://www.theses.fr/2011ISAT0006/document.

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Une forte exigence de robustesse s’est imposée dans tous les domaines d’application des composants de puissance. Dans ce cadre très contraint, seule une analyse fine des phénomènes liés directement ou indirectement aux défaillances peut garantir une maîtrise de la fiabilité des fonctions assurées par les nouveaux composants de puissance. Cependant, ces phénomènes impliquent des couplages entre des effets électriques, thermiques et mécaniques, rendant leur étude très complexe. Le recours à la modélisation multi-physique bien adaptée s’avère alors déterminant. Dans ce mémoire de thèse, nous proposons une méthodologie de modélisation électrique prenant en compte les effets de la température sur les phénomènes localisés qui initient une défaillance souvent fatale. En prévision de la simulation électrothermique couplée impliquant des transistors MOS de puissance, un modèle électrique thermosensible de ce composant et de sa diode structurelle a été développé. Corrélativement un ensemble de bancs expérimentaux a été mis en œuvre pour l’extraction des paramètres et pour la validation du modèle. Une attention particulière a été accordée à l’étude des phénomènes parasites qui pourraient survenir de manière très localisée suite à une répartition inhomogène de la température et à l’apparition de points chauds. Ainsi les fonctionnements limites en avalanche, avec le déclenchement du transistor bipolaire parasite et de son retournement ont été modélisés. Des bancs spécifiques pour la validation du modèle pour les régimes extrêmes ont été utilisés en prenant des précautions liées à la haute température. Enfin, Le modèle électrique thermosensible complet développé a été utilisé par la société Epsilon ingénierie pour faire des simulations électrothermiques du MOS de puissance en mode d’avalanche en adaptant le logiciel Epsilon-R3D
Strong demand for robustness has emerged in all areas of application of power components.Only a detailed analysis of phenomena related directly or indirectly to failures can ensure thereliability of the functions of the new power components. However, these phenomena involvethe coupling between electrical effects, thermal and mechanical, making their study verycomplex. The use of multi-physics modeling is well suited when determining. In this thesis,we propose a methodology for electrical modeling taking into account the effects of temperatureon the localized phenomena that initiate failure is often fatal. In preparation for thecoupled electro-thermal simulation involving MOS power transistors, an electric thermosensitivemodel of the MOS and its body diode has been developed. Correspondingly a set ofexperimental studies was implemented to extract the parameters and model validation. Particularattention was paid to the study of interference phenomena that could occur in a localizedresponse to an inhomogeneous distribution of temperature and hot spots. Thus the workingslimits avalanche, with the outbreak of parasitic bipolar transistor (snapback) and its reversalwere modeled. Benches specific validations of the model for harsh switching conditions wereused by taking precautions related to high temperature. Finally, the complete thermal electricmodel developed was used by the company “EPSILON Ingénierie” for electro-thermal simulationof power MOS mode Avalanche Software adapting Epsilon-R3D
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Micout, Jessy. "Fabrication et caractérisation de transistor réalisée à basse température pour l'intégration 3D séquentielle." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT008/document.

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La réduction des dimensions des dispositifs MOSFET devient de plus en plus complexe a réalisé, et les nouvelles technologies MOSFET se confrontent à de fortes difficultés. Pour surmonter ce problème, une nouvelle technique, appelée intégration 3D VLSI, est étudiée : remplacer la structure plane conventionnelle par un empilement vertical de transistors.En particulier, l’intégration 3D séquentielle ou CoolCube™ au CEA-Leti permet de profiter pleinement de la troisième dimension en fabriquant séquentiellement les transistors. La réalisation d’une telle intégration apporte une nouvelle contrainte, celle de fabriquer le transistor du dessus avec un budget thermique faible (inférieur à 500°C), afin de préserver les performances du transistor d'en dessous. Puisque ce budget thermique est principalement influencé par l'activation des dopants, plusieurs techniques innovatrices sont actuellement investiguées au CEA-LETI, afin de fabriquer le drain et la source. Dans ce manuscrit, nous utiliserons la recristallisation en phase solide comme mécanisme pour activer les dopants (inférieures à 600 °C). L’objectif de cette thèse est donc de fabriquer et de caractériser des transistors dont l’activation des dopants est réalisée grâce à ce mécanisme, afin d’atteindre des performances similaires à des transistors réalisés avec un budget thermique standard. Ce travail est organisé autour de l’activation des dopants, et en trois chapitres, où chaque chapitre est spécifique à une intégration (« Extension Last »/ « Extension First », « Gate Last »/ « Gate First ») et à une architecture (FDSOI, FINFET) considérées. Ces chapitre permettront, grâce aux caractérisations électriques, morphologiques et aux simulations, de développer un procédé de recristallisation stable à 500°C, à la fois pour les nMOS et les pMOS, et de proposer de nouveaux schémas d’intégrations, afin de réaliser des transistors à faible budget thermique et compatibles avec l’intégration 3D Séquentielle
The down scaling of MOSFET device is becoming harder and the development of future generation of MOSFET technology is facing some strong difficulties. To overcome this issue, the vertical stacking of MOSFET in replacement of the conventional planar structure is currently investigated. This technique, called 3D VLSI integration, attracts a lot of attention, in research and in the industry. Indeed, this sequential stacking of transistor enables to gain in density and performance without reducing transistors dimensions.More specifically, 3D sequential integration or CoolCube™ at CEA-Leti enables to fully benefit of the third dimension by sequentially manufacturing transistors. Implementing such an integration provides the new constraint of manufacturing top transistor with low thermal budget (below 500°C) in order to preserve bottom-transistor performances. As most of the thermal budget is due to the dopant activation, several innovative techniques are currently investigated at CEA-LETI.In this work, solid phase epitaxy regrowth will be used as the mechanism to activate dopants below 600°C. The aim of this thesis is thus to manufacture and to characterize transistors with low-temperature dopant activation, in order to reach the same performance as devices manufactured with standard thermal budget. The work is organized around the dopant activation, and in three chapters, according to each considered integration scheme (Extension Last/ Extension First, Gate Last/ Gate First) and architecture (FDSOI, FINFET). These chapters, assisted by relevant simulations, electrical and morphological characterizations, will enable to develop a new and stable 500°C recrystallization process for both N and P FETs, and to propose new integration schemes in order to manufacture transistors with low thermal budget and compatible with the 3D sequential integration
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Dia, Hussein. "Contribution à la modélisation électrothermique: Elaboration d'un modèle électrique thermosensible du transistor MOSFET de puissance." Phd thesis, INSA de Toulouse, 2011. http://tel.archives-ouvertes.fr/tel-00624193.

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Une forte exigence de robustesse s'est imposée dans tous les domaines d'application des composants de puissance. Dans ce cadre très contraint, seule une analyse fine des phénomènes liés directement ou indirectement aux défaillances peut garantir une maîtrise de la fiabilité des fonctions assurées par les nouveaux composants de puissance. Cependant, ces phénomènes impliquent des couplages entre des effets électriques, thermiques et mécaniques, rendant leur étude très complexe. Le recours à la modélisation multi-physique bien adaptée s'avère alors déterminant. Dans ce mémoire de thèse, nous proposons une méthodologie de modélisation électrique prenant en compte les effets de la température sur les phénomènes localisés qui initient une défaillance souvent fatale. En prévision de la simulation électrothermique couplée impliquant des transistors MOS de puissance, un modèle électrique thermosensible de ce composant et de sa diode structurelle a été développé. Corrélativement un ensemble de bancs expérimentaux a été mis en oeuvre pour l'extraction des paramètres et pour la validation du modèle. Une attention particulière a été accordée à l'étude des phénomènes parasites qui pourraient survenir de manière très localisée suite à une répartition inhomogène de la température et à l'apparition de points chauds. Ainsi les fonctionnements limites en avalanche, avec le déclenchement du transistor bipolaire parasite et de son retournement ont été modélisés. Des bancs spécifiques pour la validation du modèle pour les régimes extrêmes ont été utilisés en prenant des précautions liées à la haute température. Enfin, Le modèle électrique thermosensible complet développé a été utilisé par la société EPSILON Ingénierie pour faire des simulations électrothermiques du MOS de puissance en mode d'avalanche en adaptant le logiciel Epsilon-R3D.
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Bebiche, Sarah. "OTFTs de type N à base de semiconducteurs π-conjugués : fabrication, performance et stabilité." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S105/document.

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L'objectif de ce travail de recherche est l'élaboration et l'optimisation de transistors à effet de champ organiques de type N (OTFTs). Des transistors en structure Bottom Gate Bottom Contact sont fabriqués à basse température T<120°C. Trois différentes molécules organiques conductrices d'électrons, déposées par évaporation thermiques, sont utilisées pour la couche active. Les OTFTs à base de la première molécule à corps LPP présentent de faibles mobilités à effet de champ de l'ordre de 10-5cm2/V.s. L'étude d'optimisation menée sur les conditions de dépôt de cette dernière n'a pas permis d'améliorer ses performances électriques. L'étude de stabilité électrique ''Gate Bias Stress'' a mis en évidence les instabilités de cette molécule. Les OTFTs à base des deux dérivés indénofluorènes (IF) possèdent des mobilités plus importantes. Dans les conditions optimales la molécule IF(CN2)2 méta permet d'atteindre une mobilité d'effet de champ µFE=2.1x10-4 cm2/V, alors que la molécule IF(CN2)2 para permet d'obtenir des mobilités µFE=1x10-2cm2/V.s après recuit. L'étude de stabilité électrique a mis en évidence une meilleure stabilité des OTFTs à base de IF(CN2)2 para. Une étude des phénomènes de transport de charges est menée pour les deux types de molécules. Les OTFTs de type N réalisés sont utilisés pour la réalisation d'un circuit logique de type inverseur pseudo-CMOS. Finalement, ce procédé basse température nous a permis de réaliser des OTFTs sur substrat flexible
The main goal of this present work consists in the fabrication and optimization of N type organic field effect transistors. Bottom Gate Bottom Contact transistors are performed at low temperature T<120°C. Three different electro-deficient organic molecules are thermally evaporated and used as active layer. OTFTs based on LPP core molecule present low field effect mobility around 10-5cm2/V.s. The optimization study investigated on deposition parameters of this molecule on OTFTs performances does not allow improving this mobility. Moreover gate bias stress measurements reveal important instabilities related to this molecule. Indenfluorene derivatives core (IF) based OTFTs show better performances. Field effect mobility µFE=2.1x10-4 cm2/V is reached using IF(CN2)2 meta in optimized deposition conditions and µFE=1x10-2 cm2/V.s is obtained using IF(CN2)2 para after annealing treatment. The investigated gate bias stress study highlights the good electrical stability of IF(CN2)2 para based OTFTs. Temperature measurements allow us studying the charge transport phenomenon in these indenofluorene derivatives. Fabricated N-type OTFTs are used to perform a first electronic circuit that consists in a logic gate (invertor).Finally this low temperature process led us to achieve OTFTs devices on flexible substrates (PEN)
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Books on the topic "Thermal transistor"

1

Oettinger, Frank F. Thermal resistance measurements. Gaithersburg, MD: U.S. Dept. of Commerce, National Institute of Standards and Technology, 1990.

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Oettinger, Frank F. Thermal resistance measurements. Gaithersburg, MD: U.S. Dept. of Commerce, National Institute of Standards and Technology, 1990.

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Yun, Chan-Su. Static and dynamic thermal behavior of IGBT power modules. Konstanz: Hartung-Gorre, 2001.

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Anholt, Robert. Electrical and thermal characterization of MESFETs, HEMTs, and HBTs. Boston: Artech House, 1995.

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Christou, A. Reliability of high temperature electronics. College Park, Md: Center for Reliability Engineering, University of Maryland, 1996.

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International High Temperature Electronics Conference (4th 1998 Albuquerque, N.M.). 1998 Fourth International High Temperature Electronics Conference: HITEC, Albuquerque, New Mexico, USA, June 14-18, 1998. New York City, NY: The Institute of Electrical and Electronics Engineers, Inc., 1998.

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Lee, Sang-Gug. Predictive modeling of high-current output resistance and thermal effects in bipolar junction transistors. 1992.

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Jeon, Deok-Su. Modeling the temperature dependence of the silicon-on-insulator mosfet for high-temperature applications. 1990.

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Lin, Angela A. Two dimensional numerical simulation of a non-isothermal GaAs MESFET. 1992.

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1998 Fourth International High Temperature Electronics Conference: HITEC, Albuquerque, New Mexico, USA, June 14-18, 1998. The Institute of Electrical and Electronics Engineers, Inc, 1998.

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Book chapters on the topic "Thermal transistor"

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Bisht, Arvind, Yogendra Pratap Pundir, and Pankaj Kumar Pal. "Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor." In Communications in Computer and Information Science, 126–36. Cham: Springer Nature Switzerland, 2022. http://dx.doi.org/10.1007/978-3-031-21514-8_12.

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Baghaz, E., A. Naamane, and N. K. M’sirdi. "Electrical and Thermal Modeling and Aging Study of a C2M0025120D Silicon Carbide-Based Power MOSFET Transistor." In Lecture Notes in Electrical Engineering, 313–18. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1405-6_38.

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Stoecker, W. F., and P. A. Stoecker. "Transistors." In Microcomputer Control of Thermal and Mechanical Systems, 45–60. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4684-6560-0_4.

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Harrak, Abdelkhalak, and Salah Eddine Naimi. "Design and Simulation of an Ion Sensitive Field Effect Transistor (ISFET) Readout Circuit, with Low Thermal Sensitivity." In Lecture Notes in Electrical Engineering, 306–12. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1405-6_37.

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Denny, Allen, Neelkanth Kirloskar, Babu Rao Ponangi, Rex Joseph, and V. Krishna. "Electro-Thermal Model for Field Effective Transistors." In Recent Advances in Hybrid and Electric Automotive Technologies, 277–84. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2091-2_21.

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Lin, Kun Wei. "Hydrogen Sensing Characteristics of High Electron Mobility Transistor with a Catalytic Pd Metal." In THERMEC 2006, 5025–30. Stafa: Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/0-87849-428-6.5025.

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Hung, C. W., S. Y. Cheng, Kun Wei Lin, Y. Y. Tsai, P. H. Lai, S. I. Fu, and W. C. Liu. "Hydrogen Detection by a GaAs-Based Transistor with a Palladium (Pd) Thin Film Gate Structure." In THERMEC 2006 Supplement, 275–80. Stafa: Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-429-4.275.

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Canali, Claudio, Giuseppe Castellaneta, Fabrizio Magistrali, Marco Sangalli, Carlo Tedesco, and Enrico Zanoni. "Thermally Activated Failure Modes and Mechanisms of High Electron Mobility Transistors." In ESSDERC ’89, 813–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-52314-4_171.

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Kokkalera, S., C. T. Tsai, L. L. Liou, J. Barrette, C. Bozada, R. Dettmer, B. Fitch, M. Mack, and J. Sewell. "Simulation of Thermally Shunted Multiple-Emitter-Finger AlGaAs/GaAs Heterojunction Bipolar Transistors Using A Finite Element Code." In Computational Mechanics ’95, 610–15. Berlin, Heidelberg: Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/978-3-642-79654-8_100.

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Sharma, Sanjeev Kumar, Parveen Kumar, and Balwinder Raj. "Introduction to Nanowires." In Advances in Computer and Electrical Engineering, 1–15. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch001.

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This chapter describes nanowires (NWs), their types, characteristic features, and their use in sensor and transistor applications as well. Introductory part in general explains briefly about nanowires (NWs), their characteristics features, types, as well as their most significant properties. The types of nanowires (NWs) can be of conducting materials such as Ni, Pt, Au; semiconducting materials like Si, InP, GaN; as well as insulating materials like that of SiO2, TiO2, etc. The property of nanowires includes mechanical, electrical, chemical, optical, and thermal properties. Also, a small description of nanowires (NWs) and sensors are explained with their performance parameters. Furthermore, nanowires (NWs)-based transistors are discussed in addition with their characteristics and applications. Finally, this chapter concludes with the significance of nanowires (NWs) in contemporary era.
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Conference papers on the topic "Thermal transistor"

1

Oarethu, Johns, Zhigang Song, Pat McGinnis, Stephen Wu, Phong Tran, Mike Tenney, and Richard Oldrey. "Investigation of Thermal Laser Stimulation (TLS) Effects on 7nm FinFET Transistor Parameters." In ISTFA 2022. ASM International, 2022. http://dx.doi.org/10.31399/asm.cp.istfa2022p0129.

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Abstract Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.
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Ko, Seung Hwan, Inkyu Park, Heng Pan, Albert P. Pisano, and Costas P. Grigoropoulos. "Low Temperature OFET (Organic Field Effect Transistor) Fabrication by Metal Nanoparticle Imprinting." In ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/ipack2007-33448.

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The low temperature fabrication of OFET (organic field effect transistor) is presented in this paper. PDMS imprinting mold was used to pattern gold nano-particles suspended in Alpha-Terpineol solvent. After imprinting, nanoparticles was dried and then sintered at plastic compatible low temperature. Finally, air stable semiconductor polymer (modified polythiophene) in dichlorobenzene (o-DCB) solution to fabricate OFETs on flexible polymer substrates. The performance of the transistors were characterized and discussed.
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Suwa, Tohru, and Hamid Hadim. "Multi-Packaging-Level Thermal Modeling Technique for Silicon Chip Transistors." In ASME 2009 International Mechanical Engineering Congress and Exposition. ASMEDC, 2009. http://dx.doi.org/10.1115/imece2009-11815.

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Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis at micrometer level has not been possible using conventional techniques. For the present study, an efficient and accurate multi-level thermal modeling and analysis technique integrating transistor level into silicon chip level has been developed. The technique combines finite element analysis sub-modeling and superposition methods for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained using the superposition method. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled in the finite element analysis, the effect of the package is also included in the superposition results, which makes possible to model over one million transistors in a silicon chip. No present methodologies for existing silicon chip thermal modeling techniques have been able to model such a large number of transistors. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip.
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Tsarapkin, Dmitry P., and Alexis V. Kononov. "Thermal Feedback in Transistor Oscillators." In 2007 IEEE International Frequency Control Symposium Joint with the 21st European Frequency and Time Forum. IEEE, 2007. http://dx.doi.org/10.1109/freq.2007.4319135.

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Maize, Kerry, Xi Wang, Dustin Kendig, Ali Shakouri, William French, Barry O'Connell, Philip Lindorfer, and Peter Hopper. "Thermal characterization of high power transistor arrays." In 2009 25th Annual IEEE Semiconductor Thermal Measurement and Management Symposium. IEEE, 2009. http://dx.doi.org/10.1109/stherm.2009.4810742.

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Zubert, Mariusz, Marcin Janicki, Tomasz Raszkowski, and Andrzej Napieralski. "The thermal model of Fin-FET transistor." In 2015 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC). IEEE, 2015. http://dx.doi.org/10.1109/therminic.2015.7389597.

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Chen, Tianbing, Tzung-Yin Lee, Justin Allum, and Mike McPartlin. "The thermal scaling: From transistor to array." In 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2014. http://dx.doi.org/10.1109/rfic.2014.6851675.

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Fruehauf, Norbert. "Low Temperature Thin Film Transistor Technologies." In 2007 15th International Conference on Advanced Thermal Processing of Semiconductors. IEEE, 2007. http://dx.doi.org/10.1109/rtp.2007.4383807.

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Vachhani, M. G., and P. N. Gajjar. "The state of art model for thermal transistor." In INTERNATIONAL CONFERENCE ON CONDENSED MATTER AND APPLIED PHYSICS (ICC 2015): Proceeding of International Conference on Condensed Matter and Applied Physics. Author(s), 2016. http://dx.doi.org/10.1063/1.4946493.

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Hossain, Md Mahbub. "Thermal Node Characteristics of a Bipolar Junction Transistor." In 2019 IEEE International Conference on Electro Information Technology (EIT). IEEE, 2019. http://dx.doi.org/10.1109/eit.2019.8834123.

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Reports on the topic "Thermal transistor"

1

Bennett, G., M. Thompson, T. Larkin, and J. Hedstrom. Rf transistor thermal/electrical characterization. Office of Scientific and Technical Information (OSTI), September 1989. http://dx.doi.org/10.2172/5413222.

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Ovrebo, Gregory K. Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module. Fort Belvoir, VA: Defense Technical Information Center, February 2015. http://dx.doi.org/10.21236/ada616757.

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Nochetto, Horacio C., Nicholas R. Jankowski, Brian Morgan, and Avram Bar-Cohen. A Hybrid Multi-gate Model of a Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) Device Incorporating GaN-substrate Thermal Boundary Resistance. Fort Belvoir, VA: Defense Technical Information Center, October 2012. http://dx.doi.org/10.21236/ada570599.

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Boutros, Karim. Investigation of Lattice and Thermal Stress in GaN/A1GaN Field-Effect Transistors. Fort Belvoir, VA: Defense Technical Information Center, October 2006. http://dx.doi.org/10.21236/ada456241.

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Boutros, Karim. Investigation of Lattice and Thermal Stress in GaN/AlGaN Field-Effect Transistors. Fort Belvoir, VA: Defense Technical Information Center, May 2007. http://dx.doi.org/10.21236/ada467566.

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Heller, Eric R., Donald Dorsey, Jason P. Jones, Samuel Graham, Matthew R. Rosenberger, William P. King, and Rama Vetury. Electro-Thermo-Mechanical Transient Modeling of Stress Development in AlGaN/GaN High Electron Mobility Transistors (HEMTs) (Postprint). Fort Belvoir, VA: Defense Technical Information Center, February 2014. http://dx.doi.org/10.21236/ada614007.

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