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Zhou, Lixin. "Testability Design and Testability Analysis of a Cube Calculus Machine." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4911.
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Cube Calculus is an algebraic model popular used to process and minimize Boolean functions. Cube Calculus operations are widely used in logic optimization, logic synthesis, computer image processing and recognition, machine learning, and other newly developing applications which require massive logic operations. Cube calculus operations can be implemented on conventional general-purpose computers by using the appropriate "model" and software which manipulates this model. The price that we pay for this software based approach is severe speed degradation which has made the implementation of several high-level formal systems impractical. A cube calculus machine which has a special data path designed to execute multiplevalued input, and multiple-valued output cube calculus operations is presented in this thesis. This cube calculus machine can execute cube calculus operations 10-25 times faster than the software approach. For the purpose of ensuring the manufacturing testability of the cube calculus machine, emphasize has been put on the testability design of the cube calculus machine. Testability design and testability analysis of the iterative logic unit of the cube calculus machine was accomplished. Testability design and testability analysis methods of the cube calculus machine are weli discussed in this thesis. Full-scan testability design method was used in the testability design and analysis. Using the single stuck-at fault model, a 98.30% test coverage of the cube calculus machine was achieved. A Povel testability design and testability analysis approach is also presented in this thesis.
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Rabhi, Issam. "Testabilité des services Web." Phd thesis, Université Blaise Pascal - Clermont-Ferrand II, 2012. http://tel.archives-ouvertes.fr/tel-00738936.
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Cette thèse s'est attaquée sous diverses formes au test automatique des services Web : une première partie est consacrée au test fonctionnel à travers le test de robustesse. La seconde partie étend les travaux précédents pour le test de propriétés non fonctionnelles, telles que les propriétés de testabilité et de sécurité. Nous avons abordé ces problématiques à la fois d'un point de vue théorique et pratique. Nous avons pour cela proposé une nouvelle méthode de test automatique de robustesse des services Web non composés, à savoir les services Web persistants (stateful) et ceux non persistants. Cette méthode consiste à évaluer la robustesse d'un service Web par rapport aux opérations déclarées dans sa description WSDL, en examinant les réponses reçues lorsque ces opérations sont invoquées avec des aléas et en prenant en compte l'environnement SOAP. Les services Web persistants sont modélisés grâce aux systèmes symboliques. Notre méthode de test de robustesse dédiée aux services Web persistants consiste à compléter la spécification du service Web afin de décrire l'ensemble des comportements corrects et incorrects. Puis, en utilisant cette spécification complétée, les services Web sont testés en y intégrant des aléas. Un verdict est ensuite rendu. Nous avons aussi réalisé une étude sur la testabilité des services Web composés avec le langage BPEL. Nous avons décrit précisément les problèmes liés à l'observabilité qui réduisent la faisabilité du test de services Web. Par conséquent, nous avons évalué des facteurs de la testabilité et proposé des solutions afin d'améliorer cette dernière. Pour cela, nous avons proposé une approche permettant, en premier lieu, de transformer la spécification ABPEL en STS. Cette transformation consiste à convertir successivement et de façon récursive chaque activité structurée en un graphe de sous-activités. Ensuite, nous avons proposé des algorithmes d'améliorations permettant de réduire ces problèmes de testabilité. Finalement, nous avons présenté une méthode de test de sécurité des services Web persistants. Cette dernière consiste à évaluer quelques propriétés de sécurité, tel que l'authentification, l'autorisation et la disponibilité, grâce à un ensemble de règles. Ces règles ont été crée, avec le langage formel Nomad. Cette méthodologie de test consiste d'abord à transformer ces règles en objectifs de test en se basant sur la description WSDL, ensuite à compléter, en parallèle, la spécification du service Web persistant et enfin à effectuer le produit synchronisé afin de générer les cas de test.
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Karel, Amit. "Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability." Thesis, Montpellier, 2017. http://www.theses.fr/2017MONTS084/document.
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Deux innovations en matière de procédés technologiques des semi-conducteurs sont des alternatives à la technologie traditionnelle des transistors MOS (« Metal-Oxide-Semiconductor ») « Bulk » planaires : d’une part le silicium totalement déserté sur isolant (FDSOI – « Fully Depleted Silicon on Insulator ») et d’autre part les transistors à effet de champ à aileron (FinFET – « Fin Field Effect Transistor »). En effet, alors que la technologie « Bulk » arrive à ses limites de miniaturisation des composants et systèmes, notamment du fait de l’effet de canal court, ces deux technologies présentent des propriétés prometteuses pour poursuivre cette réduction des dimensions, grâce à un meilleur contrôle électrostatique de la grille sur le canal du transistor. La technologie FDSOI est, comme l’historique « Bulk », une technologie MOS planaire, ce qui la place naturellement davantage dans la continuité technologique que les ailerons verticaux des transistors FinFETs. La compétition entre ces deux technologies est rude et de nombreuses études publiées dans la littérature comparent ces technologies en termes de performance en vitesse de fonctionnement, de consommation, de coût, etc. Néanmoins, aucune étude ne s’était encore penchée sur leurs propriétés respectives en termes de testabilité ; pourtant l’impact de défauts sur les circuits réalisés en technologies FDSOI et FinFET est susceptible d’être significativement de celui induit par des défauts similaires sur des circuits planaires MOS.Le travail présenté dans cette thèse se concentre sur la conception de circuits d’étude similaires dans chacune des trois technologies et l’analyse comparative de leur comportement électrique sous l’effet d’un même défaut. Les défauts considérés dans notre étude sont les courts-circuits résistifs inter-portes, court-circuit résistif à la masse (GND), court-circuit résistif à l’alimentation (VDD), et circuits ouverts résistifs. La détectabilité des défauts est évaluée pour le test logique statique et le test dynamique en « délai ». Des simulations HSPICE et Cadence SPECTRE ont été effectuées en faisant varier la valeur de la résistance du défaut et le concept de résistance critique est utilisé afin de comparer la plage de détectabilité du défaut dans les différentes technologies. Les conditions optimales de polarisation du substrat (« body-biasing »), de tension d’alimentation et de température en vue d’obtenir la meilleure couverture de défauts possible sont déterminées pour chaque type de défaut. Un modèle analytique, basé sur la résistance équivalente des réseaux de transistors N et P actifs (« ON-resistance »), est proposé pour les courts-circuits résistifs, et permet d’évaluer la valeur de la résistance critique sans effectuer de simulation de fautes. Les propriétés en termes de testabilité sont également établies en tenant compte des variations de procédés, par des simulations Monte-Carlo réalisées aussi bien pour les dispositifs à tension de seuil nominale (« Regular-VT devices » : FDSOI-RVT et Bulk-LR) que pour les dispositifs à tension de seuil basse (« Low-VT devices » : FDSOI-LVT et Bulk-LL) disponibles pour les technologies 28 nm Bulk et FDSOIFully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are new innovations in silicon process technologies that are likely alternatives to traditional planar Bulk transistors due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit.The work of this thesis is focused on implementing similar design in each technology and comparing the electrical behavior of the circuit with the same defect. The defects that are considered for our investigation are inter-gate resistive bridging, resistive short to ground terminal (GND), resistive short to power supply (VDD) and resistive open defects. Defect detectability is evaluated in the context of either logic or delay based test. HSPICE and Cadence SPECTRE simulations are performed varying the value of the defect resistance and the concept of critical resistance is used to compare the defect detectability range in different technologies. The optimal body-biasing, supply voltage and temperature settings to achieve the maximum defect coverage are determined for these defect types. An analytical analysis is proposed for short defects based on the ON-resistance of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. Testability properties are also established under the presence of process variations based on Monte-Carlo simulations for both Regular-VT devices (FDSOI-RVT and Bulk-LR) and Low-VT devices (FDSOI-LVT and Bulk-LL) available for 28nm Bulk and FDSOI technologies
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Lindström, Birgitta. "Methods for Increasing Software Testability." Thesis, University of Skövde, Department of Computer Science, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-494.
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We present a survey over current methods for improving software testability. It is a well-known fact that the cost for testing of software takes 50\% or more of the development costs. Hence, methods to improve testability, i.e. reduce the effort required for testing, have a potential to decrease the development costs. The test effort needed to reach a level of sufficient confidence for the system is dependent on the number of possible test cases, i.e., the number of possible combinations of system state and event sequences. Each such combination results in an execution order. Properties of the execution environment that affect the number of possible execution orders can therefore also affect testability. Which execution orders that are possible and not are dependent of processor scheduling and concurrency control policies. Current methods for improving testability are investigated and their properties with respect to processor scheduling and concurrency control analyzed. Especially, their impact on the number of possible test cases is discussed. The survey revealed that (i) there are few methods which explicitly address testability, and (ii) methods that concern the execution environment suggest a time-triggered design. It is previously shown that the effort to test an event-triggered real-time system is inherently higher than testing a time-triggered real-time system. Due to the dynamic nature of the event-triggered system the number of possible execution orders is high. A time-triggered design is, however, not always suitable. The survey reveals an open research area for methods concerning improvement of testability in event-triggered systems. Moreover, a survey and analysis of processor scheduling and concurrency control properties and their effect on testability is presented. Methods are classified into different categories that are shown to separate software into different levels of testability. These categories can form a basis of taxonomy for testability. Such taxonomy has a potential to be used by system designers and enable them to perform informed trade-off decisions.
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Shi, Cheng. "High-level design for testability." Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.336135.
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Bhattacharyya, Arnab. "Testability of linear-invariant properties." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68435.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 75-80).
Property Testing is the study of super-efficient algorithms that solve "approximate decision problems" with high probability. More precisely, given a property P, a testing algorithm for P is a randomized algorithm that makes a small number of queries into its input and distinguishes between whether the input satisfies P or whether the input is "far" from satisfying P, where "farness" of an object from P is measured by the minimum fraction of places in its representation that needs to be modified in order for it to satisfy P. Property testing and ideas arising from it have had significant impact on complexity theory, pseudorandomness, coding theory, computational learning theory, and extremal combinatorics. In the history of the area, a particularly important role has been played by linearinvariant properties, i.e., properties of Boolean functions on the hypercube which are closed under linear transformations of the domain. Examples of such properties include linearity, homogeneousness, Reed-Muller codes, and Fourier sparsity. In this thesis, we describe a framework that can lead to a unified analysis of the testability of all linear-invariant properties, drawing on techniques from additive combinatorics and from graph theory. We also show the first nontrivial lowerbound for the query complexity of a natural testable linear-invariant property.
by Arnab Bhattacharyya.
Ph.D.
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Hock, Joel M. (Joel Michael) 1977. "Exposing testability in GUI objects." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86608.
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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (leaf 28).
by Joel M. Hock.
M.Eng.and S.B.
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Malla, Prakash, and Bhupendra Gurung. "Adaptation of Software Testability Concept for Test Suite Generation : A systematic review." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4322.
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Context: Software testability, which is the degree to which a software artifact facilitates process of testing, is not only the indication of the test process effectiveness but also gives the new perspective on code development. Since more than fifty percent of total software development costs is related to testing process activities, Software testability has always been the improving area in software domain so that we can make the software development process effective with respect to test cases writing and fault detection process. Objectives: The research though this thesis will have the objective of proposing a conceptual framework considering the testability issues for the simpler test suite generation and facilitating the concerned persons with better effectiveness of testing. We investigate the testability factors and testability metrics basically with the help of the systematic literature review and the proposed framework’s feasibility is evaluated with case study. Methods: Initially, we conduct the literature review to get broad knowledge on this domain as well for the key documents. Then study starts with the systematic literature review process guided by the review protocol to collect the testability factors and measurements. The framework is validated with the case study. The research documents are included from highly trusted e-database including Compendex, Inspec, IEEE Xplore, ACM Digital Library, Springer Link and Scopus. Altogether 36 primary documents are included for the study and results are extracted. Results: From the results of systematic literature review, Software testability factors and associated measurements are found and the construction of framework for simple test generation as guidelines evaluate with case study. To make the test suite generation simpler, we propped a framework based on the FTA concepts and breakdown of high level testability factors to its simpler form of measureable level. Conclusions: Numbers of different software testability factors are presented in different researches in different perspectives. We collect important testability factors and associated measurement methods and we concluded the effect of testability in simpler test suite generation with the help of framework evaluated by case study.
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Kito, Nobutaka, and Naofumi Takagi. "Level-Testability of Multi-operand Adders." IEEE, 2008. http://hdl.handle.net/2237/12025.
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Lindström, Birgitta. "Testability of Dynamic Real-Time Systems." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16486.
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This dissertation concerns testability of event-triggered real-time systems. Real-time systems are known to be hard to test because they are required to function correct both with respect to what the system does and when it does it. An event-triggered real-time system is directly controlled by the events that occur in the environment, as opposed to a time-triggered system, which behavior with respect to when the system does something is constrained, and therefore more predictable. The focus in this dissertation is the behavior in the time domain and it is shown how testability is affected by some factors when the system is tested for timeliness. This dissertation presents a survey of research that focuses on software testability and testability of real-time systems. The survey motivates both the view of testability taken in this dissertation and the metric that is chosen to measure testability in an experiment. We define a method to generate sets of traces from a model by using a meta algorithm on top of a model checker. Defining such a method is a necessary step to perform the experiment. However, the trace sets generated by this method can also be used by test strategies that are based on orderings, for example execution orders. An experimental study is presented in detail. The experiment investigates how testability of an event-triggered real-time system is affected by some constraining properties of the execution environment. The experiment investigates the effect on testability from three different constraints regarding preemptions, observations and process instances. All of these constraints were claimed in previous work to be significant factors for the level of testability. Our results support the claim for the first two of the constraints while the third constraint shows no impact on the level of testability. Finally, this dissertation discusses the effect on the event-triggered semantics when the constraints are applied on the execution environment. The result from this discussion is that the first two constraints do not change the semantics while the third one does. This result indicates that a constraint on the number of process instances might be less useful for some event-triggered real-time systems.
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Yu, Hua-Long. "Testability-directed specification of communications software." Thesis, University of Ottawa (Canada), 1992. http://hdl.handle.net/10393/7560.
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In this thesis, we make a contribution to improving software testability by providing a useful model and guide-lines for constructing highly testable specifications of distributed real time (communications) systems. A global events model is developed based on relative clock for interpreting concurrent aspect of a communications system. Extended trace assertion language (ETAL) is presented for formally representing both the sequential and concurrent aspects of the system. A relative clock based specification in ETAL method also facilitates subsequent testing activity. Subsequently, based on the global events model, a new test result analysis approach including timing information is presented for communication service and protocol conformance testing. This approach is also ETAL specification-based. After the descriptions of the contributions mentioned above, the definition of a testability-directed specification and a study on the relations between the testability-directed specification and ETAL are then presented. Finally, the feasibility and usefulness of the relative clock based formal specification method is demonstrated by its application to OSI transport software (service and protocol). Also, the effectiveness of the relative clock based approach for test result analysis is illustrated in a set of realistic conformance testing examples. (Abstract shortened by UMI.)
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Kumar, Mahilchi Milir Vaseekar. "Testability considerations in delay fault testing /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1232421401&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Al-Khanjari, Zuhoor Abdullah. "Investigations into testability and related concepts." Thesis, University of Liverpool, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.366661.
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Park, Byung-Goo. "A system-level testability allocation model /." free to MU campus, to others for purchase, 1997. http://wwwlib.umi.com/cr/mo/fullcit?p9842588.
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El, belghiti alaoui Nabil. "Stratégie de testabilité en production des cartes électroniques à forte densité d’intégration et à signaux rapides." Thesis, Toulouse, INSA, 2020. http://www.theses.fr/2020ISAT0018.
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Les étapes de test en production sont basées à ce jour sur des contrôles optiques (AOI), inspection des joints de soudures par Rayons-X (AXI), électriques (ICT) et tests fonctionnels. Face à la multiplication et à la miniaturisation des composants, la cohabitation de plusieurs technologies (numérique, analogique, radiofréquence, puissance…) sur le même PCB (Printed Circuit Board), les moyens de test listés précédemment ne sont plus suffisants pour répondre complètement aux exigences de couverture de tests en production, car peu performants et coûteux en temps de développement et de cycle de test.L'objectif de cette thèse CIFRE avec ACTIA Automotive en collaboration avec le laboratoire LAAS-CNRS est de définir une stratégie de test en production innovante et adaptée aux produits à forte densité en envisageant dans un premier temps toutes les techniques existantes ou à développer. Pour ce faire, nous avons abordé dans cette thèse, des améliorations à apporter aux méthodologies de test existantes et proposé également des approches de test utilisables en amont de la production des PCBAs (Printed Circuit Board Assemblies) à haute densité et à signaux rapides.Premièrement, nous avons introduit une nouvelle technique sans contact pour tester des PCBAs lorsque l’accès physique de test est très limité. La technique consiste à utiliser des sondes de champ magnétique proche, qui détectent la distribution de champ magnétique émanant de certains composants montés sur le PCB dans le but de tester leur présence sur la carte et leur valeur par la suite. Deuxièmement, une approche de test utilisant des signatures thermiques infrarouges est présentée. Cette technique peut détecter les défauts d’assemblage du composant tel que sa présence, sa valeur et dans certain cas son état de santé, ce qui permet de conclure sur l’état de défaut du PCBA. Afin d’évaluer la pertinence de ces deux techniques, plusieurs scénarios de défaut ont été considérés et analysés avec un algorithme de détection de valeurs aberrantes. Sur plusieurs cas, les défauts de fabrication sont discriminés avec des marges importantes, tout en tenant compte de la variabilité de spécification des composants.Finalement, une technique pour regagner de l’accessibilité de test sur des pistes de transmission de signal de haute fréquence est présentée. La technique consiste à utiliser de petites ouvertures dans le masque de soudure directement au-dessus des pistes portant des signaux digitaux. Les conducteurs exposés sont mis en contact avec une sonde à bout déformable, conducteur et anisotrope. La faisabilité industrielle de cette technique a été testée sur un prototype que nous avions développé en collaboration avec la filiale d’ACTIA Group : ACTIA Engineering ServicesUntil today, the production tests are based mainly on optical verification (AOI), X-ray inspection (AXI), electrical (ICT) and functional tests. Faced with the miniaturization of component packages, the high densification and integration of several technologies (digital, analog, radio frequency, power ...) on the same PCB (Printed Circuit Board), the test techniques listed above are no longer sufficient to fully meet the production test coverage requirements, because they are costly in terms of development time and test cycle and are not very efficient.The objective of this CIFRE thesis with ACTIA Automotive in collaboration with LAAS-CNRS is to define an innovative production test strategy adapted to high-density products. To do this, we have addressed in this work, improvements to existing test methodologies and proposed test approaches usable upstream of the production process of PCBAs (Printed Circuit Board Assemblies).First, we introduced a new contactless technique for testing PCBAs with limited physical test access. The technique involves the use of near-field magnetic sensors, which detect the magnetic signatures from components mounted on the PCB in order to test their presence and their value thereafter. Secondly, a test approach using infrared thermal signatures is presented. This technique can detect component assembly defects such as, presence, value and in some cases its state of health, which allows concluding on the PCBA state of defect. In order to evaluate the relevance of these two techniques, several fault scenarios were considered and analyzed with an outlier detection algorithm. In several cases, the manufacturing defects are discriminated with significant margins, while taking into account the variability in component specifications.Finally, a technique for regaining test accessibility on high frequency signal transmission tracks is presented. The technique uses small openings in the solder mask directly above the tracks carrying digital signals. The exposed conductors are contacted with a probe with deformable and anisotropic conductive tip. The industrial feasibility of this technique was tested on a prototype that we developed in collaboration with the ACTIA Group subsidiary: ACTIA Engineering Services
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Li, Lin. "RF transceiver front-end design for testability." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2256.
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In this thesis, we analyze the performance of a loop-back built-in-self-test for a RF transceiver front-end. The tests aim at spot defects in a transceiver front-end and they make use of RF specifications such as NF (Noise Figure), G (power gain) and IIP3 (third order Intercept point). To enhance fault detectability, RF signal path sensitization is introduced. We use a functional RF transceiver model that is implemented in MatLab™ to verify this analysis.
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Gross, Hans-Gerhard. "Measuring evolutionary testability of real-time software." Thesis, University of South Wales, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.365087.
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Oikonomakos, Petros. "High-level synthesis for on-line testability." Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.414359.
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Bastos, Antonio Josefran de Oliveira. "Convergent Sequences of Discrete Structures and Testability." Universidade Federal do CearÃ, 2012. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=7654.
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FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgicoIn this work, we studied the recent theory of convergent graph sequences and its extensions to permutation and partially ordered sets with fix dimension. Weâve conjectured a lemma of weak regularity on intervals that, if this conjecture is true, we can extend this theory to ordered graphs, which are graphs such that there is a total order on its vertices. We show some interesting relations on permutation and partially ordered sets with ordered graphs. Then, we obtain another proof to the existence of limit objects for all convergent permutation sequences. We also proved that all hereditary property of either permutation or ordered graph is testable.
Neste trabalho, estudamos a teoria recente de convergÃncia de sequÃncias de grafos e suas extensÃes para permutaÃÃes e ordens parciais de dimensÃo fixa. Conjecturamos um lema de regularidade fraca de grafos em intervalos que, se for verdadeira, nos possibilita estender essa teoria para grafos ordenados, que sÃo grafos tais que existe uma ordem total entre os vÃrtices. Mostramos algumas relaÃÃes interessantes de permutaÃÃes e ordens parciais com grafos ordenados. Com isso, conseguimos uma prova alternativa para a existÃncia de objetos limites de qualquer sequÃncia convergente de permutaÃÃes. Provamos tambÃm que toda propriedade hereditÃria de permutaÃÃes ou grafos ordenados à testÃvel.
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Larsson, Erik. "An Integrated System-Level Design for Testability Methodology." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4932.
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HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design. The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources. Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system. Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.
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Boubezari, Samir. "Analyse de testabilité au niveau transfert de registres." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0011/NQ38717.pdf.
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Elbably, M. E. "On the testability and diagnosability of digital systems." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.380169.
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Roberts, M. W. "Logic circuit testability for reconvergent fan-out nodes." Thesis, University of York, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.374197.
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Almajdoub, Salahuddin A. "A Design Methodology for Physical Design for Testability." Diss., Virginia Tech, 1996. http://hdl.handle.net/10919/30574.
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Physical design for testability (PDFT) is a strategy to design circuits in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in complementary metal-oxide-semiconductor (CMOS) circuits. To compare faults, the design process utilizes a new parameter called the fault index. The fault index for a particular fault is the probability of occurrence of the fault divided by the testability of the fault. Faults with the highest fault indices are considered the worst faults and are targeted by the PDFT design process to eliminate them or reduce their probability of occurrence.
An implementation of the PDFT design process is constructed using several new tools in addition to other "off-the-shelf" tools. The first tool developed in this work is a testability measure tool for bridging faults. Two other tools are developed to eliminate or reduce the probability of occurrence of bridging faults with high fault indices. The row enhancer targets faults inside the logic elements of the circuit, while the channel enhancer targets faults inside the routing part of the circuit.
To demonstrate the capabilities and test the eff ectiveness of the PDFT design process, this work conducts an experiment which includes designing three CMOS circuits from the ISCAS 1985 benchmark circuits. Several layouts are generated for every circuit. Every layout, except the rst one, utilizes information from the previous layout to minimize the probability of occurrence for faults with high fault indices. Experimental results show that the PDFT design process successfully achieves two goals of PDFT, providing layouts with fewer faults and minimizing the probability of occurrence of hard-to-test faults. Improvement in the total fault index was about 40 percent in some cases, while improvement in total critical area was about 30 percent in some cases. However, virtually all the improvements came from using the row enhancer; the channel enhancer provided only marginal improvements.Ph. D.
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Dammak, Abdelaziz. "Étude de mesures de testabilité de systèmes logiques." Paris 11, 1985. http://www.theses.fr/1985PA112123.
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Ce mémoire est consacré à l'étude de mesures de testabilité de systèmes logiques et à l'introduction de ces mesures dans un outil de génération de programmes de test. Un état de l'art sur la testabilité est fait, ainsi qu'une analyse critique des principaux programmes opérationnels : TMEAS, CAMELOT et SCOAP. Une description d'un système opérationnel d'aide à la spécification automatique de programmes de test : CATA, est donnée. Nous formalisons des mesures de contrôlabilité, observabilité et testabilité. Puis nous nous intéressons à la détermination d'une stratégie de test, définissant un ensemble minimal et ordonné d'écoulements permettant le test complet d'un système, au vu des mesures définiesThis report deals with the study of testability measures for logic systems and the introduction of these measures in a test programs generation tool. A general presentation of the testability concepts and a critical analysis of the main operational programs : TMEAS, CAMELOT and SCOAP, have been performed. A description of a Computer Aided Test Analysis system, CATA is given. We formalize controllability, observability and testability measures. Then we intent to determine a test strategy which defines a minimum, ordered set of flows allowing the full test of a system with respect to those measures
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PELLEGRINELLI, JEAN-LUC. "Testabilite de systemes a base de circuits vlsi." Paris 6, 1990. http://www.theses.fr/1990PA066266.
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Un probleme difficile a resoudre est celui de savoir quelle quantite de test sera necessaire pour un produit et quel degre de confiance nous pouvons lui accorder pour considerer que le resultat de la conception sera un modele testable. Il existe plusieurs methodes d'integration de la testabilite et la premiere partie du document dresse un panorama de ces techniques en presentant leurs avantages et inconvenients respectifs; ces methodes sont d'abord appliquees aux circuits vlsi puis aux cartes et systemes a base de circuits vlsi. La seconde partie du document comporte trois exemples d'application qui ont permis de valider les principes developpes au cours de la premiere partie: 1) le premier exemple est un circuit de faible complexite dans lequel sont integrees des methodes de testabilite ad hoc, 2) le deuxieme exemple est un microcontroleur 16 bits qui comporte une structure de diagnostic integre, 3) le troisieme exemple est un systeme a base de circuits vlsi qui integre une structure de bus de testabilite et une strategie de test hierarchique
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Albattah, Waleed. "SOFTWARE MAINTAINABILITY AND TESTABILITY PREDICTIONS USING PACKAGE COHESION." Kent State University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=kent1415737576.
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Das, Debaleena. "Design-for-testability techniques for deep submicron technology /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
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Sarabi, Andisheh. "Logic Synthesis with High Testability for Cellular Arrays." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4752.
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The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.
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Provost, Julien. "Test de conformité de contrôleurs logiques spécifiés en grafcet." Thesis, Cachan, Ecole normale supérieure, 2011. http://www.theses.fr/2011DENS0029/document.
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Les travaux présentés dans ce mémoire de thèse s'intéressent à la génération et à la mise en œuvre de séquences de test pour le test de conformité de contrôleurs logiques. Dans le cadre de ces travaux, le Grafcet (IEC 60848 (2002)), langage de spécification graphique utilisé dans un contexte industriel, a été retenu comme modèle de spécification. Les contrôleurs logiques principalement considérés dans ces travaux sont les automates programmables industriels (API). Afin de valider la mise en œuvre du test de conformité pour des systèmes de contrôle/commande critiques, les travaux présentés proposent: - Une formalisation du langage de spécification Grafcet. En effet, l'application des méthodes usuelles de vérification et de validation nécessitent la connaissance du comportement à partir de modèles formels. Cependant, dans un contexte industriel, les modèles utilisés pour la description des spécifications fonctionnelles sont choisis en fonction de leur pouvoir d'expression et de leur facilité d'utilisation, mais ne disposent que rarement d'une sémantique formelle. - Une étude de la mise en œuvre de séquences de test et l'analyse des verdicts obtenus lors du changement simultané de plusieurs entrées logiques. Une campagne d'expérimentation a permis de quantifier, pour différentes configurations de l'implantation, le taux de verdicts erronés dus à ces changements simultanés. - Une définition du critère de SIC-testabilité d'une implantation. Ce critère, déterminé à partir de la spécification Grafcet, définit l'aptitude d'une implantation à être testée sans erreur de verdict. La génération automatique de séquences de test minimisant le risque de verdict erroné est ensuite étudiéeThe works presented in this PhD thesis deal with the generation and implementation of test sequences for conformance test of logic controllers. Within these works, Grafcet (IEC 60848 (2002)), graphical specification language used in industry, has been selected as the specification model. Logic controllers mainly considered in these works are Programmable Logic Controllers (PLC). In order to validate the carrying out of conformance test of critical control systems, this thesis presents: - A formalization of the Grafcet specification language. Indeed, to apply usual verification and validation methods, the behavior is required to be expressed through formal models. However, in industry, the models used to describe functional specifications are chosen for their expression power and usability, but these models rarely have a formal semantics. - A study of test sequences execution and analysis of obtained verdicts when several logical inputs are changed simultaneously. Series of experimentation have permitted to quantify, for different configurations of the implantation under test, the rate of erroneous verdicts due to these simultaneous changes. - A definition of the SIC-testability criterion for an implantation. This criterion, determined on the Grafect specification defines the ability of an implementation to be tested without any erroneous verdict. Automatic generation of test sequences that minimize the risk of erroneous verdict is then studied
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Taylor, David. "Design of certain silicon semi-customised structures incorporating self-test." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329218.
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Lewis, Dean Leon. "Design for pre-bond testability in 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45756.
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In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.
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El-Maleh, Aiman H. "Testability preservation of combinational and sequential logic synthesis transformations." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29016.
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In order to reduce the test development cost and guarantee testable designs, it is essential to have synthesis transformations that are testability and test-set preserving. In this thesis, we study testability preservation of transformations that form the basis of existing state-of-the-art logic synthesis and optimization techniques.We show that the concurrent decomposition and factorization transformations, except dual-extraction of multiplexor structures, preserve testablility and test-set under several testing constraints. Furthermore, we provide sufficient conditions for test-set preservation under the algebraic resubstitution with complement transformation that cover a larger class of complementary expressions than was known previously. Experimental results show that dual-extraction of multiplexor structures is utilized in only 2 out of 50 benchmark circuits. We demonstrate that while disabling this transformation has negligible effect on area, it results in an efficient test-set preserving multilevel logic synthesis algorithm.
Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault efficiency attained. We show that retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a pre-determined number of arbitrary input vectors. Furthermore, we show that a new circuit attribute, termed density of encoding, is the main reason for high test generation time. We also propose a novel approach for reducing test pattern generation cost based on test-set preserving transformations. Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.
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Miles, J. R. "Cost modelling for VLSI circuit conversion to aid testability." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383718.
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Prepin, Valérie. "Test aléatoire de circuits combinatoires : nouvelle mesure de testabilité." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0091.
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Le test aleatoire a pour objet de detecter si un circuit est defectueux. Il consiste a envoyer une sequence aleatoire de signaux en entree du circuit et a observer la reponse en sortie. En general, on desire que le test permette de detecter une proportion de fautes donnee, parmi l'ensemble des fautes considerees pouvant affecter le circuit (une faute est un modele de defaut). Cette proportion est appelee couverture de fautes. On doit alors evaluer la longueur l de la sequence a appliquer au circuit pour obtenir cette couverture de fautes desiree. L'evaluation de l depend de la testabilite du circuit qui peut etre representee par un ensemble de parametres permettant de caracteriser le circuit. Dans la litterature, plusieurs caracterisations de la testabilite sont decrites, mais aucune ne convient reellement. Nous les avons classees en deux categories : les mesures vectorielles qui necessitent la connaissance de beaucoup de donnees, et les mesures a 1, 2 ou 4 parametres qui permettent une estimation tres imprecise de la longueur de test requise. L'objectif de cette these est de proposer une nouvelle caracterisation de la testabilite des circuits combinatoires afin d'obtenir une evaluation convenable, en termes de cout et de precision, de la longueur de test en fonction de la couverture de fautes souhaitee. Nous proposons de caracteriser le circuit par deux parametres dont nous montrons la pertinence. Puis, nous evaluons ces parametres a partir de donnees obtenues lors d'une simulation relativement courte de longueur. Les 2 parametres permettent alors d'estimer la longueur requise pour obtenir une couverture de fautes proche de 1 (l > ). Nous avons applique cette demarche a des circuits combinatoires de reference. Sans etre precis (ce qui est impossible), les resultats sont bien meilleurs que ceux obtenus par les methodes precedentes.
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Rahagude, Nikhil Prakash. "Integrated Enhancement of Testability and Diagnosability for Digital Circuits." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/35609.
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While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish currently indistinguishable fault-pairs. We achieve this by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, we propose a novel low-cost metric to identify such TD points. Further, we propose a new DFT + DFD architecture, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. Our experiments indicate that the proposed architecture can distinguish 4x more previously indistinguishable fault-pairs than existing DFT architectures while maintaining similar fault coverages. Further, the experiments illustrate that quality results can be achieved with an area overhead of around 5%. Additional experiments conducted on hard-to-test circuits show an increase in fault coverage by 48% while maintaining similar diagnostic resolution.
Built-in Self Test (BIST) is a technique of adding additional blocks of hardware to the circuits to allow them to perform self-testing. This enables the circuits to test themselves thereby reducing the dependency on the expensive external automated test equipment (ATE). At the end of a test session, BIST generates a signature which is a compaction of the obtained output responses of the circuit for that session. Comparison of this signature with the reference signature categorizes the circuit as error free or buggy. While BIST provides a quick and low cost alternative to check circuit's correctness, diagnosis in BIST environment remains poor because of the limited information present in the lossily compacted final signature. The signature does not give any information about the possible defect location in the circuit. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories,response memory to store reference responses and fail memory to store failing responses. We propose a novel architecture in which only one additional memory is required. Experimental results conducted on benchmark circuits substantiate that the same fault coverage can be maintained using just 5% of the available test vectors. This reduces the size of memory required to store responses which in turn reduces area overhead. Further, by adding test points to the circuit using our proposed architecture, we can improve the diagnostic resolution by 60% with respect to external testing.Master of Science
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Donglikar, Swapneel B. "Design for Testability Techniques to Optimize VLSI Test Cost." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/43712.
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High test data volume and long test application time are two major concerns for testing
scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective
in addressing both these issues. The ILS achieves a high degree of test data compression
thereby reducing both the test data volume and test application time. The degree of test
data volume reduction depends on the fault coverage achievable in the broadcast mode.
However, the fault coverage achieved in the broadcast mode of ILS architecture depends
on the actual configuration of individual scan chains, i.e., the number of chains and the
mapping of the individual flip-flops of the circuit to the respective scan chain positions.
Current methods for constructing scan chains in ILS are either ad-hoc or use test pattern
information from an a-priori automatic test pattern generation (ATPG) run. In this thesis,
we present novel low cost techniques to construct ILS scan configuration for a given design.
These techniques efficiently utilize the circuit topology information and try to optimize the
flip-flop assignment to a scan chain location without much compromise in the fault coverage
in the broadcast mode. Thus, they eliminate the need of an a-priori ATPG run or any
test set information. In addition, we also propose a new scan architecture which combines
the broadcast mode of ILS and Random Access Scan architecture to enable further test
volume reduction on and above effectively configured conventional ILS architecture using
the aforementioned heuristics with reasonable area overhead. Experimental results on the
ISCASâ 89 benchmark circuits show that the proposed ILS configuration methods can achieve
on an average 5% more fault coverage in the broadcast mode and on average 15% more test
data volume and test application time reduction than existing methods. The proposed new
architecture achieves, on an average, 9% and 33% additional test data volume and test
application time reduction respectively on top of our proposed ILS configuration heuristics.Master of Science
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Nguyen, Thanh Binh. "Contribution à l'analyse de testabilité de systèmes réactifs synchrones." Grenoble INPG, 2004. http://www.theses.fr/2004INPG0023.
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Cette thèse porte sur l'étude de la testabilité des systèmes réactifs, développés selon une approche flot de données synchrone. L'environnement de développement plus particulièrement étudié est l'environnement GALA utilisé par la société THALES Avionics pour développer des logiciels avioniques et spatiaux. L'objectif de l'analyse de testabilité est de prévoir et de mesurer la difficulté du test durant le développement du système. Une telle analyse permet également de guider les concepteurs et développeurs pour obtenir un système plus testable: le système doit être testé plus efficacement à moindre coût. Nous proposons l'intégration de l'analyse de testabilité dans le processus de développement du logiciel, cette analyse de testabilité pouvant s'effectuer à plusieurs niveaux: de la spécification au codage. Nous avons d'abord étudié l'analyse de testabilité des spécifications de type flot de données. Ensuite, nous nous sommes intéressés à l'analyse de testabilité du code, qui est implémenté par des langages impératifs, comme le langage C. Ceci nécessite l'utilisation de la forme SSA (Single Static Assignment) afin de transformer le code impératif sous une forme flot de données. Nous avons ainsi implémenté un traducteur permettant de générer automatiquement le modèle de testabilité à partir du code C. Enfin, concernant l'aide à la spécification des objectifs de test, nous avons proposé une amélioration des stratégies de test définies dans la technologie SATAN, en prenant en compte des caractéristiques d'impact sur le processus de test, comme les mesures d'accessibilité et les sorties critiques.
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Vial, Julien. "Test et testabilité de structures numériques tolérantes aux fautes." Montpellier 2, 2009. http://www.theses.fr/2009MON20254.
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Les technologies submicroniques permettent aujourd'hui la réalisation de circuits intégrés regroupant des milliards de transistors sur une même puce. En prenant aussi en compte la miniaturisation croissante des procédés de fabrication et la complexité des nouveaux circuits intégrés (SoC, SiP), il est de plus en plus difficile de réaliser un circuit intégré sans aucun défaut de fabrication. Par conséquent, le rendement de fabrication des circuits diminue et une diminution de plus en plus importante est à craindre pour les prochaines années. Cette tendance est confirmée par l'ITRS (International Technology Roadmap for Semiconductors) [ITR07]. L'objectif de cette thèse est d'étudier la possibilité de réaliser des structures numériques de tolérance aux fautes afin d'augmenter le rendement de fabrication. En effet, bien que ces structures aient été réalisées pour assurer une certaine sureté de fonctionnement lorsque le système est affecté par des fautes apparaissant pendant l'utilisation du circuit, plusieurs d'entre elles ont la capacité de tolérer aussi des défauts de fabrication. Dans ce manuscrit, un état de l'art sur la tolérance aux fautes est réalisé. Puis, une architecture numérique tolérante aux fautes est choisie pour déterminer sa capacité à augmenter le rendement de fabrication. Il s'agit de l'architecture TMR (Triple Modular Redundancy). Une procédure de test permettant d'évaluer sa tolérance aux fautes est décrite. Une amélioration de l'architecture TMR est ensuite proposée. Cette amélioration consiste à partitionner les modules en plusieurs parties indépendantes. Grâce à cela, les architectures TMR sont suffisamment tolérantes aux défauts de fabrication pour pouvoir améliorer le rendement de fabrication. Le dernier chapitre de ce manuscrit concerne l'utilisation d'architectures TMR dans un contexte SoC. Plus le SoC contient de mémoires, plus la réalisation d'architectures TMR permet d'augmenter le rendementThe actual trends of microelectronic are an increasing number of transistors into a single chip, a decreasing transistors dimensions and a complexity of IC manufacturing (SoC or SiP). Due to all these reasons, the yield of manufactured circuits is lower and lower. This is also the prediction of ITRS (International Technology Roadmap for Semiconductors) [ITR07]. The goal of this thesis consists in studying fault tolerant architectures to improve the yield. These architectures have been designed to tolerate transient or temporary faults but they can also tolerate manufacturing defects and thus increase the yield. This report begins with a state of the art of fault tolerance. Next, we have focused on the well-known fault tolerant architecture: the TMR (Triple Modular Redundancy). We have analyzed the ability of this architecture to tolerate manufacturing defects and the conditions to improve the yield. A test procedure has been described to measure the fault tolerance of TMR architecture. With the help of partitioning techniques, TMR architectures can be improved a lot and the realization of these architectures can improve the yield. Finally, TMR architectures have been studied in a SoC context
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Naal, Mouhamad Ayman. "Synthèse de haut niveau pour la testabilité en-ligne." Grenoble INPG, 2002. http://www.theses.fr/2002INPG0082.
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Simeu, Emmanuel. "Test aléatoire : évaluation de la testabilité des circuits combinatoires." Grenoble INPG, 1992. http://www.theses.fr/1992INPG0077.
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Une implementation optimale du test pseudo-aleatoire sur un circuit donne suppose la determination du nombre de vecteurs (longueur de test) necessaires pour garantir un niveau de couverture de faute (qualite de test) souhaite. Cette longueur est fonction non seulement de la qualite de test desiree, mais aussi du profil de detection du circuit sous test (testabilite: mesure de la facilite de tester). Ce travail propose une approche originale du calcul de la probabilite de detection de la faute-la-plus-difficile-a-detecter. Le niveau de description utilise est le niveau boite noire. Chaque faute interne a une boite noire est modelisee par un ensemble caracteristique de configurations d'entrees de cette boite noire. Comme moyen de mise en uvre de ce modele qui reste tres general, deux outils de calcul ont ete developpes: un algorithme numerique de calcul exact permet non seulement le calcul de la probabilite de detection de fautes internes a une boite noire quelconque du circuit, mais aussi la mesure d'une borne inferieure de la testabilite du circuit. Le second outil utilise la simulation et la preuve formelle pour evaluer une estimation statistique de la probabilite de detection de la faute la-plus-difficile-a-detecter. Les resultats obtenus sur les dix circuits combinatoires iscas de benchmark sont presentes. Chacun de ces deux outils fournit un ensemble d'informations suffisamment riches pour permettre une modification des circuits les moins testables afin d'ameliorer leur testabilite
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Rockliff, John E. "The implementation of testability strategies in a VLSI circuit /." Title page, contents and abstract only, 1986. http://web4.library.adelaide.edu.au/theses/09ENS/09ensr683.pdf.
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Survila, Vytautas. "Abstrakčių automatų valdomumo tyrimo programinė įranga." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050527_201609-31343.
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One of possible expenditures of reduction and testability process acceleration choices is to increase circuit’s testability. It means to increase controllability and observability of the circuit. As to determine the circuit’s controllability and observability manually takes lots of time, it is meaningful to automate this process. The main purpose is to determine and improve the controllability of the circuit by offering some suggestions to system on chip’s designers how to improve circuit’s controllability. We try to analyze if it is possible to do this only by using created software. This software’s architecture uses client-server mode and all computations are performed on a server side. The system is realized on Apache server with Linux OS. System modules are realized using C++, PHP, JAVA, HTML and JavaScript programming languages. In this paper it is being introduced the definition of controllability, explored methods of controllability estimation and increase. Also there is introduced the research how to improve accuracy of software results. The methods of the controllability estimation for “white box” are modified to work with “black box”. Assumptions made during the research were validated by experiments.
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Birgisson, Ragnar. "Improving Testability of Applications in Active Real-Time Database Environments." Thesis, University of Skövde, Department of Computer Science, 1998. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-226.
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The test effort required to achieve full test coverage of an event-trigered real-time system is very high. In this dissertation, we investigate a method for reducing this effort by constraining behavior of the system. We focus on system level testing of applications with respect to timeliness. Our approach is to define a model for constraining real-time systems to improve testability. Using this model applicability of our constraints is easily determined because all the pertinent assumptions are clearly stated. We perform a validation of a test effort upper bound for event-triggered real-time systems with respect to this model. Effects that constraints for improving testability have on predictability, efficiency, and scheduling are investigated and validated. Specific design guidelines for selection of appropriate constraint values are presented in this work. Finally, we discuss mechanisms for handling constraint violations.
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Vermaak, Hermanus Jacobus. "Design-for-delay-testability techniques for high-speed digital circuits." Enschede : University of Twente [Host], 2005. http://doc.utwente.nl/57440.
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Jagadeesh, Vasudevamurthy. "On the testability-preserving decomposition and factorization of Boolean expressions." Thesis, McGill University, 1991. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74653.
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This thesis presents a new concurrent method for the decomposition and factorization of Boolean expressions based on two simple objects: two-literal single-cube divisors, and double-cube divisors along with their complements. It is proved that the presence of common multiple-cube algebraic divisors, from a set of Boolean expressions, can be found by analyzing the set of double-cube divisors. It is also shown that in order to find the duality relations that may exist between various objects, only a subset of two-literal single-cube and double-cube divisors needs to be analyzed. Since the number of these objects grows polynomially with the size of the network, the number of objects that are to be analyzed for finding common algebraic divisors, and for finding the duality relations between them, is much less than the set of all algebraic divisors. Also, since the duality relations between these objects are exploited along with DeMorgan's laws, these objects constitute a richer set of divisors than the strictly algebraic divisors.It is also proved that the transformations based on these simple objects preserve testability. This result implies that if the input Boolean network before decomposition and factorization is 100% testable for single stuck-at faults by a test set T, then the area optimized output network will also be 100% testable for single stuck-at faults, and can be tested by the same test set T. These results are proved using the concepts of corresponding faults in the circuits and relations between complete test sets. Since the method assumes that the initial network is only single stuck-at fault testable, and because single stuck-at fault testability is maintained through the transformations, the method can be applied to a large class of irredundant two-level and multi-level circuits to synthesize fully testable circuits.
Experimental results are presented and compared with various logic synthesis systems to demonstrate the efficiency and effectiveness of the method.
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Khomentrakarn, Chusak. "Testability analysis of asynchronous circuits designed from signal transition graphs." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22657.
Full textAbstract:
This work investigates testability of asynchronous circuits and its relation with signal transition graphs (STGs), using a state based approach on non-scan asynchronous circuits. In addition to the testability characteristics studied, this work suggests some test generation techniques for asynchronous circuits designed from STGS.An event fault, interpreted as either a stimulating fault or an inhibiting fault of a transition, is used to cover the stuck-at-fault (SAF) behavior of an asynchronous circuit. An advantage of such analysis is that test vectors for an inhibiting fault can be obtained from operations on a signal transition graph (STG) or a state graph (SG) rather than simulation at the circuit level. A test vector for a test state is represented in an STG by a test marking for each event fault.
The lock relation of signals is a property proposed for hazard-free asynchronous circuit's synthesis. However, it is found that there is a special case of the lock relation that can prohibit the testing of some faults, the introduction of which cannot be avoided by the circuit level mapping. Some independent undetectable faults due to uncontrollable test states however can be detected if the reset state is the test state.
Using a minimized two-level sum-of-products representation, each literal in a cube of the sum-of-products form is found to have its own function corresponding to the STG. Consequently, four types of literals are defined and their relations with the SAF behavior over the stimulating/inhibiting fault are analyzed. Although factorization of a logic equation binded to a C-element or a set-reset (SR) flip-flop is not always possible, a correct implementation on a set-dominant SR flip-flop is guaranteed. (Abstract shortened by UMI.)
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Shaheen, Muhammad Rabee. "Validation de métriques de testabilité logicielle pour les programmes objets." Phd thesis, Université Joseph Fourier (Grenoble), 2009. http://tel.archives-ouvertes.fr/tel-00978771.
Full textAbstract:
Pour les systèmes logiciels, la méthode de validation la plus utilisée est le test. Tester consiste en l'exécution du logiciel en sélectionnant des données et en observant/jugeant les sorties. C'est un processus souvent coûteux. Il dépend de la complexité du logiciel, des objectifs en termes de validation, des outils et du processus de développement. La testabilité logicielle s'intéresse à caractériser et prédire l'effort de test. Cela est nécessaire pour estimer le travail de test, prévoir les coûts, planifier et organiser le travail. De nombreuses mesures ont été proposées dans la littérature comme indicateurs du coût du test. Ces mesures sont focalisées sur l'évaluation de certains attributs qui peuvent rendre le test difficile. D'autres approches proposent de repérer des constructions difficiles à tester à l'aide de patrons (testability antipatterns) par exemple. D'une façon générale, peu d'études ont été réalisées pour valider ces métriques ou patrons. Certaines de ces études donnent des résultats contradictoires. Or il est essentiel de fournir des informations non biaisées. Notre travail de thèse porte en premier lieu sur la validation de certaines métriques de testabilité proposées pour la prédiction du coût du test de programmes objet. Notre approche s'appuie sur une mise en relation des métriques et des stratégies de test et vise à l'établissement de corrélation entre coût prédictive et coût effective. Ceci nous a conduit à raffiner certaines métriques étudiées. Dans un second temps, nous nous sommes intéressés à des patrons (testability antipatterns) visant à détecter des faiblesses dans le code vis à vis du test. Le but de cette étude est de comprendre à quels moments ces constructions sont introduites dans le code, afin de les repérer le plus efficacement possible.
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Ellouz, Sofiane. "Techniques innovantes pour la testabilité des circuits intégrés radio-fréquence." Lyon, INSA, 2006. http://www.theses.fr/2006ISAL0068.
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Les circuits intégrés radio-fréquence subissent différents tests industriels pour vérifier leur conformité aux spécifications du client. Pour réduire l’impact économique du test, il est nécessaire de développer de nouvelles méthodes de tests. La notion de signature a été utilisée pour estimer des performances RF d’un CI à partir de la mesure de courants et tensions continus et en basse fréquence. Le manuscrit détaille tout d’abord une méthode de quantification de la pertinence d’un test. Il décrit ensuite la méthode innovante proposée, qui fait appel à la mise en œuvre des réseaux de neurones. Le manuscrit décrit des blocs de stabilité qui ont pour but d’augmenter la pertinence des mesures et leurs corrélations avec les grandeurs RF. Enfin le manuscrit décrit un flot de conception intégrant la stabilité. Des vérifications expérimentales ont été menées sur des CI industriels et sur un grand nombre de piècesRadio frequency integration-circuit suffers various industrial tests to verify the agreement to customer specifications. These RF specifications can hardly be assessed at wafer level. In order to reduce the economic impact of RF tests and to over cover the limitation in test performances, it is necessary to propose new test methods. Signatures are reasonable candidates for the estimation of RF performances based on DC low-frequency measurement. The manuscript first details the tests performances assessment. Then the test method is described and particularly neural networks are used and learning issues are addressed along with the pertinence of input data. Design for test blocs one also introduced to enhance the pertinence of neural network input data with respect to RF quantities. Finally, a design flow for testability is attempted. Commercial transceivers are used for experimental validation of the proposed methods
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Fontana, Giuseppe. "Progressi nell'Analisi di Testabilità e nella Teoria Generale dei Circuiti Analogici." Doctoral thesis, 2018. http://hdl.handle.net/2158/1121856.
Full textAbstract:
Fault diagnosis and circuit modeling represent fundamental aspects as far as analysis, synthesis, maintenance, and implementation of analog circuits are concerned. In this respect, a crucial prerequisite to the realization of efficient procedures is represented by the possibility to get a priori an upper bound to their performances, starting from measurements on the system at hand: this is accomplished by means of Testability Analysis. In this work several new results concerning analog circuit Testability Analysis are described, which contribute to advancing the state of the art in this particular research field. Specifically, herein presented are: (a) a symbolic-technique-based new algorithm for Testability Analysis of analog circuits, which circumvents the main drawbacks affecting early approaches; (b) a theory and an algorithm for Testability Analysis of dc-excited periodically-switched networks, with straightforward application to DC-DC converters; (c) a novel fast algorithm suited to Testability Analysis of very large circuits, a task that early approaches generally fail; (d) examples of application of Testability Analysis as a guide to designing from scratch or refining procedures for fault diagnosis or modeling of analog circuits. Involved in the derivations of such results, yet noticeably important as such, also presented in this work is a new twofold Generalized Substitution Theorem, along with further novel contributions to General Circuit Theory, which straightforwardly derive from the former: in particular, described herein are extensions to classic results such as the Substitution Theorem, the Thévenin/Norton Theorem, the Miller Theorem and its dual, the Augmentation Principle as well as novel procedures for calculating the dc point and input-output (or driving-point) characteristics in nonlinear networks in a penciland-paper intuitive fashion. La diagnosi di guasto e la modellazione rappresentano aspetti fondamentali per l’analisi, il progetto, la implementazione e la manutenzione dei circuiti analogici. Prerequisito cruciale per la realizzazione di procedure efficienti atte ai summenzionati scopi è disporre - a partire da informazioni che possono trarsi da misure sul sistema in esame - di una rigorosa stima a priori delle loro possibilità di successo, il che si ottiene attraverso l’Analisi di Testabilità. In questo lavoro si descrivono alcuni nuovi risultati riguardanti l’Analisi di Testabilità dei circuiti analogici, che contribuiscono all’avanzamento dello stato dell’arte in tale ambito di ricerca. Si presentano, in particolare: (a) un nuovo algoritmo per l’Analisi di Testabilità dei circuiti lineari tempo-invarianti basato su tecniche simboliche, in grado di superare i principali inconvenienti da cui algoritmi preesistenti risultano affetti; (b) una teoria ed un algoritmo che, per la prima volta, consentono l’Analisi di Testabilità dei circuiti a commutazione periodica eccitati da segnali costanti, con particolare riguardo ai convertitori statici di energia; (c) un nuovo algoritmo veloce per l’Analisi di Testabilità di circuiti di grandi dimensioni, compito nel quale gli algoritmi preesistenti in genere falliscono; (d) esempi di impiego dell’Analisi di Testabilità nel progetto ex-novo o nel raffinamento di procedure per la diagnosi o la modellazione. Con applicazioni nella derivazione di tali risultati, ma, al contempo, con autonomia ed importanza loro proprie, si presentano altresì due nuovi Teoremi di Sostituzione Generalizzati, assieme a diversi ulteriori contributi alla Teoria Generale dei Circuiti Analogici che da essi direttamente derivano: si descrivono, in particolare, estensioni di noti teoremi, quali il classico Teorema di Sostituzione, il Teorema di Thévenin/Norton, il teorema di Miller assieme al suo duale, il Principio di Aumento, come pure procedure sistematiche per il calcolo intuitivo “carta-e-matita” del punto di riposo e delle caratteristiche di trasferimento in circuiti non lineari.