Dissertations / Theses on the topic 'Test signal generation'

A probabilistic test instrument is proposed for mixed-signal embedded test applications. The system architecture of the instrument and its implementation is presented. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. Using statistical methods, the probability distributions associated with these signals can be extracted using a simple circuit called a probability extraction unit, consisting of a few simple digital logic gates. At the core of this work is the use of ΣΔ phase-encoding technique to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. This technique is also used for generating the test stimulant for the device-under-test, or DUT as a shorthand notation. Experimental results reveal the sampling time strobe can be programmed over a phase range of 45 degrees with a phase step of 1 degree at a fixed voltage reference. The DUT stimulant and the timing and voltage references are all programmable in software. This provides additional flexibility and versatility when conducting a test. A prototype of the proposed test instrument was implemented using discrete components assembled on a printed-circuit board and shown to be capable of measuring the output jitter distribution associated with a clock and data signal of a DUT. It was further extended to measure the phase and frequency response of various analog channels associated with the DUT. The performance of the instrument was evaluated by comparing the test results with those obtain using other test techniques, independent of the instrument.
Un instrument pour les tests "mixed-signal" basé sur une approche statistique est proposé. L'architecture du système ainsi que son implémentation sont présentés. L'instrument peut être utilisé afin d'injecter ou de capturer des informations en temps et voltage associé aux signaux de hautes fréquences dans les systèmes de communication. En utilisant une approche statistique, la distribution de probabilité associée à un signal peut être calculée à l'aide d'un circuit appelé « probability extraction unit » implémenté de façon digital. De plus, l'utilisation de ΣΔ pour encoder des signaux dans la phase afin de générer des signaux dans le temps ainsi que des références pour du « high speed sampling » est démontré. Les résultats expérimentaux démontrent que des variations de phase de 45 degrés avec des intervalles de1 degré est possible. Ceci permet donc plus de flexibilité pour générer des signaux de tests qui sont programmables. Un prototype de cette technique fut implémenté sur « PCB » afin de démontrer que la technique est fonctionnelle. Les résultats des tests furent également comparés à ceux obtenus avec des instruments de mesures traditionnels et démontrent une excellente corrélation entre la méthode développée et les méthodes existantes.

With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer. Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author. Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques. A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.

La miniaturisation des circuits intégrés permet d'avoir une intégration plus élevée dans une même puce. Cela, conduit a des problèmes de qualité dans les signaux de communication et d’alimentation comme le phénomène de bruit de diaphonie entre les interconnections (Crosstalk) et de bruit dans le lignes d'alimentation (PSN, GB). Aussi problèmes de fiabilité peuvent éventuellement arriver a cause des variations dans les paramètres technologiques pendant le processus de fabrication. De ce fait, tout ces phénomènes ont un effet négatif sur le délai dans les circuits embarques (IC) et donnent lieu aux défauts sur le retard. Des échecs relie au délai dans les dispositifs semi conducteurs causes une augmentation de taux d'évasion de défaut, une perte de rendement et une diminution dans le taux de fiabilité. Techniques de Design-For-Test ont était développée a fin d'avoir une meilleur contrôlabilité et observabilité dans les nœuds internes du circuit pour détecter et localiser facilement l’emplacement des défauts. Cependant, ils ne sont pas toujours détectés par les modèles de défauts traditionnels.Cette thèse s’intéresse a l’analyse de ces phénomènes a fin de proposer de nouvelle méthodes de test du délai en considérant les phénomènes physiques pour faire face aux défauts provenant du processus de fabrication ou de problèmes physiques. Ces méthodes comprennent l'analyse de la variation du retard d'un chemin en présence du bruit de diaphonie, du bruit d'alimentation, et les variations de processus. Additionnellement, nous développons méthodes d'essai de retard sur un chemin pour identifier les motifs de test qui peuvent causer le pire des cas de retard sur un chemin cible. Les méthodes proposées peuvent être utilisées pour caractériser la vitesse de chemin et il contribue à résoudre le problème de «speed binning». En outre, ils peuvent être utilisés dans l'amélioration de l'approche classique ATPG de génération de «patterns» et elles sont indépendantes de la technologie. L'application de ces contributions peut apporter des améliorations considérables à la qualité de test IC en assurant une meilleure couverture des défauts et en aidant à augmenter le rendement de fabrication au cours de la vitesse du «binning» dans les puces IC. L’évolution en continue de la technologie en échelle nanométrique
Advancing nanometer technology scaling enables higher integration on a single chip with minimal feature size. As a consequence, the effects of signal and power integrity issues such as crosstalk noise between interconnects, power supply noise and ground bounce in the supply networks significantly increases. Also, reliability issues are eventually introduced by variations in the manufacturing process. These issues will negatively impact the timing characteristics in an integrated circuit (IC), as they give rise to delay defects. Delay-related parametric failures increase the defect escape rate, yield loss and diminish reliability rate. Hence, design-for-test techniques are employed to have a better controllability and observability on the internal nodes to easily detect and locate the faults. However, they are not always detected by the traditional fault models. In our work, we target these challenges and propose novel physical design-aware path delay test methods to deal with delay faults coming from manufacturing defects or physical design issues. They include the investigation of path delay variations in the presence of crosstalk noise, power supply noise, ground bounce and process variations. Based on this, we develop technology independent test methods for identifying the test patterns that may cause a worst-case delay on a target path. Then, we develop a dedicated test pattern generation method for path delay testing in the presence of crosstalk noise, power supply noise and ground noise. The proposed methods can be used to characterize the path speed and it helps to address the speed binning problem. Also, they can be employed in improving the classical ATPG approach of pattern generation. The application of these contributions can bring tremendous improvements to the IC test quality by ensuring better defect coverage and for an increased manufacturing yield during speed binning of IC chips

Tests for detecting faults in analog and mixed-signal circuits have been traditionally derived from the datasheet speci and #64257;cations. Although these speci and #64257;cations describe important aspects of the device, in many cases these application oriented tests are costly to implement and are inefficient in determining product quality. Increasingly, the gap between speci and #64257;cation test requirements and the capabilities of test equipment has been widening. In this work, a systematic method to generate and evaluate alternate tests for detecting parametric faults is proposed. We recognize that certain aspects of analog test generation problem are not amenable to automation. Additionally, functional features of analog circuits are widely varied and cannot be assumed by the test generator. To overcome these problems, an extended device under test (DUT) model is developed that encapsulates the DUT and the DUT speci and #64257;c tasks. The interface of this model provides a well de and #64257;ned and uniform view of a large class of devices. This permits several simpli and #64257;cations in the test generator. The test generator is uses a search-based procedure that requires evaluation of a large number of candidate tests. Test evaluation is expensive because of complex fault models and slow fault simulation techniques. A tester-resident test evaluation technique is developed to address this issue. This method is not limited by simulation complexity nor does it require an explicit fault model. Making use of these two developments, an efficient and automated test generation method is developed. Theoretical development and a number of examples are used to illustrate various concepts that are presented in this thesis.

This thesis extends signal generation techniques using sigma-delta encoding principles for synthesizing test signals of all types. In fact, sigma-delta encoding is used to generate repeatable and programmable noise-like signals; phase domain signals such as accurate phase offsets, sinusoidal and Gaussian jitter; and frequency domain signals used for accurate frequency synthesis. For the synthesis of noise-like signals, a Gaussian noise with the desired frequency characteristic is encoded in the voltage/amplitude domain in software using sigma-delta modulation. The resulting sequence of bits is then captured and applied cyclically to an analog filter to reconstruct the noise-like signal with the desired frequency spectrum (e.g. spectrum with a notch for noise-power ratio test). Moreover, a novel bit-to-bit mapping algorithm that converts digital signals to either phase or frequency, is proposed. A digital-to-time conversion (DTC) algorithm is used to convert a digital signal to the phase domain; likewise, a digital-to-frequency conversion (DFC) algorithm is used to convert a digital signal to the frequency domain. The DTC or DFC conversion algorithm is implemented in software together with the sigma-delta encoding process in order to digitally encode a phase or frequency domain signal. The resulting bit sequence with the desired phase or frequency signal is then captured and applied cyclically to an analog time/frequency-mode reconstruction filter. The time/frequency-mode filtering is realized by a PLL structure with the desired phase/frequency domain transfer function. All signal generation schemes (amplitude, noise, phase and frequency) consist of a digital bit-stream with the desired signal encoded and a reconstruction filtering device in the appropriate domain. Using the proposed techniques and circuits, robust, programmable, repeatable, and portable test signals in the amplitude, phase, and frequency domains can be synthesized at low-cost. Although the techniques are demonstrated in a production test environment using a commercial mixed-signal tester, the methodology can be implemented in any testing environment: production test, characterization test, design-for-test (DFT), or built-in self-test (BIST).
Cette thèse étend les techniques de génération de signal se basant sur les principes d'encodage sigma-delta pour la synthèse de tous les types de signaux de test. En effet, l'encodage sigma-delta est utilisé pour générer de façon répétable et programmable des signaux ressemblant au bruit; des signaux dans le domaine de la phase, tel que des délais précis et gigue d'horloge sinusoïdale et Gaussienne; et des signaux dans le domaine fréquentielle utilisés pour une synthèse précise de fréquence.Pour la synthèse de signaux ressemblant au bruit, un bruit Gaussien avec le spectre désiré est encodé dans le domaine voltage/amplitude en software en utilisant la modulation sigma-delta. La séquence de bits résultante est par la suite capturée et appliquée cycliquement à un filtre analogique afin de reconstituer le signal de bruit avec les caractéristiques spectrales désirées (ex. une entaille dans la bande de fréquence pour le test de rapport de puissances de bruit).De plus, un nouvel algorithme de transformation bit-par-bit convertissant les signaux numériques au domaine de phase ou de fréquence est proposé. Un algorithme de conversion numérique-à-temps (CNT) est utilisé pour convertir un signal numérique au domaine de la phase, de la même manière, une conversion numérique-à-fréquence (CNF) est utilisée pour convertir un signal numérique au domaine fréquentielle. Les deux algorithmes de conversion CNT et CNF sont implantés en software conjointement avec le processus d'encodage sigma-delta, encodant ainsi de façon numérique le signal désiré dans le domaine de phase ou de fréquence. La séquence de bits résultante encodant le signal désiré dans la phase ou la fréquence est par la suite capturée et appliquée cycliquement à un de filtre de reconstruction de mode temps/fréquence. Le filtre de mode temps/fréquence est réalisé à l'aide d'une structure de boucle à verrouillage de phase ayant la fonction de transfert désiré.Toutes les méthodologies de génération de signaux (amplitude, bruit, phase et fréquence) consistent en un train de bits encodant le signal désiré et un dispositif de filtrage de reconstruction dans le domaine approprié. Utilisant les techniques et circuits proposés, des signaux de test robustes, programmables, répétables et portables peuvent être synthétisé à un coût relativement bas. Malgré que les techniques de test sont démontrés seulement dans un environnement de production utilisant un testeur à signaux mixtes commercial, la méthodologie quant à elle peut être implantée dans tous les environnements de test : test en production, conception pour le test (DFT) et test intégré (BIST).

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.

Considerable research has been directed towards efficient test stimuli generation for Register Transfer Level (RTL) circuits. However, stimuli generation frameworks are still not capable of generating effective stimuli for all circuits. Some of the limiting factors are 1) It is hard to ascertain if a branch in the RTL code is reachable, and 2) Some hard-to-reach branches require intelligent algorithms to reach them. Since unreachable branches cannot be reached by any test sequence, we propose a method to deduce unreachability of a branch by looking for the possible values which a signal can take in an RTL code without explicit unrolling of the design. To the best of our knowledge, this method has been able to identify more unreachable branches than any method published in this domain, while being computationally less expensive. Moreover, some branches require very specific values on input signals in specific cycles to reach them. Conventional symbolic execution can generate those values but is computationally expensive. We propose a cycle-by-cycle restrictive symbolic execution that analyzes only a selected subset of program statements to reduce the computational cost. Our proposed method gathers information from an initial execution trace generated by any technique, to intelligently decide specific cycles where the application of this method will be helpful. This method can hybrid with simulation-based test stimuli generation methods to reduce the cost of formal verification. With this method, we were able to reach some previously unreached branches in ITC99 benchmark circuits.
Master of Science

In todays fast evolving mobile communications the requirements of higher datarates are continuously increasing, pushing operators to upgrade the backhaul to support these speeds. A cost eective way of doing this is by using microwave links between base stations, but as the requirements of data rates increase, the capacity of the microwave links must be increased. This thesis was part of a funded research project with the objective of developing the next generation high speed microwave links for the E-band. In the research project there was a need for a testing system that was able to generate a series of test signals with selectable QAM modulations and adjustable properties to be able to measure and evaluate hardware within the research project. The developed system was designed in a digital domain using an FPGA platform from Altera, and had the ability of selecting several types of modulations and changing the properties of the output signals as requested. By using simulation in several steps and measurements of the complete system the functionality was verified and the system was delivered to the research project successfully. The developed system can be used to test several dierent modulators in other projects as well and is easily extended to provide further properties.

Les techniques d'autotest intégré (BIST) jouent un rôle important dans les circuits analogiques, à signaux mixtes et RF (AMS-RF) afin d'améliorer le rendement des processus nanométriques avancés. Ces circuits remplacent les testeurs AMS-RF très sophistiqués et coûteux. Le générateur de stimuli est l'un des blocs importants des circuits BIST AMS-RF. En particulier, de nombreux tests analogiques-RF nécessitent un signal sinusoïdal de haute qualité comme stimuli de test. L'objectif de cette thèse est de comprendre les défis posés par la génération d'un signal sinusoïdal dans la gamme des GHz et d'atténuer ces défis en utilisant le principe d'annulation harmonique. Dans le principe d'annulation harmonique, un ensemble de signaux périodiques décalés dans le temps sont mis à l'échelle et ajoutés. Dans ce processus, les harmoniques du signal périodique sont annulées et la fréquence fondamentale est conservée à la sortie. Dans ce cas particulier, un générateur de signaux capable d'annuler les harmoniques inférieures à la 11e harmonique est nécessaire. Malgré son efficacité, cette technique est très sensible à la dégradation des performances en raison de l'inadéquation et des variations de processus. Ces variations affectent le décalage temporel et le rapport cyclique (également appelés imprécisions temporelles) du signal, en particulier dans les applications à haute fréquence où un contrôle précis devient de plus en plus difficile. Pour y remédier, une nouvelle architecture d'étalonnage utilise un mécanisme de cellule de retard grossier-fin, qui atténue efficacement l'impact des imprécisions temporelles. L'une des solutions proposées a été fabriquée en utilisant la technologie FDSOI 28 nm de ST et validée. Les résultats des mesures montrent un SFDR supérieur à 60dBc pour des fréquences supérieures à 1 GHz après optimisation, illustrant le potentiel de notre architecture dans l'amélioration de la fiabilité et de l'efficacité de la génération de signaux sinusoïdaux sur la puce pour les circuits intégrés AMS-RF
Built-in self-test (BIST) techniques play an important role in Analog, Mixed-signal, and RF (AMS-RF) circuits so that the yield in advanced nanometric processes can be improved. These circuits replace highly sophisticated and expensive AMS-RF testers. The stimuli generator is one of the important blocks in AMS-RF BIST circuits. In particular, many analog-RF tests require a high-quality sinusoidal signal as test stimuli. The focus of this thesis is to understand the challenges of generating a sinusoidal signal in GHz range and mitigating these challenges using the harmonic cancellation principle. In harmonic cancellation principle, a set of time-shifted periodic signals are scaled and added. In this process, harmonics of the periodic signal are cancelled and the fundamental frequency is retained at the output. Particularly in this case, a signal generator that can cancel the harmonics below the 11th harmonic. Despite its efficiency, this technique is highly susceptible to performance degradation due to mismatch and process variations. These variations affect time-shift and the duty cycle (also called timing inaccuracies) of the signal, particularly in high-frequency applications where precise control becomes increasingly challenging. To address this, a novel calibration architecture employs a coarse-fine delay cell mechanism, which effectively mitigates the impact of timing inaccuracies. One of the proposed solutions was fabricated using ST 28-nm FDSOI technology and validated. The measurement results show an SFDR greater than 60dBc for frequencies greater than 1 GHz after optimization, illustrating the potential of our architecture in enhancing the reliability and effectiveness of on-chip sinusoidal signal generation for AMS-RF integrated circuits

Développer un générateur de signal analogique efficace est un élément clés pour les BIST des circuits analogiques et mixtes afin de produire le stimulus de test approprié, et remplacer les générateurs de signaux externes couteux dans les protocoles de standard de test fonctionnel analogique et mixte. Dans cette optique, nous présentons dans cette thèse des stratégies différentes de génération de signal sinusoïdal, basées sur les techniques d’annulation d’harmonique, pour le design d’un synthétiseur embarqué de signal sinusoïdal à haute fréquence. Les générateurs proposés utilisent des circuits numériques pour produire un ensemble de signaux carrés déphasés. Ces signaux carrés sont pondérés et combinés en appliquant différentes stratégies d’annulation d’harmonique dans un convertisseur numérique-analogique simplifié. Le générateur sélectionné permet d’annuler toutes les harmoniques en dessous de la 11ème. De plus, une simple stratégie de calibration a été conçue pour compenser l’effet de mismatch et de la variation de process de fabrication sur l’efficacité de la technique d’annulation d’harmonique. La simplicité du circuit rend cette approche adaptable pour le BIST des circuits intégrés analogique et mixte. Les modèles comportementaux, les simulations électriques d’un design en 28nm FDSOI et les résultats expérimentaux sont fournis pour valider la fonctionnalité du générateur proposé. Les résultats obtenus montrent des performances du circuit calibré autour de 52dB de SFDR pour un signal généré à 166MHz
One of the main key points to enable mixed-signal BIST solutions is the development of efficient on-chip analog signal generators that can provide appropriate test stimuli and replace costly external signal generators in standard analog and mixed-signal functional test protocols. In this line, we present in this thesis different sinewave generation strategies based on harmonic cancellation techniques to design a high-frequency on-chip sinusoidal synthetize. The proposed generators employ digital hardware to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using different harmonic cancellation strategies in a simplified current-steering DAC. The selected generator allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28nm FDSOI design and experimental results are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 52dB of SFDR for a generated sinusoidal signal at 166 MHz

Test and evaluation (TandE) is a critically important step before in-the-field deployment of radio-frequency (RF) hardware in order to assure that the hardware meets its design requirements and specifications. Typically, TandE is performed either in a lab setting utilizing a software simulation environment or through real-world field testing. While the former approach is typically limited by the accuracy of the simulation models (particularly of the anticipated hardware effects) and by non-real-time data rates, the latter can be extremely costly in terms of time, money, and manpower. To build upon the strengths of these approaches and to mitigate their weaknesses, this work presents the development of an FPGA-based TandE tool that allows for real-time pseudo-random aggregate signal generation for testing RF receiver hardware (such as communication receivers, spectrum sensors, etc.). In particular, a framework is developed for an FPGA-based implementation of a test signal emulator that generates randomized aggregate spectral environments containing signals with random parameters such as center frequencies, bandwidths, start times, and durations, as well as receiver and channel effects such as additive white Gaussian noise (AWGN). To test the accuracy of the developed spectrum generation framework, the randomization properties of the framework are analyzed to assure correct probability distributions and independence. Additionally, FPGA implementation decisions, such as bit precision versus accuracy of the generated signal and the impact on the FPGA's hardware footprint, are analyzed.This analysis allows the test signal engineer to make informed decisions while designing a hardware-based RF test system. This framework is easily extensible to other signal types and channel models, and can be used to test a variety of signal-based applications.
Master of Science
Test and evaluation (TandE) is a critically important step before in-the-field deployment of radio-frequency signal hardware in order to assure that the hardware meets its design requirements and specifications. Typically, TandE is performed either in a lab setting utilizing a software simulation or through real-world field testing. While the former approach is typically limited by the accuracy of the simulation models and by slower data rates, the latter can be extremely costly in terms of time, money, and manpower. To address these issues, a hardware-based signal generation approach that takes the best of both methods mentioned above is developed in this thesis. This approach allows the user to accurately model a radio-frequency system without requiring expensive equipment. This work presents the development of a hardware-based TandE tool that allows for real-time random signal generation for testing radio-frequency receiver hardware (such as communication receivers). In particular, a framework is developed for an implementation of a test signal emulator that allows for user-defined randomization of test signal parameters such as frequencies, signal bandwidths, start times, and durations, as well as communications receiver effects. To test the accuracy of the developed emulation framework, the randomization properties of the framework are analyzed to assure correct probability distributions and independence. Additionally, hardware implementation decisions such as bit precision versus quality of the generated signal and the impact on the hardware footprint are analyzed. Ultimately, it is shown that this framework is easily extensible to other signal types and communication channel models.

Il presente lavoro di tesi ha come obiettivo la progettazione di un banco prova per un quarto di veicolo e la realizzazione di un generatore di segnale in grado di inviare segnali di ingresso ad un attuatore idraulico il quale sarà utilizzato per eccitare la ruota in modo da simulare il profilo stradale. La fase di progettazione è stata svolta utilizzando il software Solidworks. In seguito sono state eseguite simulazioni per l’analisi strutturale e di frequenza di alcune parti del banco tramite l’utilizzo del software Ansys. Terminata la fase di progetto, il modello Solidworks è stato importato in ambiente Simulink utilizzando i blocchi di modellazione della piattaforma Simscape/SimMechanics, in modo da effettuare un'analisi dinamica del modello. L’ultima parte dello studio riguarda la realizzazione di un generatore di segnale in grado di ricevere il segnale di feedback proveniente dal servo controller dell’attuatore. Il generatore è stato realizzato utilizzando il micro controllore Arduino Uno. Tale dispositivo, grazie alle sue potenzialità, ha permesso la generazione di un segnale sinusoidale a diverse ampiezza e frequenze in modo da coprirne un certo campo di valori in base alla richiesta. Inoltre tale sistema è in grado di ricevere il segnale di feedback dal servo controller dello shaker in modo tale da leggerne il valore e monitorarlo in tempo reale sul PC. I risultati di questo studio mostrano che il Quarter car test rig progettato è una piattaforma in grado di studiare il comportamento dinamico dei sistemi sospensivi, la cui struttura si rende capace di poter testare diverse tipologie di sospensioni e pesi di veicolo, rappresentando un solido punto di partenza per una futura realizzazione fisica del banco.

Кваліфікаційну роботу виконано на кафедрі біотехнічних систем Тернопільського національного технічного університету імені Івана Пулюя
У кваліфікаційній роботі удосконалено комп’ютерну систему генерування тестових сигналів серцевих. Розроблено імітаційну модель тестових сигналів серцевих у вигляді імпульсного ПКПВ, а саме в межах циклу сигнали подано у вигляді суми подовжених в часовому просторі хвиль (складових) сигналів серця (електрокардіосигналу), а із врахуванням циклічності – у вигляді суми подовжених в усьому часовому просторі k-их циклів сигналів серця з елементами стохастичності. Розроблена комп’ютерна система із використанням засобу MATLAB дає змогу по відомих медичних параметрах генерувати тестові сигнали серця людини сигнали патологій і норм із високою точністю їх відтворення і врахуванням у собі стохастичної циклічності.
The computer system for generating heart test signals has been improved in the qualification work. A simulation model of cardiac test signals in the form of pulsed PCPV was developed, namely within the cycle the signals are presented in the form of the sum of elongated in time space waves (components) of heart signals (electrocardiographic signal), and taking into account cyclicity - in the form of elongated in all time space k. their cycles of heart signals with elements of stochasticity. The developed computer system with the use of MATLAB tool allows to generate test signals of pathologies and norms with high accuracy of their reproduction and taking into account stochastic cyclicity according to known medical parameters.
ВСТУП 8 РОЗДІЛ 1. АНАЛІТИЧНА ЧАСТИНА 10 1.1. Електрокардіографія та сигнали серця людини 10 1.2. Математичні моделі сигналів серцевих 14 1.2.1. Моделі детерміновані 15 1.2.2. Моделі стохастичні 16 1.3. Висновки до розділу 1 18 2. ОСНОВНА ЧАСТИНА 19 2.1. Принцип реєстрації сигналів серцевих 19 2.2. Математичне моделювання 20 2.2.1. Механізм породження сигналів серцевих 20 2.2.2. Математична модель сигналів серцевих як імпульсний ПКПВ 23 2.3. Імітаційне моделювання сигналів серцевих 25 2.4. Алгоритм генерування сигналів серцевих 30 2.5. Тестування алгоритму генерування сигналів серцевих 34 2.6. Висновки до розділу 3 42 РОЗДІЛ 3. НАУКОВО-ДОСЛІДНА ЧАСТИНА 44 3.1. Блок-схема програмного забезпечення генерування сигналів серцевих 44 3.2. Програмне забезпечення генератора сигналів серцевих 46 3.2.1. Програмне забезпечення функції генерування сигналів серцевих 47 3.2.2. Програмне забезпечення генератора тестових сигналів серцевих 50 3.3. Верифікація генератора тестових сигналів серцевих 60 3.4. Висновки до розділу 4 64 РОЗДІЛ 4. ОХОРОНА ПРАЦІ ТА БЕЗПЕКА В НАДЗВИЧАЙНИХ СИТУАЦІЯХ 65 4.1. Охорона праці 65 4.2. Безпека в надзвичайних ситуаціях 67 4.3. Висновки до розділу 4 69 ЗАГАЛЬНІ ВИСНОВКИ 70 ПЕРЕЛІК ПОСИЛАНЬ 71 Додаток А. Програмне забезпечення функції генерування тестових сигналів серця 75 Додаток Б. Програмне забезпечення із інтерфейсом генератора тестових сигналів серця людини 77 Додаток В. Копія тези конференції 84

Capacitive crosstalk between adjacent signal wires in integrated circuits may lead to noise or a speedup or slowdown in signal transitions. These in turn may lead to circuit failure or reduced operating speed. This thesis focuses on generating test patterns to induce crosstalk-induced signal delays, in order to determine whether the circuit can still meet its timing specification. A timing-driven test generator is developed to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. By using path delay information obtained from circuit preprocessing, preferred paths can be chosen during aggressor path propagation processes. As the test generator sensitizes aggressors in the presence of victim path necessary assignments, the search space is effectively reduced for aggressor path generation. This helps in reducing the test generation time for aligned aggressors. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.