Relevant bibliographies by topics / Test signal generation

Academic literature on the topic 'Test signal generation'

Author: Grafiati
Published: 7 July 2024
Last updated: 7 July 2024

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Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Journal articles on the topic "Test signal generation":

1

Burdiek, B., and W. Mathis. "Test signal generation for analog circuits." Advances in Radio Science 1 (May 5, 2003): 235–38. http://dx.doi.org/10.5194/ars-1-235-2003.

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Abstract. In this paper a new test signal generation approach for general analog circuits based on the variational calculus and modern control theory methods is presented. The computed transient test signals also called test stimuli are optimal with respect to the detection of a given fault set by means of a predefined merit functional representing a fault detection criterion. The test signal generation problem of finding optimal test stimuli detecting all faults form the fault set is formulated as an optimal control problem. The solution of the optimal control problem representing the test stimuli is computed using an optimization procedure. The optimization procedure is based on the necessary conditions for optimality like the maximum principle of Pontryagin and adjoint circuit equations.
2

Dufils, M., J. L. Carbonero, P. Planelle, and P. Raynaud. "Mixed-signal simulation and test generation." International Journal of Electronics 95, no. 3 (March 2008): 239–48. http://dx.doi.org/10.1080/00207210701827954.

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3

Yin, Qizhang, William R. Eisenstadt, and Tian Xia. "Wireless System for Microwave Test Signal Generation." IEEE Design & Test of Computers 25, no. 2 (March 2008): 160–66. http://dx.doi.org/10.1109/mdt.2008.57.

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4

Ungermann, Michael, Jan Lunze, and Dieter Schwarzmann. "Test signal generation for service diagnosis based on local structural properties." International Journal of Applied Mathematics and Computer Science 22, no. 1 (March 1, 2012): 55–65. http://dx.doi.org/10.2478/v10006-012-0004-y.

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Test signal generation for service diagnosis based on local structural propertiesThe paper presents a new approach to the generation of test signals used in service diagnosis. The tests make it possible to isolate faults, which are isolable only if the system is brought into specific operating points. The basis for the test signal selection is a structure graph that represents the couplings among the external and internal signals of the system and the fault signals. Graph-theoretic methods are used to identify edges that disappear under certain operating conditions and prevent a fault from changing the system behavior at this operating point. These operating conditions are identified by validuals, which are indicators obtained during the graph-theoretic analysis. The test generation method is illustrated by a process engineering example.
5

Haurie, X., and G. W. Roberts. "Arbitrary-precision signal generation for mixed-signal built-in-self-test." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 11 (1998): 1425–32. http://dx.doi.org/10.1109/82.735354.

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6

Živanović, Dragan, Milan Simić, Zivko Kokolanski, Dragan Denić, and Vladimir Dimcev. "Generation of Long-time Complex Signals for Testing the Instruments for Detection of Voltage Quality Disturbances." Measurement Science Review 18, no. 2 (April 1, 2018): 41–51. http://dx.doi.org/10.1515/msr-2018-0007.

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Abstract Software supported procedure for generation of long-time complex test sentences, suitable for testing the instruments for detection of standard voltage quality (VQ) disturbances is presented in this paper. This solution for test signal generation includes significant improvements of computer-based signal generator presented and described in the previously published paper [1]. The generator is based on virtual instrumentation software for defining the basic signal parameters, data acquisition card NI 6343, and power amplifier for amplification of output voltage level to the nominal RMS voltage value of 230 V. Definition of basic signal parameters in LabVIEW application software is supported using Script files, which allows simple repetition of specific test signals and combination of more different test sequences in the complex composite test waveform. The basic advantage of this generator compared to the similar solutions for signal generation is the possibility for long-time test sequence generation according to predefined complex test scenarios, including various combinations of VQ disturbances defined in accordance with the European standard EN50160. Experimental verification of the presented signal generator capability is performed by testing the commercial power quality analyzer Fluke 435 Series II. In this paper are shown some characteristic complex test signals with various disturbances and logged data obtained from the tested power quality analyzer.
7

Huynh, S. D., Seongwon Kim, M. Soma, and Jinyan Zhang. "Automatic analog test signal generation using multifrequency analysis." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, no. 5 (May 1999): 565–76. http://dx.doi.org/10.1109/82.769805.

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8

Kuang, Jiangyu, and Tao He. "Research on automatic test sequence generation method of computer interlocking test." Journal of Physics: Conference Series 2246, no. 1 (April 1, 2022): 012072. http://dx.doi.org/10.1088/1742-6596/2246/1/012072.

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Abstract Railway computer interlocking system is the core equipment of station signal control system, which directly affects the reliability and safety of the whole system. It is essential to test the interlocking software comprehensively and strictly [1]. The traditional interlocking test is conducted by testers to control the quality and efficiency of the test. According to the reference railway transportation “Interim Measures for railway signal interlocking test”, combined with the signal interlocking relationship test checklist, compared with the actual station yard of railway station, relying on manual preparation and manual implementation of test items, the test efficiency is relatively low. Therefore, the realization of automatic interlocking test has become a research hotspot at present. Interlocking function test belongs to the research field of black box test. On the premise of ensuring the comprehensiveness of test, generating efficient test sequence is the research focus of this subject.
9

Dufort, B., and G. W. Roberts. "On-chip analog signal generation for mixed-signal built-in self-test." IEEE Journal of Solid-State Circuits 34, no. 3 (March 1999): 318–30. http://dx.doi.org/10.1109/4.748183.

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10

Liu, Xin. "Conflict-Driven Learning in Test Pattern Generation." Advanced Materials Research 301-303 (July 2011): 1089–92. http://dx.doi.org/10.4028/www.scientific.net/amr.301-303.1089.

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SAT-based automatic test pattern generation (ATPG) is built on a SAT-solver, which can be scalable is that it is able to take into account the information of high-level structure of formulas. Paper analyzes specific structure of circuit instances where correlations among signals have been established. This analysis is a heuristic learning method by earlier detecting assignment conflicts. Reconvergent fanout is a fundamental cause of the difficulty in testing generation, because they introduce dependencies in the values that can be assigned to nodes. Paper exploits reconvergent fanout analysis of circuit to gather information about local signal correlation through BDD learning, and then used the learned information in the conjunctive normal form (CNF) clauses to restrict and focus the overall search space of test pattern generation. The experimental results demonstrate the effectiveness of these learning techniques.
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Journal articles Dissertations / Theses Books

Dissertations / Theses on the topic "Test signal generation":

1

Chowdhury, Azhar. "A probabilistic test instrument using sigma-delta phase signal generation technique for mixed signal embedded test." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=107696.

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A probabilistic test instrument is proposed for mixed-signal embedded test applications. The system architecture of the instrument and its implementation is presented. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. Using statistical methods, the probability distributions associated with these signals can be extracted using a simple circuit called a probability extraction unit, consisting of a few simple digital logic gates. At the core of this work is the use of ΣΔ phase-encoding technique to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. This technique is also used for generating the test stimulant for the device-under-test, or DUT as a shorthand notation. Experimental results reveal the sampling time strobe can be programmed over a phase range of 45 degrees with a phase step of 1 degree at a fixed voltage reference. The DUT stimulant and the timing and voltage references are all programmable in software. This provides additional flexibility and versatility when conducting a test. A prototype of the proposed test instrument was implemented using discrete components assembled on a printed-circuit board and shown to be capable of measuring the output jitter distribution associated with a clock and data signal of a DUT. It was further extended to measure the phase and frequency response of various analog channels associated with the DUT. The performance of the instrument was evaluated by comparing the test results with those obtain using other test techniques, independent of the instrument.
Un instrument pour les tests "mixed-signal" basé sur une approche statistique est proposé. L'architecture du système ainsi que son implémentation sont présentés. L'instrument peut être utilisé afin d'injecter ou de capturer des informations en temps et voltage associé aux signaux de hautes fréquences dans les systèmes de communication. En utilisant une approche statistique, la distribution de probabilité associée à un signal peut être calculée à l'aide d'un circuit appelé « probability extraction unit » implémenté de façon digital. De plus, l'utilisation de ΣΔ pour encoder des signaux dans la phase afin de générer des signaux dans le temps ainsi que des références pour du « high speed sampling » est démontré. Les résultats expérimentaux démontrent que des variations de phase de 45 degrés avec des intervalles de1 degré est possible. Ceci permet donc plus de flexibilité pour générer des signaux de tests qui sont programmables. Un prototype de cette technique fut implémenté sur « PCB » afin de démontrer que la technique est fonctionnelle. Les résultats des tests furent également comparés à ceux obtenus avec des instruments de mesures traditionnels et démontrent une excellente corrélation entre la méthode développée et les méthodes existantes.
2

Huynh, Sam DuPhat. "Testability analysis for mixed analog/digital circuit test generation and design for test /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6134.

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3

Ahmad, Shakeel. "Stimuli Generation Techniques for On-Chip Mixed-Signal Test." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61712.

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With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer. Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author. Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques. A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.
4

Asokan, Anu. "Signal Integrity - Aware Pattern Generation for Delay Testing." Thesis, Montpellier, 2015. http://www.theses.fr/2015MONTS206/document.

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La miniaturisation des circuits intégrés permet d'avoir une intégration plus élevée dans une même puce. Cela, conduit a des problèmes de qualité dans les signaux de communication et d’alimentation comme le phénomène de bruit de diaphonie entre les interconnections (Crosstalk) et de bruit dans le lignes d'alimentation (PSN, GB). Aussi problèmes de fiabilité peuvent éventuellement arriver a cause des variations dans les paramètres technologiques pendant le processus de fabrication. De ce fait, tout ces phénomènes ont un effet négatif sur le délai dans les circuits embarques (IC) et donnent lieu aux défauts sur le retard. Des échecs relie au délai dans les dispositifs semi conducteurs causes une augmentation de taux d'évasion de défaut, une perte de rendement et une diminution dans le taux de fiabilité. Techniques de Design-For-Test ont était développée a fin d'avoir une meilleur contrôlabilité et observabilité dans les nœuds internes du circuit pour détecter et localiser facilement l’emplacement des défauts. Cependant, ils ne sont pas toujours détectés par les modèles de défauts traditionnels.Cette thèse s’intéresse a l’analyse de ces phénomènes a fin de proposer de nouvelle méthodes de test du délai en considérant les phénomènes physiques pour faire face aux défauts provenant du processus de fabrication ou de problèmes physiques. Ces méthodes comprennent l'analyse de la variation du retard d'un chemin en présence du bruit de diaphonie, du bruit d'alimentation, et les variations de processus. Additionnellement, nous développons méthodes d'essai de retard sur un chemin pour identifier les motifs de test qui peuvent causer le pire des cas de retard sur un chemin cible. Les méthodes proposées peuvent être utilisées pour caractériser la vitesse de chemin et il contribue à résoudre le problème de «speed binning». En outre, ils peuvent être utilisés dans l'amélioration de l'approche classique ATPG de génération de «patterns» et elles sont indépendantes de la technologie. L'application de ces contributions peut apporter des améliorations considérables à la qualité de test IC en assurant une meilleure couverture des défauts et en aidant à augmenter le rendement de fabrication au cours de la vitesse du «binning» dans les puces IC. L’évolution en continue de la technologie en échelle nanométrique
Advancing nanometer technology scaling enables higher integration on a single chip with minimal feature size. As a consequence, the effects of signal and power integrity issues such as crosstalk noise between interconnects, power supply noise and ground bounce in the supply networks significantly increases. Also, reliability issues are eventually introduced by variations in the manufacturing process. These issues will negatively impact the timing characteristics in an integrated circuit (IC), as they give rise to delay defects. Delay-related parametric failures increase the defect escape rate, yield loss and diminish reliability rate. Hence, design-for-test techniques are employed to have a better controllability and observability on the internal nodes to easily detect and locate the faults. However, they are not always detected by the traditional fault models. In our work, we target these challenges and propose novel physical design-aware path delay test methods to deal with delay faults coming from manufacturing defects or physical design issues. They include the investigation of path delay variations in the presence of crosstalk noise, power supply noise, ground bounce and process variations. Based on this, we develop technology independent test methods for identifying the test patterns that may cause a worst-case delay on a target path. Then, we develop a dedicated test pattern generation method for path delay testing in the presence of crosstalk noise, power supply noise and ground noise. The proposed methods can be used to characterize the path speed and it helps to address the speed binning problem. Also, they can be employed in improving the classical ATPG approach of pattern generation. The application of these contributions can bring tremendous improvements to the IC test quality by ensuring better defect coverage and for an increased manufacturing yield during speed binning of IC chips
5

Alani, Alaa Fadhil. "A steady-state response test generation technique for mixed-signal integrated circuits." Thesis, Brunel University, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.316941.

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6

Woelk, Linley Elton. "Digital generation of low frequency, low distortion test waveforms." Thesis, Kansas State University, 1985. http://hdl.handle.net/2097/16049.

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7

Gomes, Alfred Vincent. "Alternate Test Generation for Detection of Parametric Faults." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5285.

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Tests for detecting faults in analog and mixed-signal circuits have been traditionally derived from the datasheet speci and #64257;cations. Although these speci and #64257;cations describe important aspects of the device, in many cases these application oriented tests are costly to implement and are inefficient in determining product quality. Increasingly, the gap between speci and #64257;cation test requirements and the capabilities of test equipment has been widening. In this work, a systematic method to generate and evaluate alternate tests for detecting parametric faults is proposed. We recognize that certain aspects of analog test generation problem are not amenable to automation. Additionally, functional features of analog circuits are widely varied and cannot be assumed by the test generator. To overcome these problems, an extended device under test (DUT) model is developed that encapsulates the DUT and the DUT speci and #64257;c tasks. The interface of this model provides a well de and #64257;ned and uniform view of a large class of devices. This permits several simpli and #64257;cations in the test generator. The test generator is uses a search-based procedure that requires evaluation of a large number of candidate tests. Test evaluation is expensive because of complex fault models and slow fault simulation techniques. A tester-resident test evaluation technique is developed to address this issue. This method is not limited by simulation complexity nor does it require an explicit fault model. Making use of these two developments, an efficient and automated test generation method is developed. Theoretical development and a number of examples are used to illustrate various concepts that are presented in this thesis.
8

Aouini, Sadok. "Extending test signal generation using sigma-delta encoding beyond the voltage/amplitude domain." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104477.

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This thesis extends signal generation techniques using sigma-delta encoding principles for synthesizing test signals of all types. In fact, sigma-delta encoding is used to generate repeatable and programmable noise-like signals; phase domain signals such as accurate phase offsets, sinusoidal and Gaussian jitter; and frequency domain signals used for accurate frequency synthesis. For the synthesis of noise-like signals, a Gaussian noise with the desired frequency characteristic is encoded in the voltage/amplitude domain in software using sigma-delta modulation. The resulting sequence of bits is then captured and applied cyclically to an analog filter to reconstruct the noise-like signal with the desired frequency spectrum (e.g. spectrum with a notch for noise-power ratio test). Moreover, a novel bit-to-bit mapping algorithm that converts digital signals to either phase or frequency, is proposed. A digital-to-time conversion (DTC) algorithm is used to convert a digital signal to the phase domain; likewise, a digital-to-frequency conversion (DFC) algorithm is used to convert a digital signal to the frequency domain. The DTC or DFC conversion algorithm is implemented in software together with the sigma-delta encoding process in order to digitally encode a phase or frequency domain signal. The resulting bit sequence with the desired phase or frequency signal is then captured and applied cyclically to an analog time/frequency-mode reconstruction filter. The time/frequency-mode filtering is realized by a PLL structure with the desired phase/frequency domain transfer function. All signal generation schemes (amplitude, noise, phase and frequency) consist of a digital bit-stream with the desired signal encoded and a reconstruction filtering device in the appropriate domain. Using the proposed techniques and circuits, robust, programmable, repeatable, and portable test signals in the amplitude, phase, and frequency domains can be synthesized at low-cost. Although the techniques are demonstrated in a production test environment using a commercial mixed-signal tester, the methodology can be implemented in any testing environment: production test, characterization test, design-for-test (DFT), or built-in self-test (BIST).
Cette thèse étend les techniques de génération de signal se basant sur les principes d'encodage sigma-delta pour la synthèse de tous les types de signaux de test. En effet, l'encodage sigma-delta est utilisé pour générer de façon répétable et programmable des signaux ressemblant au bruit; des signaux dans le domaine de la phase, tel que des délais précis et gigue d'horloge sinusoïdale et Gaussienne; et des signaux dans le domaine fréquentielle utilisés pour une synthèse précise de fréquence.Pour la synthèse de signaux ressemblant au bruit, un bruit Gaussien avec le spectre désiré est encodé dans le domaine voltage/amplitude en software en utilisant la modulation sigma-delta. La séquence de bits résultante est par la suite capturée et appliquée cycliquement à un filtre analogique afin de reconstituer le signal de bruit avec les caractéristiques spectrales désirées (ex. une entaille dans la bande de fréquence pour le test de rapport de puissances de bruit).De plus, un nouvel algorithme de transformation bit-par-bit convertissant les signaux numériques au domaine de phase ou de fréquence est proposé. Un algorithme de conversion numérique-à-temps (CNT) est utilisé pour convertir un signal numérique au domaine de la phase, de la même manière, une conversion numérique-à-fréquence (CNF) est utilisée pour convertir un signal numérique au domaine fréquentielle. Les deux algorithmes de conversion CNT et CNF sont implantés en software conjointement avec le processus d'encodage sigma-delta, encodant ainsi de façon numérique le signal désiré dans le domaine de phase ou de fréquence. La séquence de bits résultante encodant le signal désiré dans la phase ou la fréquence est par la suite capturée et appliquée cycliquement à un de filtre de reconstruction de mode temps/fréquence. Le filtre de mode temps/fréquence est réalisé à l'aide d'une structure de boucle à verrouillage de phase ayant la fonction de transfert désiré.Toutes les méthodologies de génération de signaux (amplitude, bruit, phase et fréquence) consistent en un train de bits encodant le signal désiré et un dispositif de filtrage de reconstruction dans le domaine approprié. Utilisant les techniques et circuits proposés, des signaux de test robustes, programmables, répétables et portables peuvent être synthétisé à un coût relativement bas. Malgré que les techniques de test sont démontrés seulement dans un environnement de production utilisant un testeur à signaux mixtes commercial, la méthodologie quant à elle peut être implantée dans tous les environnements de test : test en production, conception pour le test (DFT) et test intégré (BIST).
9

Poling, Brian. "On-Chip Signal Generation and Response Waveform Extraction for Analog Built-In-Self-Test." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1190050023.

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10

Wang, Xian. "Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53521.

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Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.
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Books on the topic "Test signal generation":

1

Critchlow, E. A. J. Automatic generation of mixed-signal test programs. Manchester: UMIST, 1997.

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Roberts, Gordon W., and Albert K. Lu. Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3.

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Roberts, Gordon W. Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits. Boston, MA: Springer US, 1995.

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Roberts, Gordon W. Analog signal generation for built-in-self-test of mixed-signal integrated circuits. Boston: Kluwer Academic Publishers, 1995.

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Dufort, Benoit, and Gordon W. Roberts. Analog Test Signal Generation Using Periodic ΣΔ-Encoded Data Streams. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4377-0.

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Diamant, P. E. Automatic generation of mixed signal test programs from circuitsimulation data. Manchester: UMIST, 1994.

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Dufort, Benoit. Analog test signal generation using periodic [sigma delta]-encoded data streams. Boston: Kluwer Academic, 2000.

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Dufort, Benoit. Analog test signal generation using periodic [sigma delta]-encoded data streams. New York: Springer Science+Business Media, 2000.

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Alani, Alaa Fadhil. A steady-state response test generation technique for mixed-signal integrated circuits. Uxbridge: Brunel University, 1993.

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Gimpilevich, Yuriy. Signals and processes in radio electronics. ru: INFRA-M Academic Publishing LLC., 2024. http://dx.doi.org/10.12737/1852258.

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Each chapter of the textbook presents the relevant theoretical sections of the discipline “Signals and Processes in Radio Electronics”, provides examples of problem solving and test questions. Meets the requirements of the latest generation Federal State Educational Standard. For students and graduate students of higher educational institutions of radio-electronic and telecommunications areas and specialties.
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Book chapters on the topic "Test signal generation":

1

Dufort, Benoit, and Gordon W. Roberts. "Analog Signal Generation." In Analog Test Signal Generation Using Periodic ΣΔ-Encoded Data Streams, 65–95. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4377-0_4.

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Roberts, Gordon W., and Albert K. Lu. "Analog Multi-Tone Signal Generation." In Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits, 33–51. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3_3.

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Dufort, Benoit, and Gordon W. Roberts. "Mixed-Signal Testing." In Analog Test Signal Generation Using Periodic ΣΔ-Encoded Data Streams, 7–26. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4377-0_2.

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Corno, Fulvio, Maurizio Rebaudengo, Matteo Sonza Reorda, and Massimo Violante. "Test Pattern Generation under Low Power Constraints." In Evolutionary Image Analysis, Signal Processing and Telecommunications, 162–70. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/10704703_13.

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Roberts, Gordon W., and Albert K. Lu. "An Oversampling-Based Function Generator." In Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits, 53–71. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3_4.

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Madhavan, Sowmya, and S. Sandya. "Test Signal Generation for Detecting Faults on Mil-Std 1553 Bus." In Lecture Notes in Electrical Engineering, 127–34. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_14.

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Roberts, Gordon W., and Albert K. Lu. "Introduction." In Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits, 1–7. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3_1.

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Roberts, Gordon W., and Albert K. Lu. "An Oversampling-Based Analog Oscillator." In Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits, 9–32. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3_2.

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Roberts, Gordon W., and Albert K. Lu. "Conclusion." In Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits, 73–122. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2341-3_5.

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Mohamed, Khaled Salah. "New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test Generation." In Analog Circuits and Signal Processing, 121–52. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-22035-2_6.

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Conference papers on the topic "Test signal generation":

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Negreiros, Marcelo, Adao Souza Jr., Luigi Carro, and Altamiro Amadeu Susin. "RF Digital Signal Generation Beyond Nyquist." In 25th IEEE VLSI Test Symmposium. IEEE, 2007. http://dx.doi.org/10.1109/vts.2007.54.

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Abe, Fumitaka, Yutaro Kobayashi, Kenji Sawada, Keisuke Kato, Osamu Kobayashi, and Haruo Kobayashi. "Low-distortion signal generation for ADC testing." In 2014 IEEE International Test Conference (ITC). IEEE, 2014. http://dx.doi.org/10.1109/test.2014.7035304.

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Uemori, Satoshi, Takahiro J. Yamaguchi, Satoshi Ito, Yohei Tan, Haruo Kobayashi, Nobukazu Takai, Kiichi Niitsu, and Nobuyoshi Ishikawa. "ADC linearity test signal generation algorithm." In APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2010. http://dx.doi.org/10.1109/apccas.2010.5774755.

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Dufils, M., J. L. Carbonero, P. Planelle, and P. Raynaud. "Mixed-signal simulation and test generation." In International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. IEEE, 2006. http://dx.doi.org/10.1109/dtis.2006.1708704.

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Kim, Yongjoon, Myung-hoon Yang, Youngkyu Park, Daeyeal Lee, and Sungho Kang. "An Effective Test Pattern Generation for Testing Signal Integrity." In 2006 15th Asian Test Symposium. IEEE, 2006. http://dx.doi.org/10.1109/ats.2006.261032.

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Coyette, Anthony, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, and Georges Gielen. "Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis." In 2016 IEEE International Test Conference (ITC). IEEE, 2016. http://dx.doi.org/10.1109/test.2016.7805867.

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Cherubal, S. "Challenges in Next Generation Mixed-Signal IC Production Testing." In 14th Asian Test Symposium (ATS'05). IEEE, 2005. http://dx.doi.org/10.1109/ats.2005.34.

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Kato, Keisuke, Fumitaka Abe, Kazuyuki Wakabayashi, Chuan Gao, Takafumi Yamada, Haruo Kobayashi, Osamu Kobayashi, and Kiichi Niitsu. "Two-Tone Signal Generation for Communication Application ADC Testing." In 2012 21st Asian Test Symposium (ATS). IEEE, 2012. http://dx.doi.org/10.1109/ats.2012.12.

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Aouini, Sadok, Kun Chuai, and Gordon W. Roberts. "A low-cost ATE phase signal generation technique for test applications." In 2010 IEEE International Test Conference (ITC). IEEE, 2010. http://dx.doi.org/10.1109/test.2010.5699202.

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Kawabata, Masayuki, Koji Asami, Shohei Shibuya, Tomonori Yanagida, and Haruo Kobayashi. "Low-distortion signal generation for analog/mixed-signal circuit testing with digital ATE." In 2017 International Test Conference in Asia (ITC-Asia). IEEE, 2017. http://dx.doi.org/10.1109/itc-asia.2017.8097100.

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Reports on the topic "Test signal generation":

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Saldivar-Carranza, Enrique D., Howell Li, Jijo K. Mathew, Jairaj Desai, Tom Platte, Saumabha Gayen, James Sturdevant, Mark Taylor, Charles Fisher, and Darcy M. Bullock. Next Generation Traffic Signal Performance Measures: Leveraging Connected Vehicle Data. Purdue University Press, 2023. http://dx.doi.org/10.5703/1288284317625.

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High-resolution connected vehicle (CV) trajectory and event data has recently become commercially available. With over 500 billion vehicle position records generated each month in the United States, these data sets provide unique opportunities to build on and expand previous advances on traffic signal performance measures and safety evaluation. This report is a synthesis of research focused on the development of CV-based performance measures. A discussion is provided on data requirements, such as acquisition, storage, and access. Subsequently, techniques to reference vehicle trajectories to relevant roadways and movements are presented. This allows for performance analyses that can range from the movement- to the system-level. A comprehensive suite of methodologies to evaluate signal performance using vehicle trajectories is then provided. Finally, uses of CV hard-braking and hard-acceleration event data to assess safety and driver behavior are discussed. To evaluate scalability and test the proposed techniques, performance measures for over 4,700 traffic signals were estimated using more than 910 million vehicle trajectories and 14 billion GPS points in all 50 states and Washington, D.C. The contents of this report will help the industry transition towards a hybrid blend of detector- and CV-based signal performance measures with rigorously defined performance measures that have been peer-reviewed by both academics and industry leaders.
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Martinez, Kimberly D., and Gaojian Huang. Exploring the Effects of Meaningful Tactile Display on Perception and Preference in Automated Vehicles. Mineta Transportation Institute, October 2022. http://dx.doi.org/10.31979/mti.2022.2164.

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There is an existing issue in human-machine interaction, such that drivers of semi-autonomous vehicles are still required to take over control of the vehicle during system limitations. A possible solution may lie in tactile displays, which can present status, direction, and position information while avoiding sensory (e.g., visual and auditory) channels overload to reliably help drivers make timely decisions and execute actions to successfully take over. However, limited work has investigated the effects of meaningful tactile signals on takeover performance. This study synthesizes literature investigating the effects of tactile displays on takeover performance in automated vehicles and conducts a human-subject study to design and test the effects of six meaningful tactile signal types and two pattern durations on drivers’ perception and performance during automated driving. The research team performed a literature review of 18 articles that conducted human-subjects experiments on takeover performance utilizing tactile displays as takeover requests. Takeover performance in these studies were highlighted, such as response times, workload, and accuracy. The team then conducted a human-subject experiment, which included 16 participants that used a driving simulator to present 30 meaningful vibrotactile signals, randomly across four driving sessions measuring for reaction times (RTs), interpretation accuracy, and subjective ratings. Results from the literature suggest that tactile displays can present meaningful vibrotactile patterns via various in-vehicle locations to help improve drivers’ performance during the takeover and can be used to assist in the design of human-machine interfaces (HMI) for automated vehicles. The experiment yielded results illustrating higher urgency patterns were associated with shorter RTs and higher intuitive ratings. Also, pedestrian status and headway reduction signals presented shorter RTs and increased confidence ratings compared to other tactile signal types. Finally, the signal types that yielded the highest accuracy were the surrounding vehicle and navigation signal types. Implications of these findings may lie in informing the design of next-generation in-vehicle HMIs and future human factors studies on human-automation interactions.
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Hughes, Timothy M. A Graphically Based Test Signal Generator. Fort Belvoir, VA: Defense Technical Information Center, September 2000. http://dx.doi.org/10.21236/ada384406.

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Perl, Avichai, Bruce I. Reisch, and Ofra Lotan. Transgenic Endochitinase Producing Grapevine for the Improvement of Resistance to Powdery Mildew (Uncinula necator). United States Department of Agriculture, January 1994. http://dx.doi.org/10.32747/1994.7568766.bard.

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The original objectives are listed below: 1. Design vectors for constitutive expression of endochitinase from Trichoderma harzianum strain P1. Design vectors with signal peptides to target gene expression. 2. Extend transformation/regeneration technology to other cultivars of importance in the U.S. and Israel. 3. Transform cultivars with the endochitinase constructs developed as part of objective 1. A. Characterize foliar powdery mildew resistance in transgenic plants. Background of the topic Conventional breeding of grapevines is a slow and imprecise process. The long generation cycle, large space requirements and poor understanding of grapevine genetics prevent rapid progress. There remains great need to improve existing important cultivars without the loss of identity that follows from hybridization. Powdery mildew (Uncinula necator) is the most important fungal pathogen of grapevines, causing economic losses around the world. Genetic control of powdery mildew would reduce the requirement for chemical or cultural control of the disease. Yet, since the trait is under polygenic control, it is difficult to manipulate through hybridization and breeding. Also, because grapevines are heterozygous and vegetatively propagated cultivar identity is lost in the breeding process. Therefore, there is great need for techniques to produce transgenic versions of established cultivars with heterologous genes conferring disease resistance. Such a gene is now available for control of powdery mildew of grapevines. The protein coded by the Endochitinase gene, derived from Trichoderma harzianum, is very effective in suppressing U. necator growth. The goal of this proposal is to develop transgenic grapevines with this antifungal gene, and to test the effect of this gene on resistance to powdery mildew. Conclusions, achievements and implications Gene transfer technology for grape was developed using commercial cultivars for both wine and table grapes. It paved the way for a new tool in grapevine genetic studies enabling the alteration of specific important traits while maintaining the essential features of existing elite cultivars. Regeneration and transformation technologies were developed and are currently at an advanced stage for USA wine and Israeli seedless cultivars, representing the cutting edge of grape genetic engineering studies worldwide. Transgenic plants produced are tested for powdery mildew resistance in greenhouse and field experiments at both locations. It is our ultimate goal to develop transgenic grapes which will be more efficient and economical for growers to produce, while also providing consumers with familiar products grown with reduced chemical inputs.
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Tucker, Mark L., Shimon Meir, Amnon Lers, Sonia Philosoph-Hadas, and Cai-Zhong Jiang. Elucidation of signaling pathways that regulate ethylene-induced leaf and flower abscission of agriculturally important plants. United States Department of Agriculture, January 2012. http://dx.doi.org/10.32747/2012.7597929.bard.

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The Problem: Abscission is a highly regulated process, occurring as a natural terminal stage of development, in which various organs are separated from the parent plant. In most plant species, the process is initiated by a decrease in active auxin in the abscission zone (AZ) and an increase in ethylene, and may be accelerated by postharvest or environmental stresses. Another potential key regulator in abscission is IDA (Inflorescence Deficient in Abscission), which was identified as an essential peptide signal for floral organ abscission in Arabidopsis. However, information is still lacking regarding the molecular mechanisms integrating all these regulators. In our previous BARD funded research we made substantial progress towards understanding these molecular events in tomato, and the study is still in progress. We established a powerful platform for analysis of genes for regulatory proteins expressed in AZ. We identified changes in gene expression for several transcription factors (TFs) directly linked to ethylene and auxin signaling and several additional regulatory proteins not so obviously linked to these hormones. Moreover, we demonstrated using a virus-induced gene silencing (VIGS) assay that several play a functional role in the onset of abscission. Based on these results we have selected 14 genes for further analysis in stably transformed tomato plants. All 14 genes were suppressed by RNA interference (RNAi) using a constitutive promoter, and 5 of them were also suppressed using an abscission-specific promoter. Transformations are currently at different stages of progress including some lines that already display an abscission phenotype. Objectives: We propose here to (1) complete the functional analysis of the stably transformed tomato plants with T2 lines and perform transcriptome analysis using custom abscission-specific microarrays; (2) conduct an indepth analysis of the role of IDA signaling in tomato leaf and flower abscission; (3) perform transcriptome and proteome analyses to extend the earlier gene expression studies to identify transcripts and proteins that are highly specific to the separation layer (i.e., target cells for cell separation) prior to the onset of abscission; (4) extend and compliment the work in tomato using a winnowed set of genes in soybean. Methodology: Next Generation Sequencing (NGS) of mRNA will be used to further increase the list of abscission-associated genes, and for preparation of a custom tomato abscission microarray to test altered gene expression in transgenic plants. Tandem mass spectrometry (LC-MS/MS) of protein extracts from leaf petiole, flower pedicel and their AZ tissues will be used to identify the proteome of the AZ before and during abscission. AZ-specific gene promoters will be used in stably transformed tomato plants to reduce non-target phenotypes. The bean pod mottle virus (BPMV) plasmid vectors will be used for VIGS analysis in soybean. Expected Contribution: Our study will provide new insights into the regulation of ethylene-induced abscission by further revealing the role of key regulators in the process. This will permit development of novel techniques for manipulating leaf and flower abscission, thereby improving the postharvest performance of agriculturally important crops.
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Bäumler, Maximilian, and Matthias Lehmann. Generating representative test scenarios: The FUSE for Representativity (fuse4rep) process model for collecting and analysing traffic observation data. TU Dresden, 2024. http://dx.doi.org/10.26128/2024.2.

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Scenario-based testing is a pillar of assessing the effectiveness of automated driving systems (ADSs). For data-driven scenario-based testing, representative traffic scenarios need to describe real road traffic situations in compressed form and, as such, cover normal driving along with critical and accident situations originating from different data sources. Nevertheless, in the choice of data sources, a conflict often arises between sample quality and depth of information. Police accident data (PD) covering accident situations, for example, represent a full survey and thus have high sample quality but low depth of information. However, for local video-based traffic observation (VO) data using drones and covering normal driving and critical situations, the opposite is true. Only the fusion of both sources of data using statistical matching can yield a representative, meaningful database able to generate representative test scenarios. For successful fusion, which requires as many relevant, shared features in both data sources as possible, the following question arises: How can VO data be collected by drones and analysed to create the maximum number of relevant, shared features with PD? To answer that question, we used the Find–Unify–Synthesise–Evaluation (FUSE) for Representativity (FUSE4Rep) process model.We applied the first (“Find”) and second (“Unify”) step of this model to VO data and conducted drone-based VOs at two intersections in Dresden, Germany, to verify our results. We observed a three-way and a four-way intersection, both without traffic signals, for more than 27 h, following a fixed sample plan. To generate as many relevant information as possible, the drone pilots collected 122 variables for each observation (which we published in the ListDB Codebook) and the behavioural errors of road users, among other information. Next, we analysed the videos for traffic conflicts, which we classified according to the German accident type catalogue and matched with complementary information collected by the drone pilots. Last, we assessed the crash risk for the detected traffic conflicts using generalised extreme value (GEV) modelling. For example, accident type 211 was predicted as happening 1.3 times per year at the observed four-way intersection. The process ultimately facilitated the preparation of VO data for fusion with PD. The orientation towards traffic conflicts, the matched behavioural errors and the estimated GEV allowed creating accident-relevant scenarios. Thus, the model applied to VO data marks an important step towards realising a representative test scenario database and, in turn, safe ADSs.
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Khan, Asad, Angeli Jayme, Imad Al-Qadi, and Gregary Renshaw. Embedded Energy Harvesting Modules in Flexible Pavements. Illinois Center for Transportation, April 2024. http://dx.doi.org/10.36501/0197-9191/24-008.

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Energy from pavements can be harvested in multiple ways to produce clean energy. One of the techniques is electromagnetic energy harvesting, in which mechanical energy from vehicles is captured in the form of input displacement to produce electricity. In this study, a rack-and-pinion electromagnetic energy harvester proposed in the literature as a speed bump is optimized for highway-speed vehicles. A displacement transfer plate is also proposed, with a minimum depth of embedment in the pavement to carry input displacements from passing vehicles and excite the energy harvester. The energy harvester was designed, and kinematic modeling was carried out to establish power–output relations as a function of rack velocity. Sensitivity analysis of various parameters indicated that, for high-speed applications where rack velocities are relatively high, small input excitations could be harnessed to achieve the rated revolutions per minute (RPM) of the generator. A set of laboratory tests was conducted to validate the kinematic model, and a good correlation was observed between measured and predicted voltages. Dynamic modeling of the plate was done for both recovery and compression to obtain the plate and rack velocities. Using Monte Carlo simulation, the plate was designed for a class-9 truck with wide-base tires moving at 128 km/h. Design and layout of the energy harvester with a displacement transfer plate was proposed for field validation. The energy harvester with the displacement plate could be integrated with transverse rumble strips in construction zones and near diversions. Hence, it could be used as a standalone system to power roadside applications such as safety signs, road lights, speed cameras, and vehicle-to-infrastructure (V2I) systems.

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