Relevant bibliographies by topics / Test digitali

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  2. Dissertations / Theses
  3. Books
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Academic literature on the topic 'Test digitali'

Author: Grafiati
Published: 9 March 2023
Last updated: 10 March 2023

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Journal articles on the topic "Test digitali"

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Guicciardi, Marco, Daniela Loi, Andrea Manca, Monica Marini, Riccardo Pazzona, and Luigi Raffo. "Pollice verde 2.0: una nuova risorsa per un invecchiamento attivo." PSICOLOGIA DELLA SALUTE, no. 3 (October 2022): 28–39. http://dx.doi.org/10.3280/pds2022-003005.

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L'orticoltura può influire positivamente sul benessere delle persone anziane, contrastando il declino fisico e cognitivo e migliorando la qualità della vita. Le moderne tecnologie fornisco-no un valido supporto per incoraggiare lo svolgimento di tali attività e promuovere uno stile di vita attivo. Il presente studio esplorativo si propone di valutare gli effetti di attività di orticultura comunitaria supportate da una piattaforma digitale in un campione misto di partecipanti over 60 durante il periodo della pandemia da COVID-19. I partecipanti di età superiore ai sessanta anni hanno preso parte ad un percorso della durata di sei mesi, diviso in due periodi. Durante i primi tre mesi i partecipanti si sono limitati a rispondere ai test che indagavano le seguenti va-riabili psicologiche: autostima, solitudine, depressione, qualità della vita, affetti, supporto sociale e funzionamento cognitivo. Nei successivi tre mesi i partecipanti sono stati coinvolti in attività di orticoltura, supportate da applicazioni digitali accessibili tramite smartphone, cui ha fatto seguito la rilevazione delle stesse variabili psicologiche. Gli effetti dell'orticultura sono stati valutati confrontando le due serie di rilevazioni. I risultati mostrano un incremento della qualità della vita degli anziani, delle funzioni cognitive e, in misura minore, del benessere soggettivo. Gli anziani che risultano spo-sati o conviventi manifestano in genere una migliore qualità della vita e a seguito dell'intervento sono meno propensi ad esprimere stati affettivi negativi. Non sono stati evidenziati segni di depressione. L'orticultura assistita digitalmente può migliorare la qualità della vita degli anziani durante la pandemia da COVID-19.
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Gasperini, Massimo. "Pisae Forma Urbis. Digital drawing and ‘reading’ of the city." ZARCH, no. 8 (October 2, 2017): 200. http://dx.doi.org/10.26754/ojs_zarch/zarch.201782156.

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Se il territorio costituisce il supporto materiale sul quale si sono impressi e sovrapposti i segni lasciati dall’uomo attraverso i secoli, la città può essere a ragione considerata la massima manifestazione dell’intervento dell’uomo su di esso. I processi urbani che determinano un impianto con tutte le sue modificazioni dinamiche sono interconnessi senza soluzione di continuità storica tanto da essere riassunti e rinvenuti nella trama stessa della città. Possedere gli strumenti per cercare di comprenderne i contenuti costituisce un primo atto cognitivo di fondamentale importanza qualora si intenda partecipare consapevolmente all’accumulazione di nuove proposte all’interno del tessuto storicizzato.La fase analitica della lettura conduce alla comprensione di questi processi dinamici che hanno determinato storicamente gli assetti insediativi e infrastrutturali del territorio. In analogia con la letteratura possiamo asserire che il palinsesto territoriale corrisponde al testo della storia dell’uomo e per essere compreso deve essere letto con la logica del progetto, lo strumento eletto della disciplina dell’architettura. Il documento principale per la lettura è il rilievo. Sottoporre la forma urbana di Pisa all’indagine sperimentale della lettura mediante l’adozione di nuovi strumenti digitali costituisce un momento di approfondimento e di sintesi delle conoscenze acquisite oltre ad esperire nuove metodologie analitiche sia nel campo degli studi storico-archeologici che in quelli dell’urbanistica e dell’architettura. I modelli tridimensionali digitali di Pisa e del suo territorio entrano per la prima volta a far parte di tale apparato strumentale, potenzialmente aperto verso nuovi possibili modi di utilizzazione. In particolare la Pianta della città si pone come supporto tecnico per molteplici e multiformi applicazioni.If the territory is the material support on where the marks left by man through the centuries are impressed and superimposed, the city could be rightly considerated as the greatest manifestation of the human intervention on it. The process that determine an urban system with all its dynamic changes are interconnected in a historical continuum so as to be summarized and found in the same interlaced city. To have the means in such a way as to try to understand its contents is primary importance if one intends to participate with good knowledge of a case in proposing new plans within the historical tissue. The analytical phase of reading leads to understand these dynamic process that have historically caused the settling down order and the territorial structure. On the analogy of the literature we can assert that the territorial palimpsest accords with the man history text and to be understood should be read with the logic of the plan, the elect instrument of the architectonic discipline. The main document for reading is the survey. To submit the urban form of Pisa to the experimental research of the reading by using new digital instruments is an opportunity of search and synthesis of the acquired knowledges besides to test new analithical methodologies both in the field of historical and archaeologic studies and in those of the town-planning and architecture. For the first time the digital threedimensional models of Pisa and its territory take part of this instrumental system, potentially open to new modes of use. Particularly the 3D representation of the town is a technical support for many and multiform applications. However, these new instruments of representation need to be connected with new methods of ‘reading’ and interpretation.KEYWORDS: 3D city model, G.I.S., territory and town, reading and typological interpretation
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Reddy, Mr B. Ravinder, J. Nandini, and P. Sowmya Y. Sathwik. "Handwritten Text Recognition and Digital Text Conversion." International Journal of Trend in Scientific Research and Development Volume-3, Issue-3 (April 30, 2019): 1826–27. http://dx.doi.org/10.31142/ijtsrd23508.

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Veninata, Chiara. "Dal Catalogo generale dei beni culturali al knowledge graph del patrimonio culturale italiano: il progetto ArCo." DigItalia 15, no. 2 (December 2020): 43–56. http://dx.doi.org/10.36181/digitalia-00013.

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Le attività dell’ICCD sono da sempre indirizzate ad una maggiore condivisione e valorizzazione sia dei modelli di strutturazione della conoscenza sul patrimonio culturale sia dei dati prodotti nelle campagne di catalogazione. Negli ultimi anni l’ICCD ha concentrato le proprie attività sull’analisi e sull’applicazione delle potenzialità offerte dal semantic web e dai suoi strumenti. Uno dei risultati è il progetto ArCo, il grafo della conoscenza del patrimonio culturale italiano, costituito da una rete di ontologie e da oltre 169 milioni di triple riferite a oltre a 800 mila schede catalografiche. ArCo si basa sui dati del Catalogo generale dei beni culturali dell’Istituto centrale per il catalogo e la documentazione del MiBACT e sui dati dei suoi archivi fotografici. ArCo è distribuito congiuntamente con uno SPARQL endpoint, un software per convertire i record di catalogo in RDF e una ricca suite di materiale di documentazione (test, valutazione, istruzioni, esempi ecc.).
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Borgmann, Felix, Nils Kalbe, Nikolas Moroff, and Lucas Schreiber. "Simulative Testumgebung für eine Matrixproduktion/Simulative test environment for a matrix production - Digital sandbox solution for connecting AI-based software and hardware modules." wt Werkstattstechnik online 112, no. 06 (2022): 378–82. http://dx.doi.org/10.37544/1436-4980-2022-06-28.

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Um die Flexibilitätspotenziale einer Matrixproduktion zu nutzen, ist eine intelligente Steuerung und Anpassungsplanung und damit die Integration der Anlagen- und Produktionssystemebene erforderlich. Mit dem Ansatz einer Sandbox-Lösung als digitale Testumgebung lassen sich unterschiedliche simulationsbasierte KI-Module zur (Re-)Konfiguration einer Matrixproduktion sowie von Anlagenmodulen in Form eines digitalen Zwillings testen sowie zur iterativen Optimierung des realen Produktionssystems nutzen. Exploiting the potential flexibility of a matrix production requires intelligent adjustment planning and control and thus to integrate the plant and production system level. The sandbox solution as a digital test environment allows for testing different simulation-based AI modules for (re-)configuration of a matrix production as well as plant modules in the form of a digital twin and using them for iterative optimization of the real production system.
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Bunyan, Sabrina, and Alan Collins. "Digital Exclusion Despite Digital Accessibility: Empirical Evidence from an English City." Tijdschrift voor economische en sociale geografie 104, no. 5 (November 5, 2013): 588–603. http://dx.doi.org/10.1111/tesg.12047.

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González Sanmamed, Mercedes, Luisa Losada Puente, Nuria Rebollo Quintela, and Eduardo Rafael Rodríguez Machado. "El test de competencia digital docente (Test CDD) ¿Está formado el profesorado en competencias digitales?" Revista INFAD de Psicología. International Journal of Developmental and Educational Psychology. 2, no. 1 (July 16, 2022): 301–12. http://dx.doi.org/10.17060/ijodaep.2022.n1.v2.2355.

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La Ley Orgánica 3/2020, de 29 de diciembre, por la que se modifica la Ley Orgánica 2/2006, de 3 de mayo, de Educación establece en su preámbulo que las Tecnologías de la Información y la Comunicación serán pieza fundamental para producir el cambio metodológico, elemento de transformación educativa, herramienta clave en la formación del profesorado, y medio con el que adaptarnos a las necesidades individuales de cada alumno. En este curso, loscentros deberán iniciar las primerasfases deelaboración desu propio Plan Digital,con un análisis de la situación real y diagnosis de sus puntos fuertes y débiles; los respectivos consejos escolares aprobarán hacia final de curso un documento ya cerrado, para su aplicación efectiva en el curso 2022-23. El Plan Digital de Centro se entiende como un instrumento que debe favorecer e impulsar el uso de los medios digitales tanto en los procesos de enseñanza-aprendizaje como en el resto de los procesos de gestión del centro, siempre con el objetivo último de colaborar en el desarrollo integral del alumnado que deberá estar actualizado atendiendo a la nueva realidad social y al nuevo marco de referencia de la competencia digital. El presente trabajo de investigación tiene como objetivo principal analizar una de sus fases, la competencia digital docente un aspecto esencial en la formación del profesorado. Se analiza a través del test de Competencia Digital Docente (Test CDD) a un total de 17 centros educativos y en el que participan 459 profesores de diferentes niveles educativos. Para ello, presentamos una comparativa de participación docente y un análisis descriptivo de los resultados. Los datos obtenidos nos darán unos resultados que nos replantear la formación del profesorado para conseguir un auténtico desarrollo competencial en los diferentes niveles.
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Dornaleteche-Ruiz, Jon, Alejandro Buitrago-Alonso, and Luisa Moreno-Cardenal. "Categorization, Item Selection and Implementation of an Online Digital Literacy Test as Media Literacy Indicator." Comunicar 22, no. 44 (January 1, 2015): 177–85. http://dx.doi.org/10.3916/c44-2015-19.

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This paper aims to measure a population’s level of knowledge and active use of certain digital tools that play a primary role in developing their media literacy. To achieve it, an Online Digital Literacy test was designed to measure the knowledge and active usage of 45 different online software packages. This tool works as a reliable indicator to identify a population’s media literacy development in terms of its linguistic and technological dimensions. More than 1,500 subjects of different gender, age and level of studies were tested in different cities within the autonomous community of Castilla and León in Spain, to measure their competence using these tools. The resulting data has enabled the identification of the level differences between age groups and gender and to formulate proposals in respect of digital literacy to enhance the public’s competence in terms of media education. The general results indicate that people’s Online Digital Literacy level is lower than ideal and that there is a level divide in relation to gender and age and that the average user has a social and recreational profile as a consumer of pre-existing content on the Internet rather than as manager, instigator or creator of his or her own content. This paper’s conclusions therefore raise awareness of these deficiencies and encourage academic institutions to design specific digital literacy educational programmes to help citizens become media empowered.La presente investigación nace con el objetivo de medir el grado de dominio por parte de la población de una serie de herramientas digitales que juegan un papel clave en el desarrollo de la competencia mediática. Con ese fin, se ha elaborado una categorización que intenta abarcar todas las funcionalidades que la Web 2.0 brinda al usuario. Posteriormente, se ha delimitado cada una de ellas a través de tres ítems digitales concretos de uso extendido en la sociedad mediática. La selección realizada conforma un test de alfabetización digital on-line (test ADO) que mide el grado de conocimiento y uso activo de dichas herramientas, y que, por tanto, compone un indicador significativo de la competencia mediática en sus dimensiones lingüística y tecnológica. El test ha sido administrado a una muestra de más de 1.500 sujetos de diferente edad y nivel de estudios con el fin de obtener datos que ayuden a establecer objetivos en el panorama de la alfabetización digital y contribuyan hacia el empoderamiento ciudadano en materia de educación mediática. Los resultados y conclusiones generales indican que el nivel de alfabetización digital on-line del ciudadano medio no es el deseado, que existe una brecha digital generacional y de género, y que el perfil medio del usuario de Internet es más social, recreativo y consumidor de contenidos existentes, que proactivo, gestor y creador de contenidos propios.
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Chik, Alice. "Naturalistic CALL and Digital Gaming." TESOL Quarterly 47, no. 4 (September 3, 2013): 834–39. http://dx.doi.org/10.1002/tesq.133.

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Hafner, Christoph A. "Embedding Digital Literacies in English Language Teaching: Students' Digital Video Projects as Multimodal Ensembles." TESOL Quarterly 48, no. 4 (September 5, 2013): 655–85. http://dx.doi.org/10.1002/tesq.138.

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Dissertations / Theses on the topic "Test digitali"

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Piva, Filippo. "Soluzioni digitali e analogiche per la garanzia di sicurezza in sottosistemi critici ferroviari." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019.

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Il trasporto ferroviario evolve verso scenari caratterizzati da convogli che viaggiano sempre più ravvicinati e a velocità crescente, il che richiede standard di sicurezza sempre più elevati. Rendere più sicuri treni che viaggiano a distanze ridotte significa poterli localizzare con precisione, cosa che oggi viene fatta anche con soluzioni che si basano sul principio della odometria. Con lo sguardo rivolto al futuro, Rete Ferroviaria Italiana e Arces stanno sviluppando un nuovo sistema di localizzazione odometrica. Questa tesi ha l’obiettivo di studiare una soluzione che assicuri al percorso dei dati del sottosistema di odometria, dal sensore all’elaborazione digitale, una Probability of Failure per Hour non inferiore a 10^-9. Per realizzarlo è stato necessario assicurare l’integrità di una sezione analogica rispetto ai guasti di tipo stuck-at. Sono state quindi studiate le dinamiche di guasto, calcolato il MTBF e infine sono stati pensati stimoli di test in ingresso con controllo delle uscite, pilotati da una sezione digitale. La difficoltà principale è stata rendere trasparenti gli stimoli di test alla logica di elaborazione odometrica, in modo da non compromettere i segnali vitali. Inoltre è stato necessario controllare l’assenza di anomalie nel sensore e nel cavo di trasmissione che lo collega alla sezione analogica, attraverso la misura di corrente assorbita dall’alimentazione. Per farlo è stato progettato un circuito per le misure di corrente ed è stata programmata la sezione digitale per digitalizzare e verificare le misure. Infine è stata redatta la documentazione formale con la descrizione delle scelte progettuali e dei collaudi effettuati in laboratorio, al fine di ottenere la certificazione di sicurezza SIL4, la più alta possibile, come previsto da RFI. L’architettura della sezione digitale in cui si è lavorato era mista, comprendente FPGA e MCU. L’innovazione del progetto risiede nel far eseguire quante più operazioni possibile alla logica programmabile.
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MASSETTI, GEMMA. "A DIGITAL BATTERY FOR UNILATERAL SPATIAL NEGLECT: HOW NEW TECHNOLOGIES CAN MAKE THE NEUROPSYCHOLOGICAL EVALUATION MORE ACCURATE AND SENSITIVE." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/374741.

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La negligenza spaziale unilaterale (NSU) è un disturbo neuropsicologico dovuto a eventi cerebrovascolari (CVA), tumori cerebrali e lesioni cerebrali acquisite. I pazienti con NSU falliscono nell’orientarsi verso, rispondere e riportare eventi sensoriali che si verificano nel lato dello spazio e del corpo controlaterale al lato della lesione (tipicamente, il lato sinistro in pazienti con danno cerebrale destro), e nell’esplorare queste porzioni di spazio. La valutazione della NSU si basa soprattutto sulla valutazione delle prestazioni dei pazienti a test carta-e-matita. Tuttavia, sono ora disponibili evidenze emergenti che le tecnologie che si basano sui computer possano migliorare le procedure diagnostiche. I test computerizzati possono offrire più sensibilità e flessibilità, registrando molte più informazioni (ad es., l’accuratezza e i tempi di reazione simultaneamente). Queste caratteristiche riducono le possibilità di errore umano e permettono misurazioni quantitative e continue nei singoli pazienti, includendo un monitoraggio individuale e sensibile dei cambiamenti prestazionali lungo il corso di ripetute valutazioni. L’obiettivo principale della presente tesi di dottorato era quello di validare preliminarmente dei test digitali appositamente creati, comparandoli a test carta-e-matita tradizionalmente usati nella pratica clinica per la diagnosi di NSU. Tutti questi test sono stati creati in un ambiente digitale facile da usare e basato sull’utilizzo di uno schermo touch e di una penna digitale, così da simulare il tradizionale atto di scrittura. All’interno di tre studi, i partecipanti sani e i pazienti con danno cerebrale destro, con e senza NSU, sono stati sottoposti sia ai testi digitali che ai test carta-e-matita. Le analisi dei dati hanno mostrato risultati promettenti, suggerendo che i test digitali potrebbero condurre a una valutazione neuropsicologica più sensibile e precisa, smascherando inoltre casi di neglect residuale. Infine, i risultati presenti incoraggiano la raccolta di dati normativi per poter adottare i test digitali nella pratica clinica.
Unilateral Spatial Neglect (USN) is a neuropsychological disorder due to cerebrovascular accidents (CVA), cerebral tumours and brain injuries. USN patients fail to orient towards, respond to and report sensory events occurring in the side of space and the body contralateral to the side of the lesion (typically the left side in the right-brain-damaged patients), and to explore these portions of space. The assessment of USN has relied mainly on evaluating patients’ performances at paper-and-pencil tests. Nevertheless, emerging evidence that computer-based technologies may improve the assessment procedure is now available. More sensitivity and flexibility may indeed be offered by computerised tests, which typically record much more information (i.e., accuracy and reaction time measures simultaneously). These features reduce the chances of human error and allow for quantitative, continuous measures and even significance levels in single patients, including sensitive individual monitoring of performance changes through repeated assessments. The main aim of the present PhD thesis was to preliminarily validate purposely created digital tests, compared to similar classic paper-and-pencil tests traditionally used in the clinical setting for USN assessment. All these tasks were built up in a user-friendly digital environment based on touch screens and digital pens, simulating the act of filling in a paper-and-pencil set-up with the advantages of the touch system. Within three studies, healthy participants and right-brain-damaged patients with and without USN performed both the digital and the paper-and-pencil versions of tests. Data analyses showed promising results, suggesting that digital tests could lead to a more sensitive and precise neuropsychological evaluation, also unmasking cases of covert USN. Lastly, the present findings encourage the collection of normative data in order to adopt digital tests in clinical practice.
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MELE, Santino. "A SAT based test generation method for delay fault testing of macro based circuits." Doctoral thesis, Università degli studi di Ferrara, 2010. http://hdl.handle.net/11392/2388685.

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Delay fault testing and at-speed testing are widely used to verify the timing of synchronous digital IC’s. The importance of these techniques is still growing because of the relevant IC’s parameters uncertainties which characterize the current technologies. In order to drive this process, several fault models and test generation techniques have been developed that target different trade-offs between accuracy and efficiency. The largest fraction of these approaches is based upon gate level descriptions of the circuit. In case the basic building blocks are more complex than logic gates and their implementation is not known, functional level approaches have been proposed. For instance, this is the case for look-up tables based Field Programmable Gate Arrays (FPGAs) and it may be a perspective for deep submicron circuits that exploit logic bricks as basic building blocks. This class of circuits has been referred to as macro or module based. In this context, the main activities performed during the tree years of my PhD are related to the timing failures problems in module-based CMOS VLSI circuits. The attention to module-based (or block-based) circuits follows the current VLSI physical design trends that attempt to limit the parametric failures due to the scaling of technology toward nanometric feature sizes. In such technologies, in fact, the traditional design paradigms that are based on small (i.e gate level) cells may produce high levels of variability, thus resulting in parametric defects. The use of highly regular cell structures, called logic bricks has been proposed to solve these problems thus increasing the yield of VLSI circuits. A brick comprises a logic function created from a small set of logic primitives that are mapped on to a micro-regular fabric. Such logic function is typically more complex that those implemented in traditional VLSI libraries. Field Programmable Gate Array (FPGA) technology also exploits a module based design approach. Unlike logic bricks, FPGAs are completely programmable, because they are based on look up tables (a n-bit LUT can accomplish every n-bit function), but the drawback is related to the implementation of the LUT, that is unknown to designer and not optimized for regularity. In this scenario, the delay fault testing became a big issue, since it is very difficult to study a circuit built using modules whose implementation in not known, either for technological and for intellectual property reasons. Moreover, the aggressive timing policies used in today’s ICs make the need for delay fault testing more relevant. The main PhD activity, that will be explained in detail in this thesis, is related to a new method that we propose to generate test vectors for path delay faults in circuits based on modules. In particular, we consider the single path delay fault model in combinational circuits or in (enhanced) full-scan ones that are composed of functional blocks whose implementation is not known. In such circuits a path fault is detected by suitable conditions so that a test pair is able to propagate a transition through the path under test, in order to detect a path delay fault. In order to identify such conditions, we introduced a new signal representation that enables the use of boolean differential calculus. Also, additional conditions to prevent invalidation of tests by hazards have been identified. We suppose that the dynamic behavior of the block is modeled using input delays such as in the timing arc delay model. We target simple combinational blocks such as logic bricks, that are expected to present up to 8-10 inputs and a low logic depth. The used method is scalable, to generate conditions for path delay fault tests also at gate level. In order to assess the feasibility of the proposed approach, I realized a software, written in C/C++, that permits to find out robust and non-robust test pairs, starting from the BLIF description of a module based circuit. Such a software uses a BDD description of the blocks’ functions on which we apply Boolean Differences to obtain local sensitization conditions at module level. Since there are circuits whose BDD structure may be very large and it may be inefficient (in some cases also infeasible) to treat it, we translate functions obtained at macros level to a CNF description. After that, a SAT solver generates the test pairs at circuit level starting from the conjunction of all the CNF functions. The software tool was used to verify the proposed approach on a set of benchmarks (both combinational or full-scan) from ITC’99 and ISCAS’85 sets. Such benchmarks allowed to show the feasibility of the proposed approach, although they are not fully representative of the target circuits for which the method was developed. Another significant work, carried out during my PhD period, also deal with testing of macro-based circuits, but it concerns specifically logic bricks. In particular, a method for high quality functional fault simulation and test generation for such circuits was conceived and a software tool that implements it was developed. For both the approaches, results showed the feasibility of them, but also highlighted possibilities to improve and extend the work done.
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Dehart, Mehgan. "Relationship between the talk test and ventilatory threshold." Connect to Internet resource, 1999. http://murphylibrary.uwlax.edu/digital/thesis/1999/dehart.pdf.

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Thesis (M.S.)--University of Wisconsin -- La Crosse, 1999.
Digitized and made available by the University of Wisconsin--La Crosse, Murphy Library. Includes bibliographical references. Online version of print edition.
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Horn, Sonja, and Evelina Olsson. "Hur digitalt format påverkar studenters läsning : Läshastighet och läsupplevelse vid läsning av digital text kontra inskannad text." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254776.

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Universitet och högskolor rekommenderar idag stora mängder digital kurslitteratur. Digitalt material kan representeras i olika format, dels som inskannad från bok (inkongruent läsning), där texten inte kan bli manipulerad, samt som digital text (kongruent läsning), där texten är producerad för ett digitalt syfte och kan bli manipulerad till dess föredragna utseende (typsnitt, storlek, etc.). Dessutom möjliggör digital text användandet av verktyg såsom överstrykning och markörer. Tidigare studier indikerar att användande av sådana verktyg vid studier är fördelaktigt för studenters prestation. Denna studie syftar till att undersöka om olika digitala presentationer av text (inskannad och digital text) påverkar studenters läshastighet samt läsupplevelse. Två akademiska texter i både digitalt och inskannat format agerade som bas för denna fallstudie där skillnaden i läshastighet och läsupplevelse, mellan två gruppen som läste ett format var, analyserades. Resultatet av denna studie visade ingen signifikant skillnad i läshastighet mellan de två formaten. Däremot fanns det avsevärda skillnader i läsupplevelsen, där digital text föredrogs, med avseende på både tillgängliga verktyg samt utseendet på texten. Resultaten angående läsupplevelsen var i linje med tidigare forskning angående vana och attityd, och visade att studenters tidigare vana och bekvämlighet vid ett format påverkar läsupplevelsen av det formatet. Resultaten indikerade även att det fanns ett oväntat samband mellan att öva sig i läsning på ett format, och sedan föredra det formatet. Sammanfattningsvis har denna fallstudie visat att inskannad text har en negativ effekt på läsupplevelsen, och att detta kan bero på studenters ovana vid det formatet. Digital text är därmed att föredra för studenters läsning.
Universities and colleges recommend great amounts of student litterature digitally, which can be represented in different formats. Either as scanned from a book (incongruent reading), where the text can not be manipulated, or as digital text (congruent reading) where the text is produced for a digital purpose and can be manipulated to its preferable appearance (font, size etc). Furthermore, digital text enables the reader to use tools such as highlighters and markers. Earlier studies indicate that usage of such tools during reading is beneficial for the student reading performance. The results from previous research about reading rate are not cohesive, and non existant for incongruent reading situations. This study aimed to investigate whether different digital presentations of text (i.e., scanned and digital text) have an influence on students’ reading rate and their perception of the reading. Two academic texts in both digital and scanned format provided the basis for this study where the disparity of the reading rate and perception, between two groups who read on one format each, where analyzed. The results of this study showed no significant difference in reading rate between the formats. However, there were substantial differences in the perception of reading, where digital text was preferred, both regarding the available tools and the appearance of the text. The results regarding perception were in alignment with previous research in this field, and confirmed that experience and student comfort with a format affects the perception of reading on that format. Results also indicated an unexpected short-term relationship between practicing a format and preferring that format. In summary, this study showed that scanned text has negative effects on the perception of the reading, and that this might be a consequence of students lacking experience with this format. Digital text is hence the preferred format for student reading situations.
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Niewenhuis, Benjamin T. "A Logic Test Chip for Optimal Test and Diagnosis." Research Showcase @ CMU, 2018. http://repository.cmu.edu/dissertations/1176.

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The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. The CM-LCV utilizes a two- dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Properties including fault coverage, logical and physical design features, and fault distinguishability are shown to be composable within the FUB array; that is, they exist regardless of the size and composition of the FUB array. A synthesis ow that leverages this composability to adapt the FUB array to a wide range of test chip design requirements is presented. The connection between the innovative FUB functionality and orthogonal Latin squares is identified and used to analyze the universe of possible FUB functions. Two additional variants to the FUB array are also developed: heterogenous FUB arrays utilize multiple FUB functions to improve the synthesis ow performance, while pipelined FUB arrays incorporate sequential circuit elements (e.g., ip- ops and latches) that are absent from the original combinational FUB array. In addition to the design of the CM-LCV, methods for testing it are presented. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the FUB array are developed. Additional constraints are described for the heterogenous and pipelined FUB arrays that allow these techniques to be applied for both variant FUB arrays. Furthermore, a simple built-in self test (BIST) scheme is described and applied to a reference design, resulting in a 88.0% reduction in the number of test cycles required without loss in fault coverage. A hierarchical FUB array diagnosis methodology (HFAD) is also presented for the CM- LCV that leverages its unique properties to improve performance for multiple defects. Experiments demonstrate that this HFAD methodology is capable of perfect accuracy in 93.1% of simulations with two injected faults, an improvement on the state-of-the-art commercial diagnosis. Additionally, silicon fail data was collected from a CM-LCV manufactured using a 14nm process by an industry partner. A comparison of the diagnosis results for the 1,375 fail logs examined shows that the HFAD methodology discovers additional defects during multiple defect diagnosis that the commercial tool misses for 40 of the diagnosed fail logs. Examination of these cases shows that the additional defects found by the HFAD methodology can result in improved diagnosis confidence and more precise descriptions of the defect behavior(s). The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning during process development. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes. All of these claims are validated through both simulated experiments and silicon data.
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Leite, Rogerio Lara. "Utilização de equipamentos automaticos de teste em circuitos integrados digitais." [s.n.], 1994. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259330.

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Orientador: Jose Antonio Siqueira Dias
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica
Made available in DSpace on 2018-07-19T16:00:39Z (GMT). No. of bitstreams: 1 Leite_RogerioLara_M.pdf: 681548 bytes, checksum: 4d0c0a495d19d9b6c369eb38102a2ce4 (MD5) Previous issue date: 1994
Resumo: Este trabalho comenta alguns aspectos importantes do teste automático de um cir­ cuito integrado digital. Apresenta os principais tipos de testes elétricos realizados por um equipamento automático de teste, comentando as diferenças dos testes dependendo da tecnologia do componente, nas diversas fases da vida de um circuito integrado digital. São descritos, de forma suscinta, os principais mecanismos de falhas em CI's digitais e são apresentadas as principais medições elétricas necessárias para avaliar o desempenho de um circuito integrado. Descrevemos também o equipamento automático de teste (ATE) e sua linguagem de programação, comentando como esta máquina é im­portante para testar circuitos integrados digitais. O trabalho termina com dois programas de teste reais, escritos em Pascal, comentando os resultados das medições de cada programa
Abstract: This work comments some important aspects of the digital integrated circuit auto­matic test. It presents the most common electrical tests done by an Automatic Test Equipment - ATE. The test differences depending on chip technology in the various steps of the integrated circuit life are commented. The main IC's digital faults and failures mechanisms are commented in a introductory way. The principal electrical measurements necessary to estimate the performance of an digital IC¿s presented. The architecture and the language of the ATE is presented , discussing how this machine is important to test digital integrated circuits. The work ends with two real test programs, written in Pascal commenting the results of the measurements of each test program
Mestrado
Mestre em Engenharia Elétrica
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8

Loeblein, James T. "A digital hardware test system analysis with test vector translation." Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/23643.

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Approved for public release; distribution is unlimited
Digital logic testing occurs in two different test environments, digital simulation and actual hardware testing. A computer aided design (CAD) tool applies a set of stimulus/response test vector patterns to check the functionality of a digital circuit design. Once manufactured, the chip with this design is tested by a hardware tester system (i.e. automatic test equipment (ATE)). The ATE performs many tests in addition to the functionality test. However the stimulus/response test vector formats used in these two environments are different and, therefore, incompatible in present form. This thesis is aimed at two major objectives. first, a system study will be performed on the GenRad-125 VLSI Hardware Tester System, including its usage, test capabilities and limitations. Secondly, this thesis addresses the problem of test vector format incompatibility between the two testing environments. Special UNIX tools, Lex and Yacc, are used to create a software translator which changes the CAD simulation file into the GenRad-125 Hardware Test System format.
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9

Traiola, Marcello. "TEST TECHNIQUES FOR APPROXIMATE DIGITAL CIRCUITS." Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS060.

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Au cours des dernières décennies, la demande d’efficacité informatique n’a cessé de croître. L’affirmation d’applications de nouvelle génération consommatrices d’énergie d’un côté, et d’appareils portables basse consommation de l’autre, exige un nouveau paradigme informatique capable de faire face aux exigences concurrentes des défis technologiques actuels. Ces dernières années, plusieurs études sur les applications dites de "Recognition, Mining and Synthesis (RMS)" ont été menées. Une particularité très intéressante a été identifiée : la résilience intrinsèque de ces applications. Une telle propriété permet aux applications RMS d’être très tolérantes aux erreurs. Ceci est dû à différents facteurs, tels que les données bruyantes traitées par ces applications, les algorithmes non déterministes utilisés et les réponses non uniques possibles. Ces propriétés ont été exploitées par un nouveau paradigme informatique de plus en plus établi : le calcul approximé (AxC). L’AxC profite intelligemment de la résilience intrinsèque des applications RMS pour réaliser des gains en termes de consommation électrique, de temps de fonctionnement et/ou de surface de puce. En effet, en introduisant des assouplissants sélectifs des spécifications non critiques, certaines parties du système informatique cible peuvent être simplifiées, pour finalement atteindre l’objectif de l’AxC. De plus, l’AxC est capable de cibler différentes couches des systèmes informatiques, du matériel au logiciel. Dans cette thèse, nous nous concentrons sur les circuits intégrés approximés (AxICs) qui sont le résultat de l’application AxC au niveau matériel. En particulier, nous nous concentrons sur l’approximation fonctionnelle des circuits intégrés, utilisée au cours des dernières années afin de concevoir efficacement les AxICs. En raison de la pertinence croissante des AxICs, il devient important de relever les nouveaux défis pour tester de tels circuits. À cet égard, certains travaux ont attiré l’attention sur les défis que représente l’approximation fonctionnelle pour les procédures de test. En même temps, l’approximation fonctionnelle des circuits intégrés offre également des possibilités. Plus en détails - d’une part - le concept de circuit acceptable change : alors qu’un circuit est conventionnellement bon si ses réponses ne sont jamais différentes de celles attendues, dans le contexte AxIC certaines réponses inattendues peuvent encore être acceptables. Pour la même raison - d’autre part - certaines fautes acceptables peuvent ne pas être détectées, ce qui mène à un gain de rendement de production (c.-à-d., augmentation du pourcentage de circuits acceptables, parmi tous les circuits fabriqués). Pour mesurer l’erreur produite par un AxIC, plusieurs métriques d’erreur ont été proposées dans la littérature. Dans cette thèse, nous présentons un ensemble de techniques de test pour les circuits approximés. En particulier, nous nous concentrons sur trois phases fondamentales du déroulement du test. Premièrement, la classification des fautes AxIC en non-redundant et ax-redundant (c.-à-d. catastrophique et acceptable, respectivement) en fonction d’un seuil d’erreur (c.-à-d. la quantité maximale tolérable d’erreur). Cette classification permet d’obtenir deux listes de fautes (c.-à-d. nonredundant et ax-redundant). Ensuite, nous proposons une génération automatique de séquences de test qui soit “consciente de l’approximation”. Les tests obtenus préviennent les défaillances catastrophiques en détectant les fautes non-redundant. En même temps, ils minimisent la détection sur les ax-redundant. Enfin – puisque dans certains cas le gain de rendement obtenu ne correspond toujours pas à celui attendu, à cause de la structure propre des AxICs – nous proposons une technique pour classer correctement les AxICs dans les catégories “catastrophiquement défectueux” et “acceptablement défectueux”, après l’application du test
Despite great improvements of the semiconductor industry in terms of energy efficiency, the computer systems’ energy consumption is constantly growing. Many largely used applications – usually referred to as Recognition, Mining and Synthesis (RMS) applications – are more and more deployed as mobile applications and on Internet of Things (IoT) structures. Therefore, it is mandatory to improve the future silicon devices and architectures on which these applications will run. Inherent resiliency property of RMS applications has been thoroughly investigated over the last few years. This interesting property leads applications to be tolerant to errors, as long as their results remain close enough to the expected ones. Approximate Computing (AxC) , is an emerging computing paradigm which takes advantages of this property. AxC has gained increasing interest in the scientific community in last years. It is based on the intuitive observation that introducing selective relaxation of non-critical specifications may lead to efficiency gains in terms of power consumption, run time, and/or chip area. So far, AxC has been applied on the whole digital system stack, from hardware to application level. This work focuses on approximate integrated circuits (AxICs), which are the result of AxC application at hardware-level. Functional approximation has been successfully applied to integrated circuits (ICs) in order to efficiently design AxICs. Specifically, we focus on testing aspects of functionally approximate ICs. In fact – since approximation changes the functional behavior of ICs – techniques to test them have to be revisited. In fact, some previous works – have shown that circuit approximation brings along some challenges for testing procedures, but also some opportunities. In particular, approximation procedures intrinsically lead the circuit to produce errors, which have to be taken into account in test procedures. Error can be measured according to different error metrics. On the one hand, the occurrence of a defect in the circuit can lead it to produce unexpected catastrophic errors. On the other hand, some defects can be tolerated, when they do not induce errors over a certain threshold. This phenomenon could lead to a yield increase, if properly investigated and managed. To deal with such aspects, conventional test flow should be revisited. Therefore, we introduce Approximation-Aware testing (AxA testing). We identify three main AxA testing phases: (i) AxA fault classification, (ii) AxA test pattern generation and (iii) AxA test set application. Briefly, the first phase has to classify faults into catastrophic and acceptable; the test pattern generation has to produce test vectors able to cover all the catastrophic faults and, at the same time, to leave acceptable faults undetected; finally, the test set application needs to correctly classify AxICs under test into catastrophically faulty, acceptably faulty, fault-free. Only AxICs falling into the first group will be rejected. In this thesis, we thoroughly discuss the three phases of AxA testing, and we present a set of AxA test techniques for approximate circuits. Firstly, we work on the classification of AxIC faults into catastrophic and acceptable according to an error threshold (i.e. the maximum tolerable amount of error). This classification provides two lists of faults (i.e. catastrophic and acceptable). Then, we propose an approximation-aware (ax-aware) Automatic Test Pattern Generation. Obtained test patterns prevent catastrophic failures by detecting catastrophic defects. At the same time, they minimize the detection of acceptable ones. Finally – since the AxIC structure often leads to a yield gain lower than expected – we propose a technique to correctly classify AxICs into “catastrophically faulty”, “acceptably faulty”, “and fault-free”, after the test application. To evaluate the proposed techniques, we perform extensive experiments on state-ofthe-art AxICs
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Jervan, Gert. "Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems." Doctoral thesis, Linköping : Dept. of Computer and Information Science, Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2994.

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Books on the topic "Test digitali"

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Cortner, J. Max. Digital test engineering. New York: Wiley, 1987.

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Loeblein, James T. A digital hardware test system analysis with test vector translation. Monterey, Calif: Naval Postgraduate School, 1992.

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Navabi, Zainalabedin. Digital System Test and Testable Design. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-1-4419-7548-5.

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North Atlantic Treaty Organization. Advisory Group for Aerospace Research and Development., ed. Digital signal conditioning for flight test. Neuilly sur Seine, France: AGARD, 1991.

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North Atlantic Treaty Organization. Advisory Group for Aerospace Research and Development. Digital signal conditioning for flight test. Neuilly-sur-Seine: AGARD, 1991.

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Bever, G. A. Digital signal conditioning for flight test. Neuilly sur Seine: Agard, 1991.

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Wojtkowiak, Hans. Test und Testbarkeit digitaler Schaltungen. Wiesbaden: Vieweg+Teubner Verlag, 1988. http://dx.doi.org/10.1007/978-3-322-96665-0.

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Wojtkowiak, Hans. Test und Testbarkeit digitaler Schaltungen. Stuttgart: B.G. Teubner, 1988.

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CTL for test information of digital ICs. Boston: Kluwer Academic Publishers, 2003.

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Facility, Dryden Flight Research, ed. Digital signal conditioning for flight test instrumentation. Edwards, Calif: NASA Ames Resarch Center, Dryden Flight Research Facility, 1991.

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Book chapters on the topic "Test digitali"

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Ravichandran, Aruna, Kieran Taylor, and Peter Waterhouse. "Test." In DevOps for Digital Leaders, 69–85. Berkeley, CA: Apress, 2016. http://dx.doi.org/10.1007/978-1-4842-1842-6_5.

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Turino, Jon L. "General Digital Circuit Guidelines." In Design to Test, 35–64. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-011-6044-5_3.

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Walrand, Jean. "Digital Link—B." In Probability in Electrical Engineering and Computer Science, 143–62. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-49995-2_8.

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AbstractChapter 7 explained the detection and hypothesis testing problems, Huffman codes and the situation where errors are independent and Gaussian. In this chapter, we prove the optimality of the Huffman code in Sect. 8.1 and the Neyman–Pearson Theorem in Sect. 8.2. Section 8.3 discusses the theory of jointly Gaussian random variables that is used to analyze the modulation schemes of Sect. 7.5 . Section 8.4 uses the results on jointly Gaussian random variables to explain hypothesis tests that arise when analyzing data. That section discusses the chi-squared test and the F-test. Section 8.5 is devoted to the LDPC codes that are widely used in high-speed communication links. These codes augment a group of bits to be transmitted over a noisy channel with additional bits computed from those in the group. When it receives the bits, when the augmented bits are not consistent, the receiver attempts to determine the bits that are most likely to have been corrupted by noise.
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Navabi, Zainalabedin. "Test Compression." In Digital System Test and Testable Design, 345–73. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_10.

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Nematollahi, Mohammad Ali, Chalee Vorakulpipat, and Hamurabi Gamboa Rosales. "Text Watermarking." In Digital Watermarking, 121–29. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-2095-7_8.

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Cavalli, Nicola. "Il testo digitale." In eReaders ed eBooks nelle università, 9–23. Milano: Springer Milan, 2012. http://dx.doi.org/10.1007/978-88-470-2528-8_2.

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Sánchez, Pablo, and Víctor Fernández. "Test Synthesis of Digital Systems." In Advanced Techniques for Embedded Systems Design and Test, 201–30. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-4419-4_9.

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Maichen, Wolfgang. "High-Speed Digital Test Interfaces." In Gizopoulos / Advances in ElectronicTesting, 141–78. Boston, MA: Springer US, 2006. http://dx.doi.org/10.1007/0-387-29409-0_5.

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Beenker, F. P. M., R. G. Bennetts, and A. P. Thijssen. "Test Control Block Concepts." In Testability Concepts for Digital ICs, 107–38. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2365-9_6.

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Chakradhar, Srimat T., Vishwani D. Agrawal, and Michael L. Bushneil. "Test Generation Reformulated." In Neural Models and Algorithms for Digital Testing, 51–55. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3958-2_6.

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Conference papers on the topic "Test digitali"

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John, Varghese Mangalathu, Jose Selvaraj Edwin, Prakash Madhukar Nandwalkar, Raju Paul, and Faris Ragheb Kamal. "Virtual Remote Factory Acceptance Test." In Abu Dhabi International Petroleum Exhibition & Conference. SPE, 2021. http://dx.doi.org/10.2118/208167-ms.

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Abstract Many of the well-established practices and procedures those were followed in the execution of Oil & Gas Industry Projects were seeing a shift towards digital transformation in recent years, which got accelerated due to the Covid-19 pandemic. Digital transformation is the adoption of digital technologies whereby the existing business processes are modified or new ones are created. This process of redefining the conventional procedures, culture and customer experience to meet the changing requirements benefit the overall business function. Redefining the process of business in the digital age is digital transformation. Digital transformation in Oil & Gas Industry is embracing of technology to reshape how oil and gas companies manage and operate their assets. The digitally-enabled and data-centric approach leads to improved productivity, higher efficiency and increased cost savings. One of the Process Transformation example in Oil & Gas sector is to conduct the Factory Inspection and Acceptance Tests remotely utilizing various digital tools available in this digital age instead of the conventional way of physical participation in the testing. Many industries were already exploring the possibilities of non-conventional work practices such as Work from Home (remotely, away from office), conducting virtual meetings with remotely located participants. These practices were still not accepted in all the industries prior to 2020. However the outbreak of Covid-19 pandemic worldwide created a need to accept these non-conventional practices of remote or virtual work. Post Covid (2020), these are widely accepted in most of the industries including Oil & Gas sector. The concept of Virtual Remote Factory Acceptance Test (FAT) is explored to overcome the unforeseen situation arose due to worldwide Covid-19 outbreak. Travel restrictions were imposed worldwide to curb the covid-19 spread, which made a halt to the normal work practices followed till then. Virtual Remote FAT is a successful alternative to the conventional way of conducting the FAT and was utilized during Covid-19 outbreak. Virtual remote FAT is successfully completed in some of the recently executed projects and this can be pursued even after the Covid crisis.
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Rivoir, Jochen. "Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration." In 2006 IEEE International Test Conference. IEEE, 2006. http://dx.doi.org/10.1109/test.2006.297713.

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Melikyan, Vazgen, Aristakes Hovsepyan, Mkrtich Ishkhanyan, and Tigran Hakobyan. "Digital lock detector for PLL." In Test Symposium (EWDTS). IEEE, 2008. http://dx.doi.org/10.1109/ewdts.2008.5580147.

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Vdovychenko, Yegor I. "FPGA-based digital phase difference meter." In Test Symposium (EWDTS). IEEE, 2010. http://dx.doi.org/10.1109/ewdts.2010.5742049.

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Ichiyama, Kiyotaka, Masahiro Ishida, Kenichi Nagatani, and Toshifumi Watanabe. "A functional test of 2-GHz/4-GHz RF digital communication device using digital tester." In 2013 IEEE International Test Conference (ITC). IEEE, 2013. http://dx.doi.org/10.1109/test.2013.6651909.

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Tao Xu and Krishnendu Chakrabarty. "Functional testing of digital microfluidic biochips." In 2007 IEEE International Test Conference. IEEE, 2007. http://dx.doi.org/10.1109/test.2007.4437614.

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Ferry, Joshua. "FPGA-based universal embedded digital instrument." In 2013 IEEE International Test Conference (ITC). IEEE, 2013. http://dx.doi.org/10.1109/test.2013.6651917.

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Okawara, Hideo. "eRNA: Refining of reconstructed digital waveform." In 2015 IEEE International Test Conference (ITC). IEEE, 2015. http://dx.doi.org/10.1109/test.2015.7342392.

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Siyad C. Ma and E. J. McCluskey. "Non-conventional faults in BiCMOS digital circuits." In Proceedings International Test Conference 1992. IEEE, 1992. http://dx.doi.org/10.1109/test.1992.527914.

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Ecker, Allan, Ken Blakkan, and Mani Soma. "A digital method for phase noise measurement." In 2012 IEEE International Test Conference (ITC). IEEE, 2012. http://dx.doi.org/10.1109/test.2012.6401537.

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Reports on the topic "Test digitali"

1

Hartmann, Carlos R., and Dennis C. Shiau. Digital Test Generation using Multiprocessing. Fort Belvoir, VA: Defense Technical Information Center, September 1995. http://dx.doi.org/10.21236/ada299902.

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Markley, R. E., J. L. Elarton, and C. T. Allen. High-speed digital project, HSD test capability. Office of Scientific and Technical Information (OSTI), April 1994. http://dx.doi.org/10.2172/10146570.

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HOWARD, BOYD. DIGITAL RADIOGRAPHY OF SPECIAL NUCLEAR MATERIAL TEST PACKAGES. Office of Scientific and Technical Information (OSTI), February 2006. http://dx.doi.org/10.2172/890212.

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Byron, B. D. ,. Westinghouse Hanford. Visual Image Digital Object Network (VIDON) operations test report. Office of Scientific and Technical Information (OSTI), July 1996. http://dx.doi.org/10.2172/296584.

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Byron, B. D. ,. Westinghouse Hanford. Visual Image Digital Object Network (VIDON) operations test plan. Office of Scientific and Technical Information (OSTI), July 1996. http://dx.doi.org/10.2172/325146.

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Kromer, Richard Paul, Darren M. Hart, and James Mark Harris. Test definitions for the evaluation of digital waveform recorders. Office of Scientific and Technical Information (OSTI), July 2007. http://dx.doi.org/10.2172/921714.

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Baral, Aniruddha, Jeffrey Roesler, M. Ley, Shinhyu Kang, Loren Emerson, Zane Lloyd, Braden Boyd, and Marllon Cook. High-volume Fly Ash Concrete for Pavements Findings: Volume 1. Illinois Center for Transportation, September 2021. http://dx.doi.org/10.36501/0197-9191/21-030.

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Abstract:
High-volume fly ash concrete (HVFAC) has improved durability and sustainability properties at a lower cost than conventional concrete, but its early-age properties like strength gain, setting time, and air entrainment can present challenges for application to concrete pavements. This research report helps with the implementation of HVFAC for pavement applications by providing guidelines for HVFAC mix design, testing protocols, and new tools for better quality control of HVFAC properties. Calorimeter tests were performed to evaluate the effects of fly ash sources, cement–fly ash interactions, chemical admixtures, and limestone replacement on the setting times and hydration reaction of HVFAC. To better target the initial air-entraining agent dosage for HVFAC, a calibration curve between air-entraining dosage for achieving 6% air content and fly ash foam index test has been developed. Further, a digital foam index test was developed to make this test more consistent across different labs and operators. For a more rapid prediction of hardened HVFAC properties, such as compressive strength, resistivity, and diffusion coefficient, an oxide-based particle model was developed. An HVFAC field test section was also constructed to demonstrate the implementation of a noncontact ultrasonic device for determining the final set time and ideal time to initiate saw cutting. Additionally, a maturity method was successfully implemented that estimates the in-place compressive strength of HVFAC through wireless thermal sensors. An HVFAC mix design procedure using the tools developed in this project such as the calorimeter test, foam index test, and particle-based model was proposed to assist engineers in implementing HVFAC pavements.
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Green, John, and Tim Robinson. Test Equipment and Method to Characterize a SWIR Digital Imaging System. Fort Belvoir, VA: Defense Technical Information Center, June 2014. http://dx.doi.org/10.21236/ada605295.

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Wahl, Ronald R., David A. Sawyer, Scott A. Minor, Michael D. Carr, James C. Cole, W. C. Swadley, Randell J. Laczniak, Richard G. Warren, Katryn S. Green, and Colin M. Engle. Digital geologic map database of the Nevada Test Site area, Nevada. Office of Scientific and Technical Information (OSTI), September 1997. http://dx.doi.org/10.2172/833900.

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Leedy, T. F., K. J. Lentner, O. B. Laug, and B. A. Bell. Electrical performance tests for hand-held digital multimeters. Gaithersburg, MD: National Institute of Standards and Technology, 1989. http://dx.doi.org/10.6028/nist.ir.88-4021.

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