Dissertations / Theses on the topic 'Technologie III-V'
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Fawaz, Hussein. "Technologie multifonction de transistors à effet de champ sur matériaux III-V pour logique rapide et hyperfréquences." Lille 1, 1993. http://www.theses.fr/1993LIL10038.
Callen, Olivier. "Nouvelle méthode d'investigation par effet Hall des états d'interface dans les composants à base d'hétérostructures III-V." Montpellier 2, 2000. http://www.theses.fr/2000MON20029.
Le, Pallec Michel. "Technologie de photorécepteurs intégrés sur InP." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0144.
Ung, Thuy Dieu Thi. "SYNTHÈSE ET CARACTÉRISATION DE NANOCRISTAUX COLLOÏDAUX DE SEMI-CONDUCTEURS III-V DOPÉS PAR DES TERRES RARES." Phd thesis, Grenoble, 2010. http://tel.archives-ouvertes.fr/tel-00626513.
Sciancalepore, Corrado. "Intégration hétérogène III-V sur silicium de microlasers à émission par la surface à base de cristaux photoniques." Phd thesis, Ecole Centrale de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00915280.
Mbow, Babacar. "Etude des réponses spectrales dans le proche infra-rouge des composés mixtes III-V, ternaires et quaternaires, à base de GaSb et de leurs dérivés." Montpellier 2, 1992. http://www.theses.fr/1992MON20048.
Bringer, Charlotte. "Technologie et caractérisation des VCSELs à diaphragme d'oxyde : application à la détection en cavité verticale." Toulouse 3, 2005. http://www.theses.fr/2005TOU30008.
This work deals with the fabrication and the characterization of buried oxide-confined vertical-cavity surface-emitting lasers (VCSELs AlOx) for emission at 850 nm. We first focus on the structure design and on the fabrication steps. Optical and electrical measurements show the improvements of the VCSELs characteristics and allow for identify current limitations. Further, we explain the principle of resonant cavity enhanced detector and then describe each detailed vertical geometry: single photodetector, standard VCSEL and BiVCSEL. Measured spectral behaviors on each device are show and discussed. Last part deals with lateral integrated detection owing the optical waveguiding of spontaneous emission between neighboting VCSELs sharing the same cavity. The main application of this new detection system concerns the VCSEL power monitoring
BRINGER, Charlotte. "Technologie et caractérisation des VCSELs à diaphragme d'oxyde. Application à la détection en cavité verticale." Phd thesis, Université Paul Sabatier - Toulouse III, 2005. http://tel.archives-ouvertes.fr/tel-00010239.
Bouguen, Laure. "Annulation de la dérive thermique de capteurs magnétiques à base d'hétérostructures pseudomorphiques AlGaAs/InGaAs/GaAs." Montpellier 2, 2009. http://www.theses.fr/2009MON20075.
The goal of this work was to decrease, and even cancel, the thermal drift of magnetic sensors based on pseudomorphic AlGaAs/InGaAs/GaAs heterojunction. For that, the chosen solution consisted in controlling the Fermi level pinning at the surface of existing heterojunction. This control has been done by the addition of a gate with different geometries and with a suitable polarisation. We showed that an one dimensional model was not adapted and that it was necessary to do a two dimensional analysis with the finite element method witch explain the results obtained
Bouillaud, Hugo. "Fabrication et optimisation des caractéristiques thermiques de diodes Schottky de la filière GaAs et reportées sur SiHR pour des applications de multiplication de fréquences." Electronic Thesis or Diss., Université de Lille (2022-....), 2023. http://www.theses.fr/2023ULILN043.
The exponential needs associated with applications exploiting the THz domain require to expand the range of available sources and optimize their fabrication processes. In this thesis, we focused on schottky diodes for its use as frequency multipliers. Our experimental research involved optimizing the characteristics of GaAs schottky diodes through the development and implementation of an innovative fabrication process. First, we fabricated GaAs schottky diodes on GaAs substrate with several aspect ratios in order to make a reference in terms of device. Then we fabricated a flip-chip device for a 150 GHz frequency multiplication application in a waveguide block. Finally, in order to enhance the power handling of the diodes, we optimized their thermal dissipation by transferring their epitaxial structure onto a substrate with higher thermal conductivity : SiHR (high resistivity silicon). The complete technological processes for these fabrications are detailed, and the last part of the study is dedicated to their characterization. On one hand, we assessed any variations in the characteristics of GaAs diodes on GaAs induced by the different aspect ratios. On the other hand, we compared the two technologies on SiHR and GaAs substrates. This work demonstrates the potential of this type of transferred technology, where a significant reduction of thermal resistance is observed and is associated with a notable improvement of the series resistance
Salzenstein, Patrice. "Technologie des composants à hétérostructures pour les têtes de réception par satellite aux longueurs d'ondes millimétriques." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 1996. http://tel.archives-ouvertes.fr/tel-00077055.
Pour les dispositifs actifs, le composant développé est une hétérostructure à simple barrière qui présente des non-linéarités en capacité extrêmement marquées utilisables dans les multiplicateurs de fréquences. Par rapport aux dispositifs Schottky varactors conventionnels, les hétérostructures permettent de tirer parti de propriétés de symétrie et d'optimiser et d'optimiser au mieux les caractéristiques des courants de déplacement et de conduction. En pratique, les composants sont fabriqués à partir de multiples hétérostructures épitaxiées par jets moléculaires sur substrat InP mettant en jeu des techniques d'intégration monolithiques. Plusieurs séries d'échantillons ont été fabriquées avec pour les dernières structures des résultats à l'état de l'art, notamment avec la possibilité de moduler la capacité dans un rapport 5 en tenue en tension de plus de 6 Volt favorable aux applications de puissance. dans cette optique, nous démontrons par ailleurs la possibilité d'intégrer verticalement plusieurs composants sur une même épitaxie.
Pour les structures passives, elles sont constituées de lignes coplanaires déposées sur membrane de polyimide ou de nitrure de silicium. Dans ces conditions le milieu de propagation peut se comparer à l'air avec une permittivité effective très proche de celle obtenue dans l'espace libre. De telles structures ont été fabriquées en utilisant des technologies de micro-usinage de l'Arséniure de Gallium. Les résultats des caractérisations hyperfréquences sont conformes aux prédictions théoriques, avec la propagation faible perte de l'énergie électromagnétique sans dispersion dans une très large bande de fréquence. Ces études sont ensuite étendues à la conception de structures de filtrage aux fréquences millimétriques, notamment à 250 GHz.
Amat, Cédric. "Technologie et caractérisation de VCSELs à détection intégrée pour applications aux communications optiques et à l'instrumentation." Phd thesis, Université Paul Sabatier - Toulouse III, 2007. http://tel.archives-ouvertes.fr/tel-00157963.
Lee, Sang-Goog. "Réalisation et caractérisation d'un capteur magnétique en couche mince." Rouen, 1994. http://www.theses.fr/1994ROUES050.
Naureen, Shagufta. "Top-down Fabrication Technologies for High Quality III-V Nanostructures." Doctoral thesis, KTH, Halvledarmaterial, HMA, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-117766.
QC 20130205
Moran, David A. J. "Self-aligned short gate length III-V HEMT technology." Thesis, University of Glasgow, 2004. http://theses.gla.ac.uk/6577/.
Green, Richard Philip. "Physics and technology of Intersubband transitions in III-V semiconductor heterostructures." Thesis, University of Sheffield, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.419619.
Pirro, Luca. "Caractérisation et modélisation électrique de substrats SOI avancés." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT096/document.
Silicon-on-insulator (SOI) substrates represent the best solution to achieve high performance devices. Electrical characterization methods are required to monitor the material quality before full transistor fabrication. The classical configuration used for SOI measurements is the pseudo-MOSFET. In this thesis, we focused on the enrichment of techniques in Ψ-MOSFET for the characterization of bare SOI and III-V wafers. The experimental setup for static ID-VG was improved using a vacuum contact for the back gate, increasing the measurement stability. Furthermore, this contact proved to be critical for achieving correct capacitance values with split-CV and quasi-static techniques (QSCV). We addressed the possibility to extract Dit values from split-CV and we demonstrated by modeling that it is impossible in typical sized SOI samples because of the time constant associated to the channel formation. The limitation was solved performing QSCV measurements. Dit signature was experimentally evidenced and physically described. Several SOI structures (thick and ultra-thin silicon films and BOX) were characterized. In case of passivated samples, the QSCV is mostly sensitive to the silicon film-BOX interface. In non-passivated wafers, a large defect related peak appears at constant energy value, independently of the film thickness; it is associated to the native oxide present on the silicon surface. For low-frequency noise measurements, a physical model proved that the signal arises from localized regions surrounding the source and drain contacts
Dupuis, Olivier. "Technologies et caractérisation hautes fréquences de composants III-V à effet tunnel résonnant." Lille 1, 1999. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/1999/50376-1999-381.pdf.
Pacella, Nan Yang. "Platform for monolithic integration of III-V devices with Si CMOS technology." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/76119.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 169-165).
Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures.
by Nan Yang Pacella.
Ph.D.
Boyd, Euan James. "Development of advanced technologies for the fabrication of III-V high electron mobility transistors." Thesis, University of Glasgow, 2004. http://theses.gla.ac.uk/5381/.
Dohrman, Carl Lawrence. "Substrate engineering for monolithic integration of III-V semiconductors with Si CMOS technology." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/44323.
Includes bibliographical references (p. 165-172).
Ge virtual substrates, fabricated using Si1-xGex-.Ge, compositionally graded buffers, enable the epitaxial growth of device-quality GaAs on Si substrates, but monolithic integration of III-V semiconductors with Si CMOS using this platform is hampered by the large thickness of the Si1-xGex graded region. To address this issue, the Silicon on Lattice-engineered Silicon (SOLES) was developed, consisting of a silicon-on-insulator (SOI) structure fabricated on a Ge virtual substrate. Placement of the Si device layer at the surface makes it possible to process this platform similarly to typical SOI wafers, with the added functionality of a buried III-V template which can be used for GaAs device fabrication. This platform was fabricated using a scalable layer transfer technique. AlInGaP LEDs were also demonstrated on a SOLES substrate. In addition, an alternative growth process was investigated for Si1-xGex virtual substrates with lower threading dislocation density (TDD) and thickness. This process, the thermally relaxed ultra-thin (TRUT) buffer process, consists of coherent growth of lattice-mismatched Si1.xGex layers, followed by post-growth annealing. Growth of TRUT buffers over the Si0.5Ge0.5 to Si0.3Ge0.7 alloy range with high strain levels resulted in the nucleation of surface defects which appear to limit the maximum strain rate of compositionally graded buffers. However, application of the TRUT process in the Si0.1Ge0.9 to Ge alloy range resulted in relaxed Ge virtual substrates with a 59% reduction in TDD compared to conventional processes. Lastly, growth of high-quality lattice-matched GaAsyP1.y on Si0.5Ge0.5, Si0.3Geo.7, and Si0.2Ge0.8 virtual substrates was investigated.
(cont.) Adaptation of standard GaAs on Ge processes to this heteroepitaxial system resulted in mostly non-planar growth (similar to typical GaP growth on Si) with only limited regions of planar GaAsyP1-y layers on Si0.2Ge0.8 virtual substrates. Planar growth of GaAsyP1-y on Si0.3Ge0.7 virtual substrates was enabled by minimizing the atmospheric exposure of the Si0.3Ge0.7 as it is transferred between growth reactors, establishing that the GaAsyP1-y growth process on Si1-xGex is strongly affected by atmospheric contaminants. Further minimization of air exposure, through use of Si1-xGex homoepitaxial buffers and growth of Si1-xGex and GaAsyP1-y in a single reactor, is expected to further improve epitaxial quality across the entire lattice-matched GaAsyP1-y/Si1-xGex range, including GaP on Si.
by Carl Lawrence Dohrman.
Ph.D.
Perkins, James Michael 1978. "Magnetically assisted statistical assembly of III-V heterostructures on silicon : initial process and technology development." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/32712.
Includes bibliographical references (leaf 75).
This work is the initial investigation of magnetically assisted statistical assembly (MASA), a novel silicon I-v integration technique developed at M.I.T. Initially procedures for processing optoelectronic devices into magnetically sensitive 40 micron discs were performed and refined. Cobalt palladium thin films were obtained and their magnetic properties were studied. An initial procedure was developed to easily integrate these patterned, magnetized films with 60-micron diameter, 5-micron deep recesses. Pill devices were then integrated into these magnetically attractive recesses. The studied showed optoelectronic pills with magnetic layers could be successfully produced and collected. Assembly using these pills was performed and showed improved recess filling yields over the non-magnetic assembly, though more investigation needs to be done. MASA was shown to offer promise as a viable and promising technique for mixed device integration.
by James Michael Perkins.
S.M.
Medjoubi, Karim. "Investigation of new solar cell technology III-V//Si behavior under irradiations for space applications." Thesis, Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAX004.
This work focuses on the behavior in space environment of a new photovoltaic solar cell technology: the III-V//Si tandems (2- and 3-junction), obtained by direct bonding. These cells have been exposed to electron and proton irradiations and tested in two types of environment: a) normal irradiance, 1 sun, and 300K room temperature, NIRT condition (Earth orbits) and b) low irradiance, 0.03 sun, and 120K low temperature, LILT condition (deep space). In a preliminary stage, a comparative study was conducted on 2 solar simulators, respectively equipped with a flash lamp and LED lamps, in order to ensure the reliability and reproducibility of the measurements of these multi-junctions. For the flash simulator, a tandems characterization method for I-V under 1 sun that dispense the use of isotype reference cells has been adopted, based on EQE and flash spectrum measurements. For the LED simulator, mounted in-situ on the irradiation beam, a spectrum optimization was performed in order to approach the low irradiance reference, i.e. ~3% AM0. This comparative study also allowed to establish the validity of the extrapolation by calculating I-V measurements under 1 sun towards low irradiances.Then, the compatibility of this tandem III-V//Si technology with thermal cycling on the one hand and irradiances on the other hand has been demonstrated. The bonding interface maintains its mechanical and electrical integrity face to these constraints. The impact of the irradiations on the cell performances has revealed certain similarities at 300 K and 120 K: - a marked decrease in the short-circuit current (linked to the decrease in the diffusion length) - a smaller decrease in the open-circuit voltage (generation type defects). Due to the series connection of the sub-cells, the degradation of the limiting Si (low intrinsic resistance to irradiation) dominates the behavior of the multi-junction. It has been shown that the addition of an increasing number of cells on the Si results in an increased sensitivity to irradiation; indeed, the tandem configuration restricts the absorption band of the Si to the near infrared, the spectral part most affected by the decrease in diffusion length. The use of a model based on the IQE allowed the qualification of this diffusion length degradation of the Si in tandem, as well as the damage coefficient. Unlike electrons, 1 MeV proton irradiations are at the origin of a non-homogeneous degradation in Si; by EQE measurements coupled with simulation, we have correlated this non-homogeneous degradation in Si with the position of the corresponding Bragg peak.For the low-temperature study, a linear increase in efficiency was observed up to ~150K; and below this, anomalies of I V characteristics were detected; of "S-like shape" and "flat spot" type, these defects affect the FF and thus the efficiency. Reported in the literature, these effects are characteristic of LILT conditions, and are often related to changes in the metal/semiconductor interfaces. Although significant, the LILT end-of-life electrical performance degradation of III-V//Si has been shown to be more predictable than that of III-V/Ge LILT (statistical dispersion). We have also shown that a 300 K annealing after irradiation at 120 K leads to a marked healing of the short-circuit current; this underlines the importance of in-situ characterizations to quantify cell aging under operating conditions. The Displacement Damage Dose (DDD) approach was applied for 1 MeV electrons and protons in order to compare the rate of induced degradation. This approach allows to predict the degradation of these cells whatever the fluence, particles and energy, for a space mission at 300 K
Beaudin, Guillaume. "Nouvelles technologies de fabrication associées aux composants photoniques hybrides." Mémoire, Université de Sherbrooke, 2009. http://savoirs.usherbrooke.ca/handle/11143/1480.
Desplats, Olivier. "Préparation de surfaces structurées et reprise d'épitaxie par jets moléculaires : réalisation de micro et nano structures sur GaAs." Toulouse 3, 2008. http://thesesups.ups-tlse.fr/299/.
Surface patterning and epitaxial regrowth are key technologies for novel optoelectronic (nano) devices. The aim of this thesis has been to develop a preparation of GaAs micro- and nanopatterned surfaces suited for regrowth and to study the organization of InAs quantum dots on these surfaces. The patterns have been achieved by electronic lithography in a cap resist and transferred into GaAs by chemical etching. Surface decontamination by a O2: SF6 micro-wave plasma has been demonstrated. Roughening upon in situ deoxidization has been prevented thanks to a low temperature H plasma treatment. Molecular beam epitaxy on these patterned surfaces has been studied. InAs quantum dots have been grown and lateral ordering has been attained. This preparation method has been shown to be efficient for GaAs selective regrowth on Si3N4/GaAs patterned surfaces
Oszustowicz, Jean-Luc. "Mise au point de technologies adaptées à la réalisation de circuits intégrés monolithiques III-V : application à un circulateur actif en bande X." Lille 1, 1995. http://www.theses.fr/1995LIL10112.
Giudicelli, Emmanuel. "Evaluation d’une filière technologique de cellules photovoltaïques multi-jonctions à base de matériaux antimoniures (III-V)-Sb pour applications aux très fortes concentrations solaires." Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT330/document.
Photovoltaic (PV) solar energy consists on the ability of certain materials to convert the photon energy into electric current. The development of PV conversion systems in the past thirty years has led to considerable improvements in terms of cost and performance in the field of renewable energies.A multi-junction (MJ) cell, based on III-V semiconductor materials, is a stack of sub-cells with decreasing gaps which notably allows wider use of the solar spectrum. Exposing these PV cells to a concentrated solar flux can significantly increase the electrical power generated, and therefore substantially lower the cost of electricity yielded.The world record is currently held by the partnership Soitec / Fraunhofer ISE with an efficiency of 46.0 % measured on a four-junction cell GaInP/GaAs//InGaAsP/InGaAs for a concentration ratio of 508 X (where 1 X = 1 sun = 1 kW/m²).The objective of the work in this thesis is to propose an alternative to existing cells, easier to implement with monolithic MJ cells grown on a GaSb substrate for solar concentrations of 1 000, which corresponds to a direct irradiance of 1 MW/m². This type of cell, due to the good complementary of the material gaps and its favorable band alignments, is a realistic and original alternative to existing cells for use under highly concentrated solar flux.To better understand the optimal multijunction III-Sb cell, the work carried out consisted on the manufacturing and characterization of the three sub-cells independently.These three epitaxial samples are Al0,9Ga0,1As0,07Sb0,93 (Top cell), the Al0,35Ga0,65As0,03Sb0,97 (Middle cell) and GaSb (Bottom cell) having as respective gaps 1.6 eV, 1.22 eV and 0.726 eV at 300 K.The work presented in this thesis is:- The establishment of all the technological steps required to manufacture the cells (metal deposition, wet and dry plasma etching ...).- The characterization of metallization by TLM structure (Transmission Line Method) with the best result being a three-layer metallization Cr/Pd/Au (30/30/30 nm) on a GaSb P-type substrate.- The characterization under dark of current-voltage electrical parameters of PV cells at room temperature and in function of the temperature.- The thermal characterization by measuring the thermal conductivity of the materials and a surface temperature mapping in function of the concentrated solar flux in realistic conditions.- The electro-optical characterization by spectral response, from which we calculated the external quantum efficiency which is the ratio between the amount of electrons created and the amount of incident photons.- The characterization under 1 sun illumination (1 000 W/m²) in a solar simulator and in realistic conditions of which we compared the electrical parameters.- The characterization of solar cells under (highly) concentrated solar flux in the PROMES laboratory.The best efficiencies for Bottom, Middle and Top PV cells respectively are 4.6 % for 40 X (close to the state of the art), 8.2 % for 96 X and 5.4 % for 185 X (world first for these quaternary materials).This work was cofounded by the Ministry of Education and Research (ED Research grant) and Labex SOLSTICE
Gónzalez, Fernández María. "Prácticas artísticas híbridas contemporáneas en el ámbito rural. Paraisurrural." Doctoral thesis, Universitat Politècnica de València, 2016. http://hdl.handle.net/10251/61461.
[ES] La tesis analiza diversas construcciones del Arte contemporáneo en los proyectos y exposiciones llevados a cabo desde principios del siglo XXI en el ámbito rural en España. A partir de estos parámetros culturales generales y de parámetros específicos la indeterminación de los proyectos artísticos en el medio rural requiere, en la actualidad, una revisión de las diversas muestras para el análisis de las actividades realizadas por los artistas, los colectivos y las instituciones en este mismo ámbito. El estudio se divide en tres capítulos: El primer capítulo ha detectado la proliferación de recuperar planteamientos pedagógicos autónomos y marcos de educación popular, repensando los modos de relación y generación de Arte en los nodos de creación en el medio rural. Más concretamente bajo los nuevos modelos de una política cultural crítica, dando cabida a lo afectivo, la aportación de otras políticas participativas del apoyo mutuo y la mediación en términos del procomún, la representación de las funciones culturales, ecológicas, estéticas, didácticas, productivas y los usos del software libre en los diversos proyectos artísticos. Estos laboratorios de creación se representan en las manifestaciones más maduras de proyectos y obras que integran el Arte en el medio rural en el sistema institucional e intentan el desarrollo de una normativa regularizada. El segundo capítulo examina de qué maneras actúan el conocimiento transdisciplinar y el Arte en los diversos emplazamientos de los centros llamados Fab labs, sedes de creación cuyo uso aboga las tecnologías de código abierto. Tras constatar esto se presenta el análisis de los casos prácticos en torno al Arte existentes en el medio rural en España, que han llevado a la formulación de unos criterios básicos a seguir para el compendio y creación de un directorio en el último capítulo. El tercer capítulo presenta mi propuesta personal como artista en búsqueda de nuevos modelos de producción, que como parte de un colectivo me ha permitido desarrollar un proyecto artístico transdisciplinar en el medio rural, llamado "Paraisurural". Este se implementa con los conocimientos adquiridos a lo largo de esta investigación en la creación de una plataforma online llamada Labrural o Laboratorio rural, que acoge las representaciones artísticas en el medio rural realizadas por los colectivos, las instituciones y las entidades creadas en España en la primera década del siglo XXI. Lugar en el que se etiquetan y catalogan en parámetros hasta ahora no considerados -como las lecturas de la etnografía, la valoración de la etnología y las aportaciones de las tecnologías de código abierto- para servir de una más rigurosa tipificación y propiciar una coherencia en la materialización de las obras artísticas.
[CAT] La tesi analitza diverses construccions de l'art contemporani en els projectes i exposicions duts a terme des de principis del segle XXI en l'`ambit rural a Espanya. A partir d'estos paràmetres culturals generals i de paràmetres específics la indeterminació dels projectes artístics en el medi rural requerix, en l'actualitat, una revisió de les diverses mostres per l'anàlisis de les activitats realitzades pels artistas, els col lectius i les institucions en este mateix àmbit. L'estudi es dividix en tres capítols: El primer capìtol ha detectat la proliferació de recuperar plantejaments pedagògics autònoms i marcs d'educació popular, repensant els modes de relació i generació d'Art en els nodes de creació en el medi rural. Més concretament davall els nous models d'una política cultural crítica, donant cabuda a l'afectiu, l'aportació d'altres polítiques participatives del suport mutu i la mediació en termes de l'utilitat pública, la representació de les funcions culturals, ecològiques, estètiques, didàctiques, productives i els usos del programari lliure en els diversos projectes artístics. Estos laboratoris de creació es representen en les manifestacions més madures de projectes i obres que integren l'art en el medi rural en el sistema institucional i intenten el desenrotllament d'una normativa regularitzada. El segon capítol examina de quines maneres actuen el coneixement transdisciplinar i l'Art en els diversos emplaçaments dels centres cridats Fab labs, seus de creació l'ús dels quals advoca les tecnologies de codi obert. Després de constatar açò es presenta l'anàlisis dels casos pràctics entorn de l'Art existents en el medi rural a Espanya, que han portat a la formulació d'uns criteris bàsics a seguir per al compendi i la creació d'un directori en l'últim capítol. El tercer capítol presenta la meua proposta personal com a artista a la recerca de nous models de producció, que com a part d'un col¿lectiu m'ha permés desenrotllar un projecte artístic transdisciplinar en el medi rural, cridat "Paraisurural". Este s'implementa amb els coneixements adquirits al llarg d'esta investigació en la creació d'una plataforma online crida Labrural o Laboratori Rural, que acull les respresentacions artístiques en el Medi Rural realitzades pels col¿lectius. les institucions i les entitats creades a Espanya en la primera década del segle XXI. Lloc en què s'etiqueten i cataloguen en paràmetres fins ara no considerats -com les lectures de l'etnografía, la valoració de l'etnologia i les aportacions de les tecnologies de codi obert- per a servir d'una més rigorosa tipificació i propiciar una coherencia en la materialització de les obres artístiques.
Gónzalez Fernández, M. (2016). Prácticas artísticas híbridas contemporáneas en el ámbito rural. Paraisurrural [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/61461
TESIS
Wu, Xiaoyue. "Simulation Study of Epitaxially Regrown Vertical-Cavity Surface-Emitting Lasers." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-52896.
Conde, Moustapha. "Composants optoélectroniques à microcavités verticales sur GaAs : Technologies avancées pour de nouvelles fonctions." Phd thesis, Université Paul Sabatier - Toulouse III, 2008. http://tel.archives-ouvertes.fr/tel-00357498.
Condé, Moustapha. "Composants optoélectroniques à microcavités verticales sur GaAs : technologies avancées pour de nouvelles fonctions." Toulouse 3, 2008. http://thesesups.ups-tlse.fr/411/.
To face up the increase in their application fields, laser emitters, including VCSELs, are moving rapidly towards greater integration capabilities, as well as diversified functionalities. Sophisticated structures and geometries for these devices are then mandatory, which implies overcoming first some technological limits. This thesis focuses, on the one hand, on the implementation of a methodology for optimizing molecular beam epitaxial growth from a rapid diagnostic method (uniformity, optical properties control) that can be applied to novel VCSEL structures with stacks of non-periodic layer. On the other hand, the wet GaAlAs oxidation technology is studied. This process, known as AlOx, opens the way for obtaining high-performance single-mode VCSELs through the resulting electro-optical lateral confinement. With the aim of an ultimate control and fine engineering for this confinement, the kinetics of oxidation is thoroughly investigated, an novel oven with a real-time in situ control of the oxidation front is presented, and a derived oxidation technique from the surface of a GaAlAs buried layer is demonstrated. This work contributes to the development of technologies for vertical and lateral structurations into vertical microcavity devices, opening up for VCSELs improved performances and new functionalities
Lindberg, Martin. "Mode Matching Analysis of One-Dimensional Periodic Structures." Thesis, KTH, Elektroteknisk teori och konstruktion, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-231842.
I detta examensarbete, analyseras elektromagnetisk v°agutbredning i periodiskav°agledarstrukturer som uppvisar glid symmetri. Analysen genomf¨ordes genom enmod matchnings-teknik som korrelerar de olika mod-koefficienterna fr°an separeraderegioner i strukturen med varandra. Denna teknik anv¨ands f¨or att ta framdispersionsrelationen f¨or tv°a endimensionella periodiska strukturer: en glid symmetriskkorrugerad meta-yta och en koaxial ledare belagd med periodiskt urgr¨opdah°aligheter. Mod matchnings-formuleringen presenteras i Kartesiska och cylindriskakoordinatsystem respektive f¨or de ovan n¨amnda fallen. Mod matchnings-resultatenj¨amf¨ors med data-simulerade resultat erh°allna fr°an CST Microwave Studio och de¨overenst¨ammer v¨al med varandra.
Teng, Sin Yong. "Intelligent Energy-Savings and Process Improvement Strategies in Energy-Intensive Industries." Doctoral thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2020. http://www.nusl.cz/ntk/nusl-433427.
Chu, Rei-Lin, and 朱瑞霖. "Antimonide-based compound semiconductors for III-V CMOS technology." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/63929518091134061196.
國立清華大學
材料科學工程學系
102
Antimonide-based compound semiconductors are emerging materials for the high-speed low-power electronics in complementary metal-oxide-semiconductor (CMOS) industry beyond 7-5 nm node technology, mid-infrared sensors/detectors in military/medical industry, and solar cells in green energy industry, due to their wide range of tunable band gaps and high carrier mobilities among the III-V compound semiconductors. However, despite the increasing demand in antimonide-based material system for realizing the high performance transistors operated at ultra-low driving voltage (< 0.5 V), the attainment of a high-/(In)GaSb interfaces possessing the low interfacial density of states (Dit) as well as the acceptable thermal stability has yet been achieved. In this dissertation, by depositing the rare-earth oxide, Y2O3, via molecule beam epitaxy (MBE) and atomic layer deposition (ALD), respectively, we have succeeded in passivating the GaSb(100) surface, which forms a thermally stable (> 500 oC) and well-bonded high-/GaSb interface. A detailed comparison between the samples with Y2O3 deposited by MBE and ALD, respectively, has been carried out with respect to the interface chemical bondings and electrical properties. Moreover, dependence of the deposition temperatures of MBE-Y2O3 to the interfacial properties and related MOS device performance has also been discussed. The corresponding chemical bondings and subsequent reactions for the Y2O3/GaSb interface were studied using in situ angle-dependent X-ray photoelectron spectroscopy (XPS). Moreover, the electrical properties for the Y2O3/GaSb interface were studied in terms of the conventional capacitance-voltage (C-V) and leakage current density-electric field (Jg-Eg) characteristics along with the temperature-dependent conductance method (CM) measurements and Gray-Brown (G-B) method analysis for the interfacial density of states (Dit) extraction. Consequently, the self-aligned inversion channel GaSb p-MOSFETs have been fabricated and yielded a record high saturation drain current density (Id,sat) of 130 A/m and maximum transconductance (Gm,max) of 90 S/m. Besides, a low subthreshold slope (S.S.) of 147 mV/decade and a peak field-effect hole mobility (h,FE) of 200 cm2/V-s were also obtained from the GaSb p-MOSFETs with 1 μm-gate-length.
Fonstad, Clifton G. Jr, Eralp Atmaca, Wojciech Giziewicz, James Perkins, and Joseph Rumpler. "Progress in Developing and Extending RM³ Heterogeneous Integration Technologies." 2003. http://hdl.handle.net/1721.1/3729.
Singapore-MIT Alliance (SMA)
KUO, HENG, and 郭衡. "Development of III-V Epitaxial Lift-off Processes by Supercritical Fluids Technology." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/30964994810584047707.
國立高雄大學
電機工程學系碩士班
104
Considering the key of high cost for producing high efficiency III-V compound solar cell is mainly due to its expensive substrate. Therefore, developing of reproducible and stable Epitaxial Lift-Off (ELO) technology has been regarded as the key way for cost down issue. Which ELO process is based on selectively attacking a thin sacrificial AlAs layer from GaAs under aqueous hydrofluoric acid (HF) solution (selectivity: >106, as compared to GaAs). Looking into the bottleneck of traditional ELO technology by wet etching method, people found its later etch rate (LER) is mainly dominant by diffusion-limited instead of reaction-rate-limited. In other words, the dominant reason for manipulating etching rate is dependent on the solubility of reaction residual and the exchanging rate of fresh etchant solution in the tunnel. Hence, as sample size is getting larger and the sacrifice layer is going to become narrower (i.e. higher gap-aspect-ratio), it has been expected the etching rate will be more slow down. In order to overcome those bottlenecks caused by traditional wet etching ELO processes, this study was focus on surveying the way for reducing surface tension. We were therefore inspired by supercritical fluids (SCFs) and know it naturally exhibits low viscosity, high diffusivities and zero surface tension – has extremely potential to bring breakthrough in developing ELO technology. Therefore, in the beginning of this study, we aim to establish a highly corrosion-resistance and HF-compatible SCFs etching system for moving into developing SCFs etching technology. Moreover, we launched this study by systematically investigating LER under various SCFs conditions (such as T, P and etchant concentration), accompanying with developing the related thin-film maintained technology. For studying LER by wet etching method, samples with a 500nm thick Au-coated layer (structure: 3µm GaAs thin film - 150nm AlAs sacrificial layer - 350µm GaAs substrate) were patterned to form shapes of square, circle and hexagonal as well as having various size in range of 200µm ~ 1000µm. We hence can evaluate their LER in different concentration of aqueous hydrofluoric acid (HFaq) by determining if the Au-coated GaAs thin film has been lift-off and floating in the etchant. We observed the LER of sample with hexagonal pattern in condition of [HF] = 49% can go to 30 ~ 65µm/min. On the other hand, once the sample area enlarges 400 times (1mm x 1mm → 20mm x 20mm), meanwhile, the ratio of the length of etching tunnel to the thickness of sacrificial layer (gap-aspect-ratio) have one order degree higher (104 → 105). With the same concentration of HF (49%), the LER for 20nm or 100nm AlAs sacrificial layer is 4.6 and 6.2 µm/min, respectively. It also indicates that the speed of ELO processes is mainly affected by diffusion-limit. In the beginning of moving into supercritical fluids etching, we choose anhydrous Hydrogen fluoride-pyridine (HF/Py) as the solute and mix it into the supercritical CO2 (scCO2) as the solvent. By trade off people’s safety and system operation limit, the experiment was conducted under available temperature (T) and pressure (P) in the range of 40oC ~ 60oC and 2000psi ~ 3000psi, respectively. The results show that the LER can be manipulated and enhanced by either of increasing etching temperature or pressure. We therefore set T = 60oC and P = 3000psi for keeping the LER stay in high speed for following studies. Considering mixing low content of pure water into scCO2 can help in taking the residues away from the etching tunnel, in this study, we also confirm that using low concentration aqueous HF(aq) mixed in scCO2 indeed can offer us a higher LER than etching in high concentration of HF/Py. On the other hand, co-solvent effect of mixing acetone (ACE) into HF/scCO2 was also investigated. In case of low [HF] (< 500mM), mixing ACE and HF with the same volume, we found the LER can be little enhanced. However, as increasing [HF] (500 ~ 700 mM), using co-solvent will make the LER have an obvious reducing. Furthermore, in case of [HF] = 713mM, as the volume proportional of ACE to HF is going higher, the LER will be further decreased. In addition, for understanding those etching performance under even higher [HF], by comparing of samples with 150nm AlAs sacrificial layer separately etching in condition of [HF(aq)] = 713mM and [HF(aq)] = 938mM under scCO2, the results shown, in case of [HF(aq)] = 938mM, the LER can be pushed to 111m/min, but damage on the wafer surface was easily accompanying by. Therefore, in this study, we were keeping [HF(aq)] = 713mM (~ 1.24% in wt) to immerse larger samples (size: 20mm x 20mm) in HF/scCO2 until which GaAs thin film can be totally lift-off for realizing their average LER when the needed etching time goes to 0.5 ~ 1 day. The results show that as narrowing the thickness of AlAs from 150nm to 20nm (150, 100, 20nm), the LER will be decreased from 12.8m/min to 7m/min (12.8, 9.3, 7 µm/min). Moreover, comparing to the traditional wet etching ELO method, this study using only 1/40 concentration of HF in scCO2 (i.e. 1.24% V.S. 49%), the LER can be even increased higher than 1.5 times. The niche of introducing SCFs technology into developing “dry” and high efficient ELO processes has been initial demonstrated. Following the ELO process, a 3m GaAs thin film in dimension of 400mm2 has been successfully well-transferred into a flexible PET substrate by using polydimethylsiloxane (PDMS) and NOA61. Overall, in this study, we have built-up a high corrosion-resistance SCFs etching system and introduced it into developing SCFs-related etching technology. We also investigated its etching performances under various pressure and temperature as well as studying its co-solvent effect by acetone. Hopefully, our work in pioneer can become the valuable foundation for developing SCFs etching technology and bring inspired in the field of photonics, Silicon industry, etc.
Hwang, Jung Min, and 黃忠民. "KEY TECHNOLOGY DEVELOPMENT FOR HIGH EFFICIENCY III-V BASED SOLID-STATE LIGHTING SOURCE." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/19750220019717228324.
國立清華大學
電子工程研究所
93
There had various methods to generate the white light of SSL. Each method could be evaluated by cost, performance, and technology requirement. The research and challenge for industry or scientist was still in progress. The thesis was focus on the discussion of performance and technology requirement. The major technology now for III-nitride based LED fabricated including III-Nitride growth, doping, contact, etching and package was presented. How to make the high efficiency device was the research key point in this thesis. The solution was listed below in my research. ² Solution for Improvement of internal quantum efficiency We invented a photon-assisted wet etching with chopped photon source method for device fabrication. This damage free etching method could produce an ultra-smooth etching surface with RMS=0.37nm in GaN. The smooth, uniform, and broaden etching surface in GaN by ELPEC-CS was achieved. The methods was extended to etching p-type GaN, the physical limitation in photoelectrochemical etching was overcame. The first blue LED fabricated by photon-assisted wet etching method was fabricated. The surface treatment methods were also developed. The surface state was removed by boiled KOH treatment with short time or photon assisted cryogenic etching. The etching damage was the key issue while the device was scale down. ² Solution for Improvement of light extraction efficiency The light extraction method in the III-Nitride LED and III-Phosphide LED were developed by our photon-assisted wet etching method. ² Solution for Improvement of electrical efficiency n The p-type GaN issue was considered in hydrogen extraction and ohmic contact. The series resistance included resistance of p-type GaN and contact resistance were reduced and discussed in detail. n The scale-down effect of the III-Nitride structure and device was discussed. While the device scaling down, the current crowding effect will be suppressed. Many application of my research were presented including Digital light source and quick testing method. In the thesis, various structure sizes were fabricated by various etching technology. The size of III-Nitride based structure was fabricated from 300mm to 10nm. The LED structure from 300mm to 4mm could be formed by photolithography following by etching. By controlling photolithography in diffraction mode or over etching the metal mask, the size could be reduced from 2mm to 0.5mm. The mesa GaN LED or P/N diode could be fabricated. The nano structure from 100 to 30nm of GaN could be formed due to the dislocation-induced morphology during etching in photo-assisted wet etching. The structure with 50~10nm nano-wire could be fabricated in GaN or p-GaN during photo-assisted wet etching. The micro-LED was successfully fabricated. How to make the nano-LED with scale-down (100~0.1nm for nano scale) for III-Nitride was the major research in the future. The optimized device structure was designed by the commercial software with lattice mismatch control concept. The heat extraction in III-Nitride based flip chip LED and III-Phosphide vertical LED was designed. The scale-down effect of the thermal extracted was designed and discussion. There still had much challenges for fabricating or modeling while device was scale-down from micro to nano scale (100nm-0.1nm). The research and develop of micro-LED, nano-LED or quantum dot LED for “Next generation light source” was an interested, valuable and challenge work.
Hsiao, Ya, and 蕭亞. "Low resistance metal T-gate and source/drain contact technologies for III-V MOSFET Application." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/85767090660071059345.
國立交通大學
光電系統研究所
102
III-V materials, comparing with Si, can provide significantly higher electron mobility and higher drift velocity under low voltage operation. Consequently, III-V materials are very promising to replace currently used Si as channel material in order to achieve a better power consumption/device performance tradeoff. In this thesis, gate and source/drain technologies for III-V metal oxide semiconductor field effect transistor (MOSFET) application have been developed. The related key structure fabrication as well as material and electrical analysis were also carried out in this study. Firstly, the control gate is basically a metal T-shaped gate structure consisting of (1) a wide top cover to provide a low-resistance path for RF signal passing through; (2) a narrow stem at the bottom as gate footprint to reduce the contact area with the substrate, to form smaller gate length, to reduce electron transit delay, and hence to increase operation frequencies. In order to achieve a smaller gate length, we use silicon nitride (SiNx) film as a structural support layer, coupled with "double nitride deposition and dry etching process" to shrink the gate length. The minimum finally gate length achieved in this study is 60 nm. Source/drain contact technology is developed based on conventional silicide technology which can be easily applied on III-V epitaxial layers, such as indium gallium arsenide and gallium arsenide, for self-aligned metal alloy formation. The self-aligned S/D structure without additional lithography steps can achieve better device density scaling and reduce the series resistance simultaneously. A variety of metal stacks were deposited on indium gallium arsenide or gallium arsenide substrates to form alloys under different annealing temperatures. Experimental results show that the lowest contact resistance achieved is 768 Ω∙um when using germanium/nickel metal contact stack. The developed gate and source/drain contact technologies are potential for future high-performance III-V MOSFET development.
Hau-YuLin and 林浩宇. "The Study of Substrate-Strained Silicon Technology and III-V Compound Semiconductor for Realizing High Performance Transistors." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/29240663120737958427.
Chang, Pen, and 張翔筆. "Interface engineering between high-κ dielectrics and III-V high mobility channel materials for passivation enabling the technology beyond Si CMOS." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/26050156900427811103.
國立清華大學
材料科學工程學系
100
The High-κ/Metal-Gate plus III-V high mobility channel materials is regarded as a urgent issue for achieving high performance and low power dissipation complementary metal-oxide-semiconductor (CMOS) technology beyond 15 nm node. A combination of electrical, chemical, and structural characterization methods to evaluate the MOS interface passivation quality. The interface engineering of in-situ directly deposited not only rare-earth oxide (REOs) but also HfO2-based high-κ dielectrics on III-V surface exhibited the successful passivation, in terms of low interfacial density of states (Dit) below 10e12 eV-1cm-2 without midgap peak, low equivalent oxide thickness (EOT) below 1 nm, low leakage current, both conduction band offset (ΔEc) and valence band offset (ΔEv) are larger than 1.5 eV, and truly high thermal stability higher than 800 oC. Moreover, high performance of self-aligned gate first inversion-channel MOS field-effect-transistors (MOSFETs) have achieved steep subthreshold swing (SS) value below 100 mV/dec, a maximum drain current (Id,max) of 1.5 mA/μm, a maximum transconductance (Gm) of 0.77 mS/μm, and a peak field-effect mobility (μFE) of 2100 cm2/Vs. This work suffices the key for realizing ultimately scaled devices with really high performance.
Wu, Yan-Dar, and 吳彥達. "The study of high k dielectrics and metal gates on Si and III-V semiconductor substrates for the advanced CMOS technology." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/87326659377380981542.
國立清華大學
材料科學工程學系
101
Looking beyond the 15 nm node ICs, the consensus is that not only high-κ dielectrics but also appropriate channel material should replace the long-standing SiO2/Si system. The combination of high-κ dielectrics with channel of the III-Vs will have to be integrated onto Si. The themes of this work were divided into three parts: 1. Silicon wafer and MBE-grown HfO2 thin template were used as substrates for sputtering deposition. From TEM pictures, the interfacial layer thickness of HfO2 deposited on Si and MBE-grown thin HfO2 template is 19.3 Å and 9 Å. At -1V, the leakage density is 3.8x10-3A/cm2 and 8.1x10-7A/cm2 for HfO2/Si and HfO2/(MBE-grown thin HfO2 template) samples. For HfO2/(MBE-grown thin HfO2 template) sample, a maximum value of capacitance at 1 kHz is 151pF, yielding a dielectric constant of 12.8 with the capacitance equivalent thickness (CET) of 17.8Å. The capacitance-voltage curves of HfO2/(MBE-grown thin HfO2 template) sample show a minor frequency dispersion of capacitance. The interfacial improvement and the enhanced electrical properties of the HfO2 film were obtained with MBE-grown thin HfO2 template. 2. HfO2 was combined with TiO2 to increase the dielectric constant. From TEM, the oxide thickness of Ti-doped HfO2 on Si and MBE-grown HfO2 template is 76 Å and 87 Å. The thickness of interfacial layer for Ti-doped HfO2 on Si and MBE-grown HfO2 template is 12Å and 8Å. At Vfb+1V, the leakage current density of Ti-doped HfO2 on Si and MBE-grown HfO2 template was 0.31 and 2x10-2 A/cm2. According to the CV curves, the calculated flat-band voltage of the Ti-doped HfO2 on Si and MBE-grown template was 0.15 and 0.28 volt. From the CV curves modified with two-frequency model, the calculated dielectric constant of Ti-doped HfO2 on Si and MBE-grown template is 13.4 and 21.4 with capacitance equivalent thickness of 22Å and 16 Å. 3. For the Al2O3/Ga2O3(Gd2O3)/In0.2Ga0.8As system, an atomically sharp oxide/semiconductor interface and amorphous GGO without any re-crystallization indicates the robustness and thermal stability of the hetero-structures. Both p- and n-MOS capacitors show very small frequency dispersion ranging from 2.2% to 4.4% (10 kHz–500 kHz) in the accumulation region, indicating the high-quality gate dielectric stack and GGO/In0.2Ga0.8As interface. For MOS capacitors with the same type of substrate and different metal gates, the differences between the Vfb’s are in good agreement with the differences in metal work functions, indicating unpinned Fermi-levels at the metal/dielectric interfaces. These are due to the perfected interfaces on both oxide/semiconductor and metal/oxide, revealing Fermi- level unpinning at both interfaces. Moreover, we have further derived the Vth’s of the p- and n-MOS capacitors with different metal gates. The present derived Vth values may not be very accurate, however, are in a good agreement with those observed on quasi-static C-V curves. In summary, the results in this dissertation demonstrate MBE-grown thin template is a good buffer layer to decrease the plasma bombardment during the sputtering process, mixing TiO2 into HfO2 is effectively to increase the dielectric constant value, and Vth’s of the p- and n-MOS capacitors with different metal gates was derived.
"Synthesis of Hybrid (III-V)y(IV)5-2y Semiconductors: A New Approach to Extending the Optoelectronic Capabilities of Si and Ge Technologies." Doctoral diss., 2017. http://hdl.handle.net/2286/R.I.44221.
Dissertation/Thesis
Doctoral Dissertation Chemistry 2017
Ok, Injo 1974. "A study on electrical and material characteristics of hafnium oxide with silicon interface passivation on III-V substrate for future scaled CMOS technology." Thesis, 2008. http://hdl.handle.net/2152/3974.
text
Chen, Yi-Ren, and 陳奕任. "Growth of Silver-nanoparticle-distributed Zinc Oxide Thin Films to Improve The Efficiency of III-V(InGaP/GaAs/Ge) Solar Cells Using Spin-coating Technology." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/92g2gz.
國立虎尾科技大學
光電與材料科技研究所
102
ilver-nanoparticle-distributed Zinc Oxide (Ag/ZnO) thin films was prepared by spin-coating technology in this thesis. The solution composed of zinc acetate, sodium hydroxide and silver nitrate is used as the coating, which spins on the silicon and glass substrate uniformly. The Ag/ZnO films will form on the substrate after baking in furnace system. The effects of zinc acetate concentration, sodium hydroxide concentration, silver nitrate concentration were investigated in this thesis.The optimal concentration of zinc acetate and sodium hydroxide and silver nitrate concentration are 0.007M and 1 M and 0.008M, respectively. The best baking temperature is about 200 oC under vacuum condition. The Transmittance and Reflectivity of Ag/ZnO film are 95 % and 2.5% , respectively under the optimal condition. The peak position of PL spectrum at optimal condition are 379 nm and 550 nm, respectively. We will coat the bestest Ag/ZnO film on the surface of III-V(InGaP/GaAs/Ge) solar cells,it can increases the efficiency of III-V solar cells from 30.4% to 34.1%.
Fastlund, Martina. "Arseniks löslighet i grundvattenakviferen i Hjältevad : Utvärdering med geokemisk modellering." Thesis, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-343032.