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Journal articles on the topic 'TCAD TOOL'

Author: Grafiati
Published: 11 September 2023

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1

Lee, YongJae. "Simulations of Proposed Shallow Trench Isolation using TCAD Tool." Journal of the Korea Society for Simulation 22, no. 4 (December 31, 2013): 93–98. http://dx.doi.org/10.9709/jkss.2013.22.4.093.

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2

Landowski, Matthew M., and Z. John Shen. "TCAD Based Power Semiconductor Device e-Learning Tool." Journal of Power Electronics 10, no. 6 (November 20, 2010): 643–46. http://dx.doi.org/10.6113/jpe.2010.10.6.643.

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3

Sakai, Atsushi, Katsumi Eikyu, Kenichi Hisada, Yasuhiro Yamashita, Koichi Arai, Hiroyuki Arie, Yutaka Akiyama, and Tomohiro Yamashita. "Inverse Modeling of 4H-SiC Trench Gate MOSFETs Validated with Electrical and Physical Characterization." Materials Science Forum 963 (July 2019): 609–12. http://dx.doi.org/10.4028/www.scientific.net/msf.963.609.

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The effective modeling methodology of 4H-SiC trench gate MOSFETs is presented. The potential barrier lowering at the MOS channel region suggested by I-V measurements is implemented to commercial TCAD tool as the net-doping reduction. The proposed model is validated by comparison of TCAD simulations with I-V measurements and SEM image observations.
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4

Ruey-Sing Wei and A. Sangiovanni-Vincentelli. "PLATYPUS: A PLA Test Pattern Generation Tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 4 (October 1986): 633–44. http://dx.doi.org/10.1109/tcad.1986.1270233.

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5

Hongmei Li, C. E. Zemke, G. Manetas, V. I. Okhmatovski, E. Rosenbaum, and A. C. Cangellaris. "An automated and efficient substrate noise analysis tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 3 (March 2006): 454–68. http://dx.doi.org/10.1109/tcad.2005.854628.

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6

Riente, Fabrizio, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, and Mariagrazia Graziano. "ToPoliNano: A CAD Tool for Nano Magnetic Logic." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 7 (July 2017): 1061–74. http://dx.doi.org/10.1109/tcad.2017.2650983.

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7

Oikonomakos, P., and M. Zwolinski. "An Integrated High-Level On-Line Test Synthesis Tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 11 (November 2006): 2479–91. http://dx.doi.org/10.1109/tcad.2006.882120.

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8

Tulunay, GÜlin, and Sina Balkir. "A Synthesis Tool for CMOS RF Low-Noise Amplifiers." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 5 (May 2008): 977–82. http://dx.doi.org/10.1109/tcad.2008.917579.

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9

Abderehman, Mohammed, Rupak Gupta, Rakesh Reddy Theegala, and Chandan Karfa. "BLAST: Belling the Black-Hat High-Level Synthesis Tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41, no. 11 (November 2022): 3661–72. http://dx.doi.org/10.1109/tcad.2022.3200513.

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10

Kuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev, and Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 3 (November 18, 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.

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Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents methodological features of work with PMI and results of implementation of custom parameter models for silicon devices.
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11

Ibrahim, Walid, Valeriu Beiu, and Azam Beg. "GREDA: A Fast and More Accurate Gate Reliability EDA Tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 4 (April 2012): 509–21. http://dx.doi.org/10.1109/tcad.2011.2176123.

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12

Kagaris, Dimitri. "MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 1 (January 2016): 114–27. http://dx.doi.org/10.1109/tcad.2015.2448675.

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13

Pantho, Jubaer Hossain, and Christophe Bobda. "MeXT-SE: A Design Tool to Transparently Generate Secure MPSoC." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 11 (November 2020): 3799–808. http://dx.doi.org/10.1109/tcad.2020.3012651.

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14

Tao, Nick G. M., Bo-Rong Lin, Chien-Ping Lee, Tim Henderson, and Barry J. F. Lin. "Study on mechanisms of InGaP/GaAs HBT safe operating area using TCAD simulation." International Journal of Microwave and Wireless Technologies 7, no. 3-4 (April 10, 2015): 279–85. http://dx.doi.org/10.1017/s1759078715000495.

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The safe operating area (SOA) of InGaP/GaAs heterojunction bipolar transistors has been studied using two-dimensional Technology Computer-Aided Design (TCAD) tool. Comprehensive physical models, including hydrodynamic transport-based impact ionization and self-heating models were implemented. The simulations for two DC modes (constant Iband Vbmodes) captured all the SOA features observed in measurements and some failure mechanisms were revealed for the first time by TCAD simulations. The simulated results are also in agreement with analytical modeling. The simulation not only gives us insight to the detailed failure mechanisms, but also provides guidance for the design of devices with better ruggedness and improved SOA performances.
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15

Shih, Hsiu-Chuan, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, and Cheng-Wen Wu. "DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 9 (September 2014): 1356–69. http://dx.doi.org/10.1109/tcad.2014.2323203.

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16

SZCZESNY, ROMUALD, and MIECZYSLAW RONKOWSKI. "MODELING AND SIMULATION OF CONVERTER SYSTEMS PART II: SIMULATION PACKAGE TCAD." Journal of Circuits, Systems and Computers 05, no. 04 (December 1995): 669–97. http://dx.doi.org/10.1142/s0218126695000400.

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The methods, models and techniques — presented in the companion paper — have been used as a basis for the evaluation of popular general-purpose electrical circuit simulation programs, in particular, their applicability in the analysis of power electronic circuits. As a result of this critical evaluation, the general requirements for the simulation program adequate for converter systems studies and design have been formulated. On this basis the algorithm of TCAD — a general-purpose converter system simulation program — has been elaborated. In presentation of the TCAD program three parties have been distinguished: the first one emphasizes the applications of modern simulation methods for converter systems, the second describes briefly the features of the main modules of the TCAD package, and the third presents some simulation examples of practical converter systems. Three simulation examples are presented: two resonant converters and an induction motor drive fed by a full-bridge voltage source PWM inverter at normal and fault operation conditions. A good agreement between simulation and experimental results has proved that this simulation package is a power tool for research, teaching and engineering practice.
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17

Louris, E., D. Stefanakis, G. Priniotakis, L. Van Langenhove, and D. Tassis. "Optimization of cylindrical textile organic field effect transistors using TCAD simulation tool." IOP Conference Series: Materials Science and Engineering 254 (October 2017): 162006. http://dx.doi.org/10.1088/1757-899x/254/16/162006.

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18

Mamidipaka, M., K. Khouri, N. Dutt, and M. Abadir. "IDAP: A Tool for High-Level Power Estimation of Custom Array Structures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 9 (September 2004): 1361–69. http://dx.doi.org/10.1109/tcad.2004.833609.

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19

Tseng, Tsun-Ming, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci, and Ulf Schlichtmann. "Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 8 (August 2018): 1588–601. http://dx.doi.org/10.1109/tcad.2017.2760628.

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20

Mohanachandran Nair, Sarath, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, and Mehdi B. Tahoori. "VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 7 (July 2018): 1396–407. http://dx.doi.org/10.1109/tcad.2017.2760861.

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21

Rouying Zhan, Haigang Feng, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen, and A. Z. H. Wang. "Esdextractor: a new technology-independent cad tool for arbitrary esd protection device extraction." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 10 (October 2003): 1362–70. http://dx.doi.org/10.1109/tcad.2003.818140.

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22

Michez, A., S. Dhombres, and J. Boch. "ECORCE: A TCAD Tool for Total Ionizing Dose and Single Event Effect Modeling." IEEE Transactions on Nuclear Science 62, no. 4 (August 2015): 1516–27. http://dx.doi.org/10.1109/tns.2015.2449281.

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23

Biagetti, G., S. Orcioni, C. Turchetti, P. Crippa, and M. Alessandrini. "SiSMA—A Tool for Efficient Analysis of Analog CMOS Integrated Circuits Affected by Device Mismatch." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 2 (February 2004): 192–207. http://dx.doi.org/10.1109/tcad.2003.822131.

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24

Hazra, Aritra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin M. Harer, Ansuman Banerjee, and Subhankar Mukherjee. "POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 11 (November 2013): 1801–13. http://dx.doi.org/10.1109/tcad.2013.2267454.

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25

Akopyan, Filipp, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, Nabil Imam, et al. "TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 10 (October 2015): 1537–57. http://dx.doi.org/10.1109/tcad.2015.2474396.

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26

Viale, Benjamin, and Bruno Allard. "Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (October 2020): 3107–17. http://dx.doi.org/10.1109/tcad.2019.2962119.

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27

Viale, Benjamin, and Bruno Allard. "Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits - Part I." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (October 2020): 3067–80. http://dx.doi.org/10.1109/tcad.2019.2962120.

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28

Seiculescu, Ciprian, Srinivasan Murali, Luca Benini, and Giovanni De Micheli. "SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 12 (December 2010): 1987–2000. http://dx.doi.org/10.1109/tcad.2010.2061610.

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29

Usha, C., and Palanichamy Vimala. "Analytical Drain Current Model for Fully Depleted Surrounding Gate TFET." Journal of Nano Research 55 (November 2018): 75–81. http://dx.doi.org/10.4028/www.scientific.net/jnanor.55.75.

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In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.
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30

Zhan, R., H. Feng, Q. Wu, H. Xie, X. Guan, G. Chen, and A. Z. H. Wang. "ESDInspector: A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 10 (October 2004): 1421–28. http://dx.doi.org/10.1109/tcad.2004.833613.

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31

Duan, B. h., C. Xiong, L. Zhong, C. Zeng, and J. h. Xiong. "Simulation of 14 MeV neutron-induced SEU in SRAM." Journal of Instrumentation 18, no. 02 (February 1, 2023): T02003. http://dx.doi.org/10.1088/1748-0221/18/02/t02003.

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Abstract This paper presents a full-physical methodology to simulate single event upset (SEU) induced by 14 MeV neutron in static random access memory (SRAM). Nuclear-reaction simulator TALYS is first utilized to acquire valuable information about the secondary particles generated by nuclear interactions between 14 MeV neutrons with both silicon and oxygen nuclei. Based on Geant4 code, a tool named Gproton is used exclusively for the neutron/proton-induced SEU calculation. Pioneering Gproton simulation is used to output SEU candidate events by traditional critical-charge method and computing process is accelerated through a forced collision definition. Afterwards, a commercial TCAD which has good compatibility with the input and output files of the customized Gproton code is employed to distinguish the real SEU events from the candidate SEU events randomly selected. By combining Gproton and TCAD, a calibrated cross section of 14 MeV neutron-induced SEU can be obtained. The proposed method is applied to a 180-nm commercial SRAM with six-transistor memory cell. Predicted SEU cross section is in good agreement with experimentally measured value. The results present in this paper suggest that, for SRAMs exposed in 14 MeV neutron, the combination of the material particle transporting simulation and device TCAD modeling is a candidate method to provide reasonable predictions of the cross section of SEU which improves the accuracy of the prediction effectively.
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32

Liu, Manwen, Wenzheng Cheng, Zheng Li, Zhenyang Zhao, and Zhihua Li. "3D Simulation, Electrical Characteristics and Customized Manufacturing Method for a Hemispherical Electrode Detector." Sensors 22, no. 18 (September 9, 2022): 6835. http://dx.doi.org/10.3390/s22186835.

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The theoretical basis of a hypothetical spherical electrode detector was investigated in our previous work. It was found that the proposed detector has very good electrical characteristics, such as greatly reduced full depletion voltage, small capacitance and ultra-fast collection time. However, due to the limitations of current technology, spherical electrode detectors cannot be made. Therefore, in order to use existing CMOS technology to realize the fabrication of the detector, a hemispherical electrode detector is proposed. In this work, 3D modeling and simulation including potential and electric field distribution and hole concentration distribution are carried out using the TCAD simulation tools. In addition, the electrical characteristics, such as I-V, C-V, induced current and charge collection efficiency (CCE) with different radiation fluences, are studied to predict the radiation hardness property of the device. Furthermore, a customized manufacturing method is proposed and simulated with the TCAD-SPROCESS simulation tool. The key is to reasonably set the aspect ratio of the deep trench in the multi-step repetitive process and optimize parameters such as the angle, energy, and dose of ion implantation to realize the connection of the heavily doped region of the near-hemispherical electrode. Finally, the electrical characteristics of the process simulation are compared with the device simulation results to verify its feasibility.
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33

Chen, Jing, Yufeng Guo, Jun Zhang, Jianhua Liu, Qing Yao, Jiafei Yao, Maolin Zhang, and Man Li. "Off-State Performance Characterization of an AlGaN/GaN Device via Artificial Neural Networks." Micromachines 13, no. 5 (May 5, 2022): 737. http://dx.doi.org/10.3390/mi13050737.

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Due to the complexity of the 2D coupling effects in AlGaN/GaN HEMTs, the characterization of a device’s off-state performance remains the main obstacle to exploring the device’s breakdown characteristics. To predict the off-state performance of AlGaN/GaN HEMTs with efficiency and veracity, an artificial neural network-based methodology is proposed in this paper. Given the structure parameters, the off-state current–voltage (I–V) curve can therefore be obtained along with the essential performance index, such as breakdown voltage (BV) and saturation leakage current, without any physics domain requirement. The trained neural network is verified by the good agreement between predictions and simulated data. The proposed tool can achieve a low average error of the off-state I–V curve prediction (Ave. Error < 5%) and consumes less than 0.001‰ of average computing time than in TCAD simulation. Meanwhile, the convergence issue of TCAD simulation is avoided using the proposed method.
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34

Dargar, Shashi Kant, J. K. Srivastava, Santosh Bharti, and Abha Nyati. "Performance Evaluation of GaN based Thin Film Transistor using TCAD Simulation." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (February 1, 2017): 144. http://dx.doi.org/10.11591/ijece.v7i1.pp144-151.

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<p>As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10<sup>7 </sup>~8.3×10<sup>8</sup>, and a sub-threshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.</p>
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35

Sirakoulis, G. Ch, I. Karafyllidis, and A. Thanailakis. "A TCAD tool for the simulation of the CVD process based on cellular automata." Le Journal de Physique IV 11, PR3 (August 2001): Pr3–205—Pr3–212. http://dx.doi.org/10.1051/jp4:2001326.

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36

KUMARI, RITI, MANISH GOSWAMI, and B. R. SINGH. "THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs." International Journal of Nanoscience 11, no. 02 (April 2012): 1250021. http://dx.doi.org/10.1142/s0219581x12500214.

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This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.
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37

Kim, Ki Yeong, Joo Seok Noh, Tae Young Yoon, and Jang Hyun Kim. "Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers." Micromachines 12, no. 11 (November 19, 2021): 1422. http://dx.doi.org/10.3390/mi12111422.

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In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.
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38

Sharma, Sanjeev Kumar, Jeetendra Singh, Balwinder Raj, and Mamta Khosla. "Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET." Journal of Nanoelectronics and Optoelectronics 13, no. 10 (October 1, 2018): 1473–77. http://dx.doi.org/10.1166/jno.2018.2374.

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In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the barrier thickness.
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39

Jiang, Yi Fan, B. Jayant Baliga, and Alex Q. Huang. "Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design." Materials Science Forum 924 (June 2018): 361–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.361.

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This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge termination designs was compared and analyzed.
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40

Othman, Nurul Aida Farhana, Sharidya Rahman, Sharifah Fatmadiana Wan Muhamad Hatta, Norhayati Soin, Brahim Benbakhti, and Steven Duffy. "Design optimization of the graded AlGaN/GaN HEMT device performance based on material and physical dimensions." Microelectronics International 36, no. 2 (April 1, 2019): 73–82. http://dx.doi.org/10.1108/mi-09-2018-0057.

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Purpose To design and optimize the traditional aluminum gallium nitride/gallium nitride high electron mobility transistor (HEMT) device in achieving improved performance and current handling capability using the Synopsys’ Sentaurus TCAD tool. Design/methodology/approach Varying material and physical considerations, specifically investigating the effects of graded barriers, spacer interlayer, material selection for the channel, as well as study of the effects in the physical dimensions of the HEMT, have been extensively carried out. Findings Critical figure-of-merits, specifically the DC characteristics, 2DEG concentrations and mobility of the heterostructure device, have been evaluated. Significant observations include enhancement of maximum current density by 63 per cent, whereas the electron concentration was found to propagate by 1,020 cm−3 in the channel. Practical implications This work aims to provide tactical optimization to traditional heterostructure field effect transistors, rendering its application as power amplifiers, Monolithic Microwave Integrated Circuit (MMICs) and Radar, which requires low noise performance and very high radio frequency design operations. Originality/value Analysis in covering the breadth and complexity of heterostructure devices has been carefully executed through extensive TCAD modeling, and the end structure obtained has been optimized to provide best performance.
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41

Jayachandran, Remya, Dhanaraj Jagalchandran, and Perinkolam Chidambaram Subramaniam. "Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load." Facta universitatis - series: Electronics and Energetics 35, no. 1 (2022): 13–28. http://dx.doi.org/10.2298/fuee2201013j.

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Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 ?m SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 ?. The gain tuning of up to 5 V/V is achieved with RL equal to 50 ?, output swing of 1 V. OTA buffer configuration implemented using multigate transistor with resistive load below 1 k? exhibits a bandwidth around 5 GHz and tunable gain up to 5 V/V.
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42

Vimala, Palanichamy, and N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer." Journal of Nano Research 56 (February 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.

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In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device structures.
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43

Masalsky, Nikolae V. "Simulation of the characteristics of low-voltage gates on combined cylindrical surrounding gate field-effect nanotransistors." Radioelectronics. Nanosystems. Information Technologies. 13, no. 4 (December 29, 2021): 449–56. http://dx.doi.org/10.17725/rensit.2021.13.449.

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The applicability of the architecture of a nanoscale surrounding gate field-effect transistor with a combined cylindrical working area for low-voltage applications is discussed. At the same time, the licensed TCAD Sentaurus instrument and technological modeling system is used as a tool. The transistor architecture under consideration involves combining the working zones of n-channel and p-channel transistors with one common gate. At the same time, the efficiency of suppressing short-channel effects is maintained and a high level of transistor current is provided in the strong inversion mode. Based on this architecture, a TCAD model of the NAND gate has been developed, the design of which contains two independent surrounding gates one combined working area. The use of the proposed gate architecture makes it possible to reduce the number of required transistor structures per gate by three times. This leads to a decrease in the switched capacity and power dissipation. From the simulation results, the gate geometric parameters with a working area length of 25 nm and a diameter of 8.5 nm, which can function at control voltages of 0.5 V in the frequency range up to 20 GHz with high gain, are determined. The switching time delay is 0.81 ps. The TCAD model of a half-adder is developed in the basis 2NAND. According to the simulation results, the efficiency of the prototype, which performs binary code addition operations with a delay of 4.2 ps at a supply voltage of 0.5 V and a frequency of 20 GHz, is shown. The obtained results create a theoretical basis for the synthesis of low-voltage complex functional blocks with high performance and minimal occupied area, which meets modern requirements for digital applications.
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44

Elpelt, Rudolf, Bernd Zippelius, Stefan Doering, and Uwe Winkler. "Employing Scanning Spreading Resistance Microscopy (SSRM) for Improving TCAD Simulation Accuracy of Silicon Carbide." Materials Science Forum 897 (May 2017): 295–98. http://dx.doi.org/10.4028/www.scientific.net/msf.897.295.

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Computer-Aided-Design for the prediction of the technology process and the physical device properties (TCAD) is a key tool for the development and improvement of new device concepts as well as for the analysis and understanding of device properties and device behavior under application conditions. Apart from physical device models and parameters the precise process simulation of implanted doping profiles is mandatory for a sufficient prediction quality of the subsequent device simulations. In order to verify and improve the accuracy of process simulation, we employ the – for silicon carbide – relatively new method of Scanning Spreading Resistance Microscopy (SSRM) for the characterization of doping profiles.
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45

Morozzi, A., M. Hoffmann, R. Mulargia, S. Slesazeck, and E. Robutti. "Negative capacitance devices: sensitivity analyses of the developed TCAD ferroelectric model for HZO." Journal of Instrumentation 17, no. 01 (January 1, 2022): C01048. http://dx.doi.org/10.1088/1748-0221/17/01/c01048.

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Abstract This work aims to investigate the suitability of innovative negative capacitance (NC) devices to be used in High Energy Physics experiments detection systems, featuring self-amplified, segmented, high granularity detectors. Within this framework, MFM (Metal-Ferroelectric-Metal) and MFIM (Metal-Ferroelectric-Insulator-Metal) structures have been investigated within the Technology-CAD environment. The strength of this approach is to exploit the behavior of a simple capacitor to accurately ad-hoc customize the TCAD library aiming at realistically modeling the polarization properties of devices fabricated with ferroelectric materials. The comparison between simulations and measurements in terms of polarization as a function of the applied electric field for both MFM and MFIM devices has been used for modeling and methodologies validation purposes. The analyses and results obtained for MFIM capacitors can be straightforwardly extended to the study of NC-FETs. This work would support the use of the TCAD modeling approach as a predictive tool to optimize the design and the operation of the new generation NC-FET devices for the future High Energy Physics experiments in the HL-LHC scenario. The NC working principle will be employed for particle detection applications in order to exceed the limits imposed by current CMOS technology in terms of power consumption, signal detectability and switching speed.
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46

Zhou, Kai, Songming Miao, Xuanze Zhou, Guangwei Xu, Lingfei Wang, and Shibing Long. "A core drain current model for β-Ga2O3 power MOSFETs based on surface potential." AIP Advances 13, no. 1 (January 1, 2023): 015202. http://dx.doi.org/10.1063/5.0134215.

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For the first time, a core drain current model based on surface potential without any implicit functions is developed for beta-phase gallium oxide ( β-Ga2O3) power metal-oxide-semiconductor field-effect transistors (MOSFETs). The surface potential solution is analytically deduced by solving the Poisson equation with appropriate simplification assumptions in accumulation, partial-depletion, and full-depletion modes. Then, the drain current expression is analytically derived from the Pao–Sah integral as a function of the mobile charge density obtained from the surface potential at the source and drain terminals. In addition, nonlinear resistors in the source/drain access region are considered. It continuously predicts the characteristics of β-Ga2O3 power MOSFETs in all operation modes, including accumulation mode, partial-depletion mode, and full-depletion mode. Furthermore, the validity of the model is verified by comparing the results of the model with the numerical simulations carried out with the technology computer-aided design (TCAD) tool ATLAS Device Simulator from Silvaco. Good agreement between the proposed model and TCAD simulations is shown for β-Ga2O3 power MOSFETs with different intrinsic channel lengths, channel doping concentrations, and channel thicknesses. Ultimately, the Gummel symmetry test and the harmonic balance simulation test are performed to validate the model’s robustness and convergence.
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47

Italia, Markus, Ioannis Deretzis, Alfio Nastasi, Silvia Scalese, Antonino La Magna, Massimo Pirnaci, Daniele Pagano, Dario Tenaglia, and Patrizia Vasquez. "Multiscale Simulations of Plasma Etching in Silicon Carbide Structures." Materials Science Forum 1062 (May 31, 2022): 214–18. http://dx.doi.org/10.4028/p-n9v122.

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Manufacturing of Silicon Carbide (SiC) based devices will soon require the accuracy and control typical of the advanced Si based nanoelectronics. As a consequence, the processes development will surely benefit of technology computer aided design (TCAD) tools dedicated to the current and future SiC process technologies. Plasma etching is one of the most critical and difficult process for optimization procedures in the micro/nanofabrication area, since the resultant 2D (e.g. in trenches) or 3D (e.g in holes) profiling is the consequence of the complex interactions between plasma and materials in the device structures. In this contribution we present a simulation tool dedicated to the etching simulation of SiC structures based on the sequential combination of a plasma scale global model and feature scale Kinetic Monte Carlo simulations. As an example of the approach validation procedure the simulations are compared with the characterization analysis of particular real process results.
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48

Subash, T. D., T. Gnanasekaran, J. Jagannathan, and C. Divya. "Relative Analysis of GaAs, InSb, InP Using QWFET." Advanced Materials Research 984-985 (July 2014): 1080–84. http://dx.doi.org/10.4028/www.scientific.net/amr.984-985.1080.

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Indium Antimonide (InSb) has the greater electron mobility and saturation velocity of any semiconductor. Also InSb detectors are sensitive between 1–5 μm wavelengths and it belongs to III-V [13] component. In this paper we compare the InSb with some other major components like Indium Phosphide (InP) and Gallium Arsenide (GaAs) which are also from same III-V group. The analysis was made using the simulation tool TCAD and using the properties and band structure of those materials we compare InSb with InP and GaAs. The results we proposed shows that InSb is best for ultra high speed and very low power applications.
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49

Yang, Shao-Ming, Gene Sheu, Tzu Chieh Lee, Ting Yao Chien, Chieh Chih Wu, and Yun Jung Lin. "Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology." MATEC Web of Conferences 201 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201820102004.

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High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.
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50

Tang, Zhao Huan, Bin Wang, Jia Nan Wang, and Kai Zhou Tan. "Use N+ Buried Layer to Design a Low On-Resistance VDMOS." Advanced Materials Research 756-759 (September 2013): 4267–70. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4267.

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A novel structure of a VDMOS in reducing on-resistance is proposed and experimentally demonstrated with a 200V N-channel VDMOS. With this structure, the on-resistance value of the VDMOS is reduced by 19.6% than that of a traditional VDMOS structure as the breakdown voltage almost maintained the same value, and there is only one additional mask in processing this new structure VDMOS, which is easily fabricated. By TCAD tool, the specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in high-voltage VDMOS and BCD areas.
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