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Journal articles on the topic 'TCAD Design'

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Author: Grafiati

Published: 6 September 2023

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1

Bellini, Marco, and Lars Knoll. "Advanced TCAD Design Techniques for the Performance Improvement of SiC MOSFETs." Materials Science Forum 1004 (July 2020): 865–71. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.865.

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This paper introduces novel TCAD post-processing techniques for SiC MOSFETs with the aim of understanding which parts of the device limit the on-state performance. Typically, analytical models of MOSFETs are used as a starting point for the TCAD design process or as a simple way to understand the influence of complex design choices, as discussed in the works of [1-3]. These lumped element models result in a relatively straightforward approach because they explicitly identify the contributions of the regions of the transistor, facilitating the understanding of basic design choices and performance trade-offs. However, the simplifications introduced in analytical models limit their applicability to advanced device structures such as aggressively scaled transistors or trench MOSFETs with cellular layout. This paper presents mathematical techniques based on post-processing of TCAD simulations that combine the accuracy of numerical Finite Element studies with the interpretability of lumped element analytical models.

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2

Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

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In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design and device operation in electrical circuits.

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3

Rehman, Atta Ur, Amna Siddiqui, Muhammad Nadeem, and Muhammad Usman. "Improved PERC Solar Cell Design by TCAD Simulation." Proceedings of the Pakistan Academy of Sciences: A. Physical and Computational Sciences 58, no. 4 (March 28, 2022): 61–67. http://dx.doi.org/10.53560/ppasa(58-4)637.

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In this work, we aim to identify the performance limiting factors and consequently improve the performance of PERC solar cells through extensive TCAD based device simulation and modelling. Initially, a simplified planar PERC solar cell structure is simulated in Silvaco (Athena/Atlas), where the device geometry is selected according to an experimentally fabricated cell with an efficiency of 17.86%. The J-V curves and solar cell parameters such as Jsc, FF, Voc and efficiency (η) of the simulated cell are then fitted to the experimental performance parameters by incorporating relevant models as suggested by the literature. These include: carriers’ generation-recombination, mobility, statistics and bandgap narrowing. A good agreement is obtained, where the average percentage difference between simulated and experimental performance parameters is 0.65%. The solar cell performance is then improved to 21.52% by optimising the anti-reflective coating stack composition and thickness, and adding surface texturing. This increase in efficiency is attributed to lower surface recombination and reduced reflection due to light trapping. In addition, a textured front surface enhances the path-length of light, causing it to undergo multiple internal reflections which further increases light trapping, thus increasing Jsc by 7.31 mA/cm2.

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4

Pan, Zijin, Cheng Li, Mengfu Di, Feilong Zhang, and Albert Wang. "3D TCAD Analysis Enabling ESD Layout Design Optimization." IEEE Journal of the Electron Devices Society 8 (2020): 1289–96. http://dx.doi.org/10.1109/jeds.2020.3027034.

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5

Woo, Sola, Juhee Jeon, and Sangsig Kim. "Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning." Micromachines 14, no. 3 (February 21, 2023): 504. http://dx.doi.org/10.3390/mi14030504.

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In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current–voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.

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6

Singh, Vivek. "Relevance of technology computer aided design (TCAD) to process-aware design." Journal of Micro/Nanolithography, MEMS, and MOEMS 1, no. 3 (October 1, 2002): 290. http://dx.doi.org/10.1117/1.1508411.

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7

Chen, Yu-Guang, Hui Geng, Kuan-Yu Lai, Yiyu Shi, and Shih-Chieh Chang. "Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 4 (April 2014): 507–18. http://dx.doi.org/10.1109/tcad.2013.2293881.

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8

Wang, Ke, Haodong Jiang, Yiming Liao, Yue Xu, Feng Yan, and Xiaoli Ji. "Degradation Prediction of GaN HEMTs under Hot-Electron Stress Based on ML-TCAD Approach." Electronics 11, no. 21 (November 2, 2022): 3582. http://dx.doi.org/10.3390/electronics11213582.

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In this paper, a novel approach that combines technology computer-aided design (TCAD) simulation and machine learning (ML) techniques is demonstrated to assist the analysis of the performance degradation of GaN HEMTs under hot-electron stress. TCAD is used to simulate the statistical effect of hot-electron-induced, electrically active defects on device performance, while the artificial neural network (ANN) algorithm is tested for reproducing the simulation results. The results show that the ML-TCAD approach can not only rapidly obtain the performance degradation of GaN HEMTs, but can accurately predict the progressive failure under the work conditions with a mean squared error (MSE) of 0.2, informing the possibility of quantitative failure data analysis and rapid defect extraction via the ML-TCAD approach.

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9

Ma, Qiang, and Evangeline F. Y. Young. "Multivoltage Floorplan Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 4 (April 2010): 607–17. http://dx.doi.org/10.1109/tcad.2010.2042895.

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10

Nandi, Prajit, Hirak Talukdar, Dhiraj Kumar, and Ashvin Kumar G. Katakwar. "A Novel Approach to Design SAR-ADC: Design Partitioning Method." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 3 (March 2016): 346–56. http://dx.doi.org/10.1109/tcad.2015.2474379.

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11

Potbhare, Siddharth, Akin Akturk, Neil Goldsman, James M. McGarrity, and Anant Agarwal. "Modeling and Design of High Temperature Silicon Carbide DMOSFET Based Medium Power DC-DC Converter." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000144–51. http://dx.doi.org/10.4071/hitec-spotbhare-tp22.

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Silicon Carbide (SiC) is a promising new material for high power high temperature electronics applications. SiC Schottky diodes are already finding wide acceptance in designing high efficiency power electronic systems. We present TCAD and Verilog-A based modeling of SiC DMOSFET, and the design and analysis of a medium power DC-DC converter designed using SiC power DMOSFETs and SiC Schottky diodes. The system is designed as a 300W boost converter with a 12V input and 24V/36V outputs. The SiC power converter is compared to another designed with commercially available Silicon power devices to evaluate power dissipation in the DMOSFETs, transient response of the system and its conversion efficiency. SiC DMOSFETs are characterized at high temperature by developing temperature dependent TCAD and Verilog-A models for the device. Detailed TCAD modeling allows probing inside the device for understanding the physical processes of transport, whereas Verilog-A modeling allows us to define the complex relationship of interface traps and surface physics that is typical to SiC DMOSFETs in a compact analytical format that is suitable for inclusion in commercially available circuit simulators.

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12

Kwon, Hyoungcheol, Hyunsuk Huh, Hwiwon Seo, Songhee Han, Imhee Won, Jiwoong Sue, Dongyean Oh, et al. "TCAD augmented generative adversarial network for hot-spot detection and mask-layout optimization in a large area HARC etching process." Physics of Plasmas 29, no. 7 (July 2022): 073504. http://dx.doi.org/10.1063/5.0093076.

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Cost-effective vertical etching of plug holes and word lines is crucial in enhancing 3D NAND device manufacturability. Even though multiscale technology computer-aided design (TCAD) methodology is suitable for effectively predicting etching processes and optimizing recipes, it is highly time-consuming. This article demonstrates that our deep learning platform called TCAD-augmented Generative Adversarial Network can reduce the computational load by 2 600 000 times. In addition, because well-calibrated TCAD data based on physical and chemical mutual reactions are used to train the platform, the etching profile can be predicted with the same accuracy as TCAD-only even when the actual experimental data are scarce. This platform opens up new applications, such as hot spot detection and mask layout optimization, in a chip-level area of 3D NAND fabrication.

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13

Hu, Shiyan, Xiaobo Sharon Hu, and Albert Y. Zomaya. "Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 5 (May 2016): 697–98. http://dx.doi.org/10.1109/tcad.2016.2548179.

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14

Veneris, A., and M. S. Abadir. "Design rewiring using ATPG." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, no. 12 (December 2002): 1469–79. http://dx.doi.org/10.1109/tcad.2002.804388.

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15

Kagalwalla, Abde Ali, Puneet Gupta, Christopher J. Progler, and Steve McDonald. "Design-Aware Mask Inspection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 5 (May 2012): 690–702. http://dx.doi.org/10.1109/tcad.2011.2181909.

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16

Kahng, A. B., Seokhyeong Kang, R. Kumar, and J. Sartori. "Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 3 (March 2012): 404–17. http://dx.doi.org/10.1109/tcad.2011.2172610.

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17

Ludwig, Tobias, Joakim Urdahl, Dominik Stoffel, and Wolfgang Kunz. "Properties First—Correct-By-Construction RTL Design in System-Level Design Flows." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (October 2020): 3093–106. http://dx.doi.org/10.1109/tcad.2019.2921319.

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18

Chen, H. M., I. M. Liu, and M. D. F. Wong. "I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 11 (November 2006): 2552–56. http://dx.doi.org/10.1109/tcad.2006.873900.

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19

Fanshu Jiao, Sergio Montano, Cristian Ferent, Alex Doboli, and Simona Doboli. "Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 7 (July 2015): 1045–58. http://dx.doi.org/10.1109/tcad.2015.2418287.

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20

Brisk, Philip, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatie, Swaroop Ghosh, and Xun Jiao. "TCAD EIC Message: February 2019." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 2 (February 2019): 197–98. http://dx.doi.org/10.1109/tcad.2018.2890315.

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21

Razdan, R., and A. Strojwas. "A Statistical Design Rule Developer." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 4 (October 1986): 508–20. http://dx.doi.org/10.1109/tcad.1986.1270222.

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22

Kane, R., and S. Sahni. "A Systolic Design-Rule Checker." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 1 (January 1987): 22–32. http://dx.doi.org/10.1109/tcad.1987.1270242.

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23

Gnudi, A., P. Ciampolini, R. Guerrieri, M. Rudan, and G. Baccarani. "Sensitivity Analysis for Device Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 5 (September 1987): 879–85. http://dx.doi.org/10.1109/tcad.1987.1270330.

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24

De Smedt, B., and G. G. E. Gielen. "Watson: design space boundary exploration and model generation for analog and RF IC design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 2 (February 2003): 213–24. http://dx.doi.org/10.1109/tcad.2002.806598.

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25

Dobre, Sorin Adrian, Andrew B. Kahng, and Jiajia Li. "Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 4 (April 2018): 855–68. http://dx.doi.org/10.1109/tcad.2017.2731679.

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26

Tao, Nick G. M., Bo-Rong Lin, Chien-Ping Lee, Tim Henderson, and Barry J. F. Lin. "Study on mechanisms of InGaP/GaAs HBT safe operating area using TCAD simulation." International Journal of Microwave and Wireless Technologies 7, no. 3-4 (April 10, 2015): 279–85. http://dx.doi.org/10.1017/s1759078715000495.

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The safe operating area (SOA) of InGaP/GaAs heterojunction bipolar transistors has been studied using two-dimensional Technology Computer-Aided Design (TCAD) tool. Comprehensive physical models, including hydrodynamic transport-based impact ionization and self-heating models were implemented. The simulations for two DC modes (constant Iband Vbmodes) captured all the SOA features observed in measurements and some failure mechanisms were revealed for the first time by TCAD simulations. The simulated results are also in agreement with analytical modeling. The simulation not only gives us insight to the detailed failure mechanisms, but also provides guidance for the design of devices with better ruggedness and improved SOA performances.

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27

Dash, T. P., S. Dey, S. Das, J. Jena, E. Mahapatra, and C. K. Maiti. "Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 447–56. http://dx.doi.org/10.2174/2210681209666190809101307.

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Background:: In nano and microelectronics, device performance enhancement is limited by downscaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. This paper explores the key design challenges of stress-engineered FinFETs based on the epitaxial SiGe S/D at 7 nm Technology node. Objective:: To study the mechanical stress evolution in a tri-gate FinFET at 7 nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the devices through device simulation. Methods: 3D sub-band Boltzmann transport analysis for tri-gate PMOS FinFETs was used, with 2D Schrödinger solution in the fin cross-section and 1D Boltzmann transport along the channel. Results:: Using stress maps, the mechanical stress impact on the transfer characteristics of the device through device simulation has been analyzed. Conclusion:: Suitability of predictive TCAD simulations to explore the potential of innovative strain-engineered FinFET structures for future generation CMOS technology is demonstrated.

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28

Pangrle, B. M., and D. D. Gajski. "Design Tools for Intelligent Silicon Compilation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 6 (November 1987): 1098–112. http://dx.doi.org/10.1109/tcad.1987.1270350.

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29

Yongseok Cheon and M. D. F. Wong. "Design hierarchy-guided multilevel circuit partitioning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 4 (April 2003): 420–27. http://dx.doi.org/10.1109/tcad.2003.809659.

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30

Qiang Xu and N. Nicolici. "Multifrequency TAM design for hierarchical SOCs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 1 (January 2006): 181–96. http://dx.doi.org/10.1109/tcad.2005.852440.

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31

Cheng, Lei, and Martin D. F. Wong. "Floorplan Design for Multimillion Gate FPGAs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 12 (December 2006): 2795–805. http://dx.doi.org/10.1109/tcad.2006.882481.

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32

Jaffari, J., and M. Anis. "Variability-Aware Bulk-MOS Device Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 2 (February 2008): 205–16. http://dx.doi.org/10.1109/tcad.2007.907234.

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33

Chen, Yibin, Sean Safarpour, Joao Marques-Silva, and Andreas Veneris. "Automated Design Debugging With Maximum Satisfiability." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 11 (November 2010): 1804–17. http://dx.doi.org/10.1109/tcad.2010.2061270.

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34

Pan, David Z., Bei Yu, and Jhih-Rong Gao. "Design for Manufacturing With Emerging Nanolithography." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 10 (October 2013): 1453–72. http://dx.doi.org/10.1109/tcad.2013.2276751.

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35

Spoto, J. P., W. T. Coston, and C. Paul Hernandez. "Statistical Integrated Circuit Design and Characterization." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 1 (January 1986): 90–103. http://dx.doi.org/10.1109/tcad.1986.1270180.

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36

Kung-Chao Chu, J. P. Fishburn, P. Honeyman, and Y. E. Lien. "A Database-Driven VLSI Design System." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 1 (January 1986): 180–87. http://dx.doi.org/10.1109/tcad.1986.1270185.

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37

Chang, Wanli, Dip Goswami, Samarjit Chakraborty, Lei Ju, Chun Jason Xue, and Sidharta Andalam. "Memory-Aware Embedded Control Systems Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 4 (April 2017): 586–99. http://dx.doi.org/10.1109/tcad.2016.2613933.

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38

Phung, L. V., D. Planson, P. Brosselard, D. Tournier, and C. Brylinski. "3D TCAD Simulations for More Efficient SiC Power Devices Design." ECS Transactions 58, no. 4 (August 31, 2013): 331–39. http://dx.doi.org/10.1149/05804.0331ecst.

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39

Kuruvilla, Nisha. "National Workshop on Advanced Nanoscale Device Design Using TCAD [Chapters]." IEEE Solid-State Circuits Magazine 8, no. 4 (2016): 94–95. http://dx.doi.org/10.1109/mssc.2016.2601525.

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40

Lim, Wee Han, Amy L. Ziebell, Iwan Cornelius, Mark I. Reinhard, Dale A. Prokopovich, Andrew S. Dzurak, and Anatoly B. Rosenfeld. "Cylindrical Silicon-on-Insulator Microdosimeter: Design, Fabrication and TCAD Modeling." IEEE Transactions on Nuclear Science 56, no. 2 (April 2009): 424–28. http://dx.doi.org/10.1109/tns.2009.2013467.

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41

Boufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.

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A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.

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42

Ishikawa, M., T. Matsuda, T. Yoshimura, and S. Goto. "Compaction-Based Custom LSI Layout Design Method." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 3 (May 1987): 374–82. http://dx.doi.org/10.1109/tcad.1987.1270282.

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43

Modarres, H., and R. J. Lomax. "A Formal Approach to Design-Rule Checking." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 4 (July 1987): 561–73. http://dx.doi.org/10.1109/tcad.1987.1270303.

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44

Wisniewski, M. Y. L., E. Yashchin, R. L. Franch, D. P. Conrady, D. N. Maynard, G. Fiorenza, and I. C. Noyan. "The physical design of on-chip interconnections." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 3 (March 2003): 254–76. http://dx.doi.org/10.1109/tcad.2002.807881.

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45

Caldwell, A. E., H. J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu, and J. L. Wong. "Effective Iterative Techniques for Fingerprinting Design IP." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 2 (February 2004): 208–15. http://dx.doi.org/10.1109/tcad.2003.822126.

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46

Ryu, K. K., and V. J. MooneyIII. "Automated Bus Generation for Multiprocessor SoC Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 11 (November 2004): 1531–49. http://dx.doi.org/10.1109/tcad.2004.835119.

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47

Auge, I., F. Petrot, F. Donnet, and P. Gomez. "Platform-based design from parallel C specifications." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 12 (December 2005): 1811–26. http://dx.doi.org/10.1109/tcad.2005.852431.

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48

Agarwal, K., M. Agarwal, D. Sylvester, and D. Blaauw. "Statistical interconnect metrics for physical-design optimization." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 7 (July 2006): 1273–88. http://dx.doi.org/10.1109/tcad.2005.855954.

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49

Wang, G., S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh. "Statistical Analysis and Design of HARP FPGAs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 10 (October 2006): 2088–102. http://dx.doi.org/10.1109/tcad.2005.859485.

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50

Drinic, Milenko, Darko Kirovski, Seapahn Megerian, and Miodrag Potkonjak. "Latency-Guided On-Chip Bus-Network Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 12 (December 2006): 2663–73. http://dx.doi.org/10.1109/tcad.2006.882488.

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