Dissertations / Theses on the topic 'TCAD Design'

Le travail porte sur le développement et l’optimisation de transistors bipolaires à hétérojonction (TBH) SiGe et SiGeC par conception technologique assistée par ordinateur (TCAD). L'objectif est d'aboutir à un dispositif performant réalisable technologiquement, en tenant compte de tous les paramètres : étapes de fabrication technologiques, topologie du transistor, modèles physiques. Les études menées permettent d’atteindre les meilleures performances, en particulier une amélioration importante de la fréquence maximale d’oscillation (fMAX). Ce travail est la première approche développée pour la simulation des TBH SiGeC qui prend en compte l'impact de la contrainte et de la teneur en germanium et en carbone dans la base; conjointement pour les simulations des procédés de fabrication et les simulations électriques.Pour ce travail, nous avons développé et implémenté dans le simulateur TCAD des méthodes d'extraction de fMAX prenant en compte les éléments parasites intrinsèques et extrinsèques. Nous avons développé et implémenté un modèle pour la densité effective d’états fonction de la teneur en germanium et en carbone dans la base. Les modèles pour la bande interdite, la mobilité et le temps de relaxation de l'énergie sont calibrés sur la base de simulations Monte-Carlo.Les différentes analyses présentées dans cette thèse portent sur six variantes technologiques de TBH. Trois nouvelles architectures de TBH SiGeC avancés ont été élaborées et proposées pour des besoins basse et haute performance. Grace aux résultats obtenus, le meilleur compromis entre les différents paramètres technologiques et dimensionnels permettent de fabriquer un TBH SiGeC avec une valeur de fMAX de 500 GHz, réalisant ainsi l’objectif principal de la thèse
The present work investigates the technology development of state-of-the-art SiGe and SiGeC Heterojunction Bipolar Transistors (HBT) by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, a better understanding of charge transport, and to facilitate the development and optimization of SiGe and SiGeC HBT devices.The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.In this work we will work with the successive evolutions of B3T, B4T and B5T technologies. For each new device fMAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz, respectively.Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for fMAX and the carrier transport in extremely scaled HBTs.Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation.Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase fMAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of fMAX

L’augmentation de la densité d’intégration des circuits intégrés nous a amené à étudier, dans le cadre du développement de la technologie CMOS 45 nm, les sources de variabilité inhérentes aux procédés de fabrication utilisés pour ce nœud technologique, et à en déterminer les composantes principales,dans le but ultime de permettre la simulation précise de l’impact de la variabilité technologique à la fois au niveau transistor et circuit. Après un état de l’art des sources de variabilité du transistor MOS et des moyens de simulation associés,ce travail s'est orienté sur les fluctuations d'un facteur technologique difficilement accessible à la mesure statistique qu'est le dopage canal. Ensuite le nœud 45 nm a été étudié expérimentalement via un plan d'expériences.Ceci a permis de connaitre les variations naturelles des facteurs technologiques mais surtout les sensibilités des performances électriques vis-à-vis de ces facteurs.Nous avons pu ainsi identifier les causes prépondérantes de variabilité dues au procédé.Enfin, nous proposons d’améliorer la prise en compte des déviations des facteurs process dans les simulations Monte-Carlo et pire-cas appliquées aux modèles compacts au regard de ces observations expérimentales
Continuous improvement in integrated circuits density of integration lead us to study process-induced variations in the framework of the 45 nm node, and to determine their principal contributions with the ultimate goal being to allow an accurate simulation of both transistor and circuit level variability. This work starts with a study of the state of the art of variability sources of the MOS transistor and associated simulation means. Then it focuses on the fluctuations of the channel doping, which is a difficult factor to measure statistically.After that we study the 45 nm node through a design of experiment which let us learn about natural variations of process factors but mostly about electrical performances sensitivity to those factors.Thanks to that we could identify major causes of process-induced variability at this stage of this node development. At last, with respect to those experimental results, we propose to enhance the taking in account of process variations in Monte-Carlo and corner simulations applied to compact models

The present work investigates the technology development of state-of-the-art SiGe and SiGeC Heterojunction Bipolar Transistors (HBT) by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, a better understanding of charge transport, and to facilitate the development and optimization of SiGe and SiGeC HBT devices.The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.In this work we will work with the successive evolutions of B3T, B4T and B5T technologies. For each new device fMAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz, respectively.Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for fMAX and the carrier transport in extremely scaled HBTs.Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation.Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase fMAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of fMAX.

The goal of this thesis is to improve pilot understanding of the Traffic alert and Collision Avoidance System (TCAS) by changing the Traffic Situation Display (TSD). This is supported by two objectives. The first objective is to create an integrated, realistic air traffic environment. This serves as an experimental platform for testing and evaluating future TCAS TSDs. The simulator environment includes a desktop flight simulator, background air traffic simulator, and intruder aircraft. The intruder aircraft uses seven dimensional waypoints to robustly follow trajectories and cause specific resolution advisories. Second, the relative benefits of, and potential concerns with, new TCAS TSDs are explored using a structured, iterative design process with subject matter ex- perts (SMEs). Incremental changes to the TSD were implemented into the simulator environment. SMEs evaluated the displays and potential points of confusion were identified. Several display features are discussed and implemented for future evaluations. These include boundary lines of TCAS variables depicted on the TSD and on a vertical situation display, speed lines which vary with the TCAS estimate of time to closest point of approach, and a prediction of the safe altitude target during a resolution advisory. Scenarios which may be confusing or misleading are discussed. These scenarios may be ameliorated or exacerbated by display features. This information is useful to guide both design and certification or operational approval and is a starting place for future TCAS experiments.

Thesis (MScEng)--Stellenbosch University, 2003.
ENGLISH ABSTRACT: The aim of this thesis is to investigate a design of a microcontroller based embedded system that will be used to minimise cable harness on the SUNSAT micro-satellite. The system is called CAN node. The CAN node(s) implements CAN (Controller Area Network) serial bus architecture protocol. The protocol is implemented on the two nodes to transport data from the TCMD tot he 0 ther trays 0 f SUNSAT. CAN node( s) design proj ect focuses on the TCMD tray, because it is the central point for data communication in SUNSAT and it acts as the eyes and hands of the satellite's operator. As a result most of the communication cables are located at this tray. The two nodes are called TX-node and RX-nodes. The TX-node is used to collect data from the TCMD tray and transmits them serially to RX-node. The RX-nodes receives the TCMD data from TX-node and transmits these data to their respective nodes. In application RX-nodes need to be ten, but only one is used for testing purpose. The design had its shortcomings, of which they are discussed in this thesis. The recommendations of an ideal system are also given to elaborate how the system should behave in the real situation. Despite its shortcomings, the CAN node(s) project has successfully proven that cable harness on the TCMD tray of SUNSAT can be minimised by using CAN technology.
AFRIKAANSE OPSOMMING: Die doel van hierdie tesis is om die ontwerp van 'n mikro-beheerder gebaseerde stelsel wat die SUNSA T mikro-satelliet kabel harnas sal verklein, te ondersoek. Die stelsel word die CAN nodus genoem. Die CAN nodus implementeer die CAN (Controller Area Network) bus argitektuur protokol. Die protokol is op twee nodusse geïmplementeer om data vanaf die TCMD na ander laaie van SUNSAT te voer. Die CAN nodus ontwerp fokus op die TCMD laai, want dit is die sentrale punt vir data kommunikasie in SUNSA T en dit tree soos die oog en hande van die satelliet operateur op. As 'n gevolg, is die meeste van die kommunikasie kabels in hierdie laai. Die twee nodusse is genoem TXnodus en RX-nodus. TX-nodus word gebruik om die data van die TCMD af te kollekteer en dan versprei hulle tot hulle onderskeie nodusse. In die toepaslik moet daar tien RX-nodusse wees, maar net een is gebruik terwille van die toets. Die ontwerp het sy eie tekortkomings, wat in hierdie tesis bespreek word. Die rekommendasie van 'n ideale stelsel is ook gemaak om te bewys hoe die stelsel dit in 'n ware situasie moet gedra. Ongeag die tekortkomings daarvan, het die CAN-nodus projek suksesvol bewys dat die kabel harnas in die TCMD laai van SUNSAT kan verminder word deur die gebruik van die CAN tegnologie.

Les procédés bipolaires semi-conducteurs complémentaires à oxyde de métal (BiCMOS) peuvent être considérés comme étant la solution la plus généralepour les produits RF car ils combinent la fabrication sophistiquée du CMOSavec la vitesse et les capacités de conduction des transistors bipolaires silicium germanium(SiGe) à hétérojonction (HBT). Les HBTs, réciproquement, sontles principaux concurrents pour combler partiellement l'écart de térahertzqui décrit la plage dans laquelle les fréquences générées par les transistors etles lasers ne se chevauchent pas (environ 0.3 THz à 30 THz). A_n d'évaluerles capacités de ces dispositifs futurs, une méthodologie de prévision fiable estsouhaitable. L'utilisation d'un ensemble hétérogène d'outils et de méthodes desimulations permet d'atteindre successivement cet objectif et est avantageusepour la résolution des problèmes. Plusieurs domaines scientifiques sont combinés, tel que la technologie de conception assistée par ordinateur (TCAO),la modélisation compacte et l'extraction des paramètres.Afin de créer une base pour l'environnement de simulation et d'améliorerla confirmabilité pour les lecteurs, les modèles de matériaux utilisés pour lesapproches hydrodynamiques et de diffusion par conduction sont introduits dèsle début de la thèse. Les modèles physiques sont principalement fondés surdes données de la littérature basées sur simulations Monte Carlo (MC) ou dessimulations déterministes de l'équation de transport de Boltzmann (BTE).Néanmoins, le module de TCAO doit être aussi étalonné sur les données demesure pour une prévision fiable des performances des HBTs. L'approchecorrespondante d'étalonnage est basée sur les mesures d'une technologie depointe de HBT SiGe pour laquelle un ensemble de paramètres spécifiques àla technologie du modèle compact HICUM/L2 est extrait pour les versionsdu transistor à haute vitesse, moyenne et haute tension. En s'aidant de cesrésultats, les caractéristiques du transistor unidimensionnel qui sont généréesservent de référence pour le profil de dopage et l'étalonnage du modèle. Enélaborant des comparaisons entre les données de références basées sur les mesureset les simulations, la thèse fait progresser l'état actuel des prévisionsbasées sur la technologie CAO et démontre la faisabilité de l'approche.Enfin, une technologie future de 28nm performante est prédite en appliquantla méthodologie hétérogène. Sur la base des résultats de TCAO, leslimites de la technologie sont soulignées
Bipolar complementary metal-oxide-semiconductor (BiCMOS) processescan be considered as the most general solution for RF products, as theycombine the mature manufacturing tools of CMOS with the speed and drivecapabilities of silicon-germanium (SiGe) heterojunction bipolar transistors(HBTs). HBTs in turn are major contenders for partially filling the terahertzgap, which describes the range in which the frequencies generated bytransistors and lasers do not overlap (approximately 0.3THz to 30 THz). Toevaluate the capabilities of such future devices, a reliable prediction methodologyis desirable. Using a heterogeneous set of simulation tools and approachesallows to achieve this goal successively and is beneficial for troubleshooting.Various scientific fields are combined, such as technology computer-aided design(TCAD), compact modeling and parameter extraction.To create a foundation for the simulation environment and to ensure reproducibility,the used material models of the hydrodynamic and drift-diffusionapproaches are introduced in the beginning of this thesis. The physical modelsare mainly based on literature data of Monte Carlo (MC) or deterministicsimulations of the Boltzmann transport equation (BTE). However, the TCADdeck must be calibrated on measurement data too for a reliable performanceprediction of HBTs. The corresponding calibration approach is based onmeasurements of an advanced SiGe HBT technology for which a technology specific parameter set of the HICUM/L2 compact model is extracted for thehigh-speed, medium-voltage and high-voltage transistor versions. With thehelp of the results, one-dimensional transistor characteristics are generatedthat serve as reference for the doping profile and model calibration. By performingelaborate comparisons between measurement-based reference dataand simulations, the thesis advances the state-of-the-art of TCAD-based predictionsand proofs the feasibility of the approach.Finally, the performance of a future technology in 28nm is predicted byapplying the heterogeneous methodology. On the basis of the TCAD results,bottlenecks of the technology are identified
Bipolare komplementäre Metall-Oxid-Halbleiter (BiCMOS) Prozesse bietenhervorragende Rahmenbedingungen um Hochfrequenzanwendungen zurealisieren, da sie die fortschrittliche Fertigungstechnik von CMOS mit derGeschwindigkeit und Treiberleistung von Silizium-Germanium (SiGe) Heterostruktur-Bipolartransistoren (HBTs) verknüpfen. Zudem sind HBTs bedeutendeWettbewerber für die teilweise Überbrückung der Terahertz-Lücke, derFrequenzbereich zwischen Transistoren (< 0.3 THz) und Lasern (> 30 THz).Um die Leistungsfähigkeit solcher zukünftigen Bauelemente zu bewerten, isteine zuverlässige Methodologie zur Vorhersage notwendig. Die Verwendungeiner heterogenen Zusammenstellung von Simulationstools und Lösungsansätzenerlaubt es dieses Ziel schrittweise zu erreichen und erleichtert die Fehler-_ndung. Verschiedene wissenschaftliche Bereiche werden kombiniert, wie zumBeispiel der rechnergestützte Entwurf für Technologie (TCAD), die Kompaktmodellierungund Parameterextraktion.Die verwendeten Modelle des hydrodynamischen Simulationsansatzes werdenzu Beginn der Arbeit vorgestellt, um die Simulationseinstellung zu erläuternund somit die Nachvollziehbarkeit für den Leser zu verbessern. Die physikalischenModelle basieren hauptsächlich auf Literaturdaten von Monte Carlo(MC) oder deterministischen Simulationen der Boltzmann-Transportgleichung(BTE). Für eine zuverlässige Vorhersage der Eigenschaften von HBTs muss dieTCAD Kon_guration jedoch zusätzlich auf der Grundlage von Messdaten kalibriertwerden. Der zugehörige Ansatz zur Kalibrierung beruht auf Messungeneiner fortschrittlichen SiGe HBT Technologie, für welche ein technologiespezifischer HICUM/L2 Parametersatz für die high-speed, medium-voltage undhigh-voltage Transistoren extrahiert wird. Mit diesen Ergebnissen werden eindimensionaleTransistorcharakteristiken generiert, die als Referenzdaten fürdie Kalibrierung von Dotierungspro_len und physikalischer Modelle genutztwerden. Der ausführliche Vergleich dieser Referenz- und Messdaten mit Simulationengeht über den Stand der Technik TCAD-basierender Vorhersagenhinaus und weist die Machbarkeit des heterogenen Ansatzes nach.Schlieÿlich wird die Leistungsfähigkeit einer zukünftigen Technologie in28nm unter Anwendung der heterogenen Methodik vorhergesagt. Anhand derTCAD Ergebnisse wird auf Engpässe der Technologie hingewiesen

The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..

Les travaux présentés à travers ce manuscrit s'inscrivent dans un contexte de recherches exploratoires sur l'optimisation des surfaces engrenantes. Après une étude approfondie de l'emploi des engrenages dans un environnement aéronautique, l'élaboration d'une nouvelle méthodologie de génération de profils de denture est proposée. Les travaux s'attachent à caractériser le comportement mécanique spécifique d'un montage d'engrenages dans les Boites de Transmission de Puissances (BTP) d'hélicoptère.Un outil informatique a été créé dans le module VBA (Visual Basic Application) d'Excel. Il permet de créer automatiquement des profils de denture conjugués et optimisés. Il a l'avantage de définir analytiquement plusieurs grandeurs physiques. L'outil a ainsi pour objectif de proposer des profils de denture optimisés selon plusieurs critères. Les « objectifs » retenus sont le rendement et la contrainte équivalente de Hertz au contact suivant le critère de Von Mises.Les travaux s'articulent autour de trois axes : - la reconstruction de profils conjugués de denture par une approche novatrice basée sur le « contact », - la construction de critères physiques (glissement, pression, contrainte, …), - la recherche de profils de denture optimaux en utilisant la simulation de Monte Carlo.Enfin, la perspective de rendre générique cette méthode afin qu'elle puisse générer n'importe quels types d'engrenage est envisagée en fin de manuscrit
The work described in the present manuscript is part of exploratory researches dealing with gears meshing surfaces optimization. After a short study of gears used in an aeronautical environment, the development of an innovative tool for tooth profile design is defined. Then, the specific behavior of a gear mesh within a helicopter main gearbox (MGB) is evaluated.A VBA software has been coded under MS Excel to generate conjugated and optimized gear tooth profiles. It advantageously defines and uses several physical parameters with their analytical formulation. The software provides at the user optimized tooth profiles according to a couple of criteria. The two “objective” functions evaluated are the efficiency and the Hertz equivalent stress within the contact using the Von Mises criterion.The work has been focused on three aspects:- The design of conjugated tooth profiles by contact sharing,- The definition of the relevant physical parameters,- The optimization of tooth profiles using Monte Carlo SimulationEventually, a generic method to design gear profiles, taking into account any physical parameters related to a gear mesh, could be expected as a future of this thesis work

Un jeu pédagogique constitue une déclinaison relative à l'apprentissage du concept de jeu sérieux (serious game). Ce type d'outil permet la ludification (gamification) de l'activité afin d'utiliser des éléments de jeu dans un contexte non ludique et conduit à catalyser l'attention, faire accroître l'engagement et augmenter la motivation des joueurs-apprenants dans les situations d'apprentissage. Les jeux pédagogiques reposent sur la mise en situation et l'immersion des apprenants, utilisant les ressorts ludiques dans des simulations axées vers la résolution de problèmes. Parmi des recherches antérieures, certains retours d'expériences font écho d'une trop grande artificialité de l'activité notamment par manque de contextualisation de l'apprentissage dans l'environnement d'utilisation des connaissances apprises. Nous avons proposé la mise en place un environnement mixte (physique et numérique) et l'utilisation de techniques collaboratives pour raffiner l'approche pédagogique. Ces orientations nous ont menés à la mise en place de ce que nous appelons des "Jeux Pédagogiques Collaboratifs Situés " (JPCS). Les deux questions de recherche qui nous ont été posées dans le cadre du projet SEGAREM et qui sont devenues les nôtres sont : 1/ comment accompagner les jeux sérieux par l'approche Réalité Augmentée (RA) et l'approche Interface Tangible (IT)? 2/ comment rendre la conception et la mise en œuvre des JPCS (Jeux Pédagogiques Collaboratifs Situés) plus explicite et plus systématique ? Les réponses que nous présentons dans cette thèse sont les suivantes : 1/ la conception et la mise en œuvre des pupitres interactifs supportant des objets réels augmentés, associés à un protocole de communication existant, proposant un support générique des techniques d'interaction détectée et de prise en compte du contexte physique d'utilisation ; 2/ une approche de production de JPCS se situant après l'étape de scénarisation ludo-pédagogique qui constitue notre cahier des charges. Nous avons basé notre approche sur des modèles pour permettre un support d'expression qui précise les caractéristiques des JPCS. Ces modèles sont soutenus par des éditeurs contextuels et produisent comme résultat des fichiers de descriptions en XML. La projection des descriptions obtenues sur une architecture générique d'exécution du JPCS permet une spécialisation pour obtenir une version exécutable. Dans les six modèles, certains sont adaptés des travaux antérieurs de l'équipe, d'autres issues de la littérature et les derniers sont directement proposés ici. Ces six modèles décrivent l'activité (un modèle d'orchestration de l'activité et un modèle de tâches), la structure de différents environnements, l'état initial de l'environnement et les conditions nécessaires d'un état final et les interactions possibles entre les joueurs et l'environnement. Nos travaux tant sur les pupitres que sur les modèles et le support d'exécution ont été concrétisés dans la mise en place de Lea(r)nIt. Ce JPCS avait pour but de consolider des acquis méthodologiques en Lean Manufacturing par l'utilisation et l'optimisation d'une chaîne de production simulée sur pupitres (supportant interactions tactiles, interactions tangibles et pouvant être assemblés) et sur téléphones mobiles (permettant la mobilité des joueurs-apprenants).

碩士
國立交通大學
國際半導體產業學院
108
In this paper, we successfully build the component model with TCAD based on the actual AlGaN/GaN high electron mobility transistor, and after the simulation results and measurement results have achieved high accuracy. , to optimize the high frequency characteristics. First, we divide the T-type gate into four parts, including the gate length (Lg) of the lower half, the gate height (Hgate), and the top half gate height (Tgate) and the gate tip width. (Wgate), etc., respectively studied the effects of various dimensions on the RF performance of components, and extracted the parameters of high-frequency related components for analysis. Finally, combining the simulation results of the above four parameters, we provide an optimized T-gate design. Compared with the original design, the high-frequency characteristics of the components such as cutoff frequency and maximum oscillation frequency are significantly improved. To sum up, the research proposes a set of design methods for the gate of GaN devices, which can quickly and effectively improve the performance of high-frequency components. In addition, the TCAD component model provided in this paper is not limited to a single component. It is also applicable to the study of high-frequency components with similar materials and structures. It can be widely applied to all similar high-frequency components and is also the value of this research.

碩士
國立臺灣大學
電子工程學研究所
105
The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performance of device due to the tunneling mainly occurring at nanowire surface. To further improve the subthreshold slope, we introduce Si pocket structure. This structure can further decrease the subthreshold slope by Si to Si tunneling mechanism. On the other hand, to further increase the on-state current, we introduce core shell structure. This structure can further increase on-state current because it enlarges the tunnel area. However, the on-state current does not increase proportional to the core length due to the tunnel barrier width in the direction across channel increases as the core length increasing.

Dottorato ""Archimede" in Scienze Comunicazione e Tecnologie, Ciclo XXVIII, a.a. 2015-2016
La promessa dell’energia solare come forma di energia principale è sempre più concreta, ma il nodo cruciale rimane il costo per Watt, che deve essere sempre di più avvicinato o finanche ulteriormente ridotto rispetto a quello delle reti di distribuzione energetiche esistenti. Un lavoro di ottimizzazione in termini di design e parametri di fabbricazione è quindi fondamentale per raggiungere questo obiettivo. Il silicio cristallino è il materiale maggiormente diffuso nell’industria fotovoltaica, per via di diversi fattori, tra cui l’ottimo rapporto costo/prestazioni e la vasta presenza di macchinari per la sua lavorazione, dovute al suo impiego pluridecennale nell’industria microelettronica. Fra le diverse tipologie di celle esistenti è stata scelta un’architettura che presenta entrambi i contatti metallici sul retro, chiamata per questo interdigitated back-contact (iBC). Questo particolare design offre numerosi vantaggi in termini di efficienza massima, costo di produzione ed estetica del pannello, in relazione alle celle convenzionali. Difatti, al momento attuale le maggiori efficienze in celle monogiunzione, sia a livello di laboratorio che di moduli commerciali, sono state ottenute utilizzando questa struttura, sulla quale un’approfondita attività di ricerca può quindi dimostrarsi di notevole interesse. Per il processo di analisi è stato scelto un approccio numerico, tramite l’uso del simulatore di dispositivi TCAD Sentaurus di Synopsys. L’utilizzo di simulazioni offre numerosi punti a favore rispetto all’ottimizzazione per mezzo di step ripetuti di fabbricazione. In primis, un vantaggio in termini di costi, non necessitando di macchinari, materiali e camere pulite. Inoltre un’analisi numerica rende possibile individuare ed evidenziare punti o cause specifiche di perdite o problemi di progettazione. La problematica maggiore di questo approccio risiede nella necessità di garantire l’affidabilità delle simulazioni e ciò è stato ottenuto mediante l’applicazione dello stato dell’arte di tutti i modelli fisici specifici coinvolti nel funzionamento di questo tipo di celle. La tematica di ricerca affrontata è stata quindi la progettazione di celle solari al silicio con contatti interdigitati sul retro tramite l’uso di simulazioni numeriche. Il lavoro di ottimizzazione è stato realizzato investigando uno spazio di parametri di fabbricazione molto vasto e ottenendo informazioni sui trend delle prestazioni al variare degli stessi. Nel primo capitolo è stata illustrata la fisica e i principi di funzionamento di una cella solare, iniziando dall’assorbimento della luce, passando alla sua conversione in cariche elettriche, per finire con la loro raccolta per generare potenza. I meccanismi di ricombinazione e le altre cause di perdite sono stati presentati ed esaminati. Nel secondo capitolo è stata dettagliata l’architettura di una cella solare, evidenziando le diverse regioni e presentando la struttura back-contact. Il terzo capitolo è stato dedicato alla spiegazione delle strategie di simulazione applicate in questo lavoro, con la definizione dei modelli fisici applicati e calibrati per assicurare l’accuratezza richiesta. Nei capitoli quattro e cinque sono stati presentati i risultati delle simulazioni effettuate, realizzate variando le caratteristiche geometriche delle diverse regioni della cella e i profili di drogaggio. Sono stati ottenuti i trend di comportamento relativi ai singoli parametri che, nel caso relativo ai drogaggi, permettono di affermare che per ogni regione l’andamento dell’efficienza ha una forma a campana, che presenta un ottimo di drogaggio relativo in un punto intermedio. Questo comportamento è dovuto, per bassi valori di drogaggio, all’effetto della ricombinazione sul contatto per BSF ed emettitore e della ricombinazione superficiale per l’FSF. Per alti valori di drogaggio, la degradazione dell’efficienza dipende dall’effetto della ricombinazione Auger per BSF ed emettitore e da quella superficiale per l’FSF. Per quanto riguarda i parametri geometrici, le analisi svolte evidenziano che il gap tra emettitore e BSF deve essere quanto più piccolo possibile, dato che all’aumentare della sua dimensione aumentano le perdite per effetto resistivo e di ricombinazione. È stato determinato che il valore ottimale di emitter coverage non è assoluto, ma dipende dalla resistività del bulk e dai drogaggi delle altre regioni, os cillando tra l’80% e il 90%. Per quanto riguarda il pitch ottimale, cioè la distanza tra i contatti, è stato determinato che maggiori efficenze corrispondono a valori minori, principalmente perché all’aumentare della distanza aumentano le resistenze parassite. Infine si è evidenziato che l’aggiunta di un secondo contatto sull’emettitore, equispaziato dal centro della regione, migliora l’efficienza totale poiché riduce le perdite resistive, soprattutto nel caso di celle con emettitori lunghi.
Università della Calabria

Dottorato di Ricerca in Information and Communication Engineering For Pervasive Intelligent Environments, Ciclo XXIX
The most hard-working goal within PV community is to design and manufacture devices featuring high-efficiency at low-cost with the better reliability as possible. The key to achieving this target is to optimize and improve the current fabrication processes as well as the layouts of the devices. TCAD modeling of PV devices turns out to be a powerful tool that lowers laboratory manufacturing costs and accelerates optimization processes by bringing guidelines of how to do it. The modeling in TCAD examines the designs before their implementation, accurately predicting its real behavior. When simulations are correctly calibrated, by changing simulations’ parameters, allow finding ways to improve designs’ parameters or just understand better the internal functioning of these devices. In this regard, this Ph.D. thesis fairly treats the electro-optical numerical simulations of interdigitated back-contact (IBC) c-Si solar cells, which nowadays is the architecture to which industry is trying to pull forward because of its numerous advantages. Among the benefits of this design are their improved efficiency due to the absence of front optical shading or the relative simplicity regarding their massive production. The aim of this thesis, it is focusing on providing guidelines of the optimal design parameters of IBC solar cells, based on the state-of-the-art of advanced numerical simulations. Two main topics are treated, (i) the development of a simplified method to compute the optical profiles ten times faster than the traditional one and (ii) an extensive study on the impact of adding multiple striped metal contacts throughout the emitter region improving the efficiency by reducing the inner series resistance. It was performed a large number of ad-hoc calibrated simulations that sweep wide ranges of modeling parameters (i.e., changing geometric sizes, doping profiles, carriers’ lifetimes, and recombination rates) to investigate their influence over the device operation, allowing to identify the most critical ones. This insight leads a better understanding of this kind of solar cells and helps to appraise ways to refine structures and enhance layouts of real devices for either laboratory or industry.
Università della Calabria

Silicon-based transistors such as MOSFETs have been the preferred choice for decades now for both power as well as high-frequency device applications. The meteoric rise of Silicon was fuelled by the quest for a highly efficient and low-cost switching device. However, the rate of performance improvement in Silicon-based devices is levelling off over the past few years due to underlying theoretical limits set by fundamental physics. It has become extremely challenging to deliver the performance standards at declining costs consistently. GaN has risen as the most promising alternative to traditional Silicon-based technology. The wide bandgap and ability to conduct carriers at very high mobility infuses a positive momentum to the Moor’s law. The fundamental high electric field strength of the material ensures a significant reduction in device size for a given on-resistance and breakdown voltage. It directly translates to lower effective costs per chip. The existing commercial products with 5-10 times enhanced performance compared to Silicon theoretical limits is a strong motivation to further optimize GaN-based devices for power and RF applications. Silicon-based devices have long enjoyed the luxury of an established technology development process, which has been optimized over the years via several iterations and efforts. TCAD based design is the stepping-stone for any technology realization. Employing theoretical knowledge and visualizing the physics in real-time for device design or optimization is the heart of the Silicon Industry. The amount of design cost and time saved by following a consistent CAD design to fabrication approach is enormous. On the contrary, GaN-based devices have unique properties and associated design parameters. The conventional Silicon device design knowledge cannot be extrapolated to GaN-based devices. A wide gap exists between the theoretical and reported performance of GaN-based power and RF devices. A systematic design approach is needed, which involves both simulation and experimental analysis. In this thesis, we have developed a consistent design framework extending from TCAD modelling, device fabrication, experimental analyses to circuit-level feasibility. The co-design approach has enabled the exploration of accurate physical behaviour and helped identify the critical design parameters for GaN-based devices [1,2]. This thesis has been divided into the following threads: In the first part of the work, insights into GaN-based high electron transistors (HEMT) for power and mm-wave applications have been developed. Field Plate technology is the most widely adopted technique for increasing the breakdown voltage in HEMT. In order to achieve optimum performance, it is imperative to scale down the device without compromising the breakdown voltage. However, the conventional lateral field plate configuration is limited by the drift region or gate to drain distance of the device. This issue becomes more severe as the device is scaled down to enhance the on-state performance. This translates to a narrower design window for field plate implementation, which requires more complex and precise lithography alignment. Notably, in the case of RF applications, where the design rules for the lateral device dimensions are rather stringent, the use of a lateral field plate becomes less feasible. Besides, as the device scales down, the contribution of the field plate induced parasitic miller capacitance begins to dominate, resulting in degradation in RF performance parameters such as power gain and cut-off frequency. In order to circumvent these issues, in this thesis, we have proposed two novel field plate architecture- vertical field plate and dual field plate [3,4]. The proposed designs show superior DC, small-signal, and large-signal performance compared to conventional field plate architectures. In addition, various field plate designs have been reported in the past to improve the breakdown performance, namely- source connected, gate connected, and drain connected field plate configurations. However, there is no consensus on the criteria for field plate implementation. The field plate design in HEMT is dependent on the spatial electric field distribution in the channel. Since the electric field is a function of charge distribution across the entire system, the interplay of various charge sources and its implications on field and breakdown voltage must be explored in detail from the device design point of view. Subsequently, we have revealed the interplay of charges (Surface, Polarization and Buffer) and their relative concentrations across the AlGaN/GaN epi-stack governing the electric field distribution and the breakdown mechanism in HEMTs [5]. The investigations are carried out for Schottky, MIS, and p-GaN gate stacks while accounting for possible GaN buffer types (Fe-doped and C-doped). These insights will help to design efficient surface passivation schemes and resolve ambiguities, often observed in experiments, in terms of location of peak electric field (drain side, or gate side, or both) as well as OFF-state conduction and breakdown mechanism (gate injection, or punch-through, or parasitic conduction through buffer or avalanche generation). Besides, these learnings are used to develop unified field plate design guidelines for various scenarios [6]. Attributed to several design/technology/growth parameters to engineer, the design of RF HEMT has become a multi-dimensional engineering problem, which is non-trivial to address from the experimental design of experiments. In this thesis, we have developed an approach for maximizing RF figures of merit parameters of HEMTs, while accounting for design - performance - nonlinearity trade-offs [7,8]. We have investigated the RF performance of a partially recessed architecture by carrying out thorough comparative analyses of design parameters such as barrier type, lateral scaling, and contact resistance. The modelling of mm-wave HEMT enables performance optimization in these devices by employing CAD analysis. The optimized partially recessed architecture has been demonstrated in an RF class A and class AB power amplifier configuration operating from 0.25Thz to 0.6 THz frequency range. It confirms the feasibility of the optimized RF device for various circuit applications [9]. The other key component in any power electronic circuit or THz/mmW system is a Schottky barrier diode. GaN-based heterostructure Schottky Barrier Diodes (SBD), owing to its ability to sustain high electric fields and high temperature while offering exceptionally high current density, low cut-in voltage, has attracted tremendous attention for high power switching applications. In the second part of the thesis, comprehensive TCAD and experimental co-design strategies have been proposed for high power and THz SBD. The critical part of the SBD diode design involves modelling the non-idealities at the Schottky interface and designing physics based process experiments to fix these non-idealities. The fabrication process-induced dangling bonds and interface traps substantially affect the forward and reverse diode performance. These dangling bonds alter the localized energy band level and impact the carrier transport. We have modelled the anode contact interface by accounting for - (1) thin (∼ 5A˚ ) interfacial oxide layer, (2) discrete energy levels in energy band gap due to Nitrogen vacancies, and (3) continuum of trap states due to surface dangling bonds. The trap characteristics such as type, energy levels, and concentration determine the reverse leakage and breakdown voltage. Using the developed physical insights, we then reported (experimentally) an interface engineering technique to reverse the adverse impact of donor interface states on device performance [10]. In this thesis, we also discovered that the impact of Schottky interface quality has a strong correlation to anode recess depth. The Breakdown mechanisms in SBD for unintentionally doped (UID) buffer, Fe-doped buffer, and C-doped buffer are studied. In addition to the impact of anode termination on breakdown voltage, we have also investigated the repercussions of field plate design on other performance figures of merit parameters such as diode current collapse, reverse recovery time, reverse current overshoot, and electro-thermal behaviour [11]. Using the systematic device design approach, we have experimentally demonstrated high power SBD with 15A forward current at 5.5V while having reverse blocking greater than 500V. SBD diode also finds a wide range of applications in THz frequency detection, frequency multiplication, and mixing. The design metrics for THz SBD vastly differs from the one used for high power applications. It is imperative to account for the impact of associated device parasitic elements at high-frequency operating conditions. The planer, multi-finger SBD topology looks most promising due to the ease of integration and high cut-off frequencies demonstrated. This thesis presents the first report on the design and engineering of multi-finger THz SBD [12]. The study investigates the design metrics of AlN/GaN-based multi-finger, lateral SBD and proposes guidelines to maximize THz operation performance.

碩士
國立中興大學
資訊科學與工程學系
102
Ternary Content Addressable memory (TCAM) is widely used in the routing table of the network router. Besides the dynamic power dissipated in?active mode, however, TCAM also consumes?large amount of leakage power in standby mode. In this paper, we propose the vertical partial control (VPC) technique to reduce the?leakage power consumption of TCAM.?Based on the vertiacally continuous "don''t care" feature shown in the routing table, the VPC technique uses segmentation method to?reduce the leakage power dissipated in the TCAM celles with "don''t care" mask. For a 128x32-bit TCAM array, using TSMC 0.18um technology process the simulation results show that the VPC?technique can reduce the?leakage power consumption by 14.24% compared to the conventional TCAM design.

碩士
國立臺灣大學
資訊工程學研究所
99
Due to the characteristic of high-speed search in Ternary Content Addressable Memory (TCAM), it plays an important role in many high-speed devices, however it consumes too much power. The power consumption in conventional NOR-type TCAM is mainly from the dynamic power consumption, in which precharging all the match lines and discharging mismatched match lines during a search operation. Since the number of mismatched match lines is much more than the matched ones, most of the match lines are discharged leading to high power consumption. In this thesis, based on the characteristic of IP prefix stored in TCAM, the mask bit “0” has a continuity property when “0” appears. Therefore, we proposed a method called segmented-precharge technique in TCAM to reduce dynamic power consumption. The experimental results show that the proposed TCAM design with 4 segments is the most appropriate considering power and delay, which has 23.68% power saving and 0.74ns delay in average-case compared to the conventional TCAM.

碩士
國立中興大學
資訊科學與工程學系
102
With shrinking feature size, FinFET device is an attractive alternative to the conventional Bulk CMOS because of the superior ability in suppressing leakage. In this paper we propose a low-power FinFET TCAM design, in which the dynamic voltage control (DVC) technique can effectivley reduce the TCAM leakage power consumption by combining the independent-gate (IG) FinFET technique and the continuous "don''t care" feature of the mask data. Based on PTM 32 nm FinFET technology, the DVC technique can achieve 39.1% leakage power reduction compared with the traditional TCAM design.

碩士
國立交通大學
電子研究所
101
Ternary content addressable memory (TCAM) is extensively adopted in routing tables of network systems and occupied great amounts of energy consumption. In this thesis, energy-efficient TCAM macros have been designed and realized in 40nm LP CMOS process with the sizes of 256x40 and 256x144, respectively. Based on the small drain current in 40nm LP CMOS process, a 16T AND-type TCAM cell with p-type comparison circuits is utilized to increase the Ion/Ioff ratio of the dynamic circuitry. Additionally, the butterfly match-line scheme with AND gates is designed to reduce the wire loading on the evaluation nodes and to ensure that the capacitance of the evaluation nodes are the same in all segments. For further reducing the energy consumption in nano-scale technologies, don’t-care-based ripple search-line and ripple bit-lines are realized to decrease both the switching activities and wire capacitance of search-lines and bit-lines. Moreover, the column-based data-aware power control is also employed to realize the leakage power reduction, write-ability and static noise margin (SNM) improvements by the power gating devices. Consequently, the timing of the power switching is tolerant to PVT variation and Vt scatter by the replica circuitry. The energy-efficient 256x40 and 256x144 TCAM macros are implemented using UMC 40nm LP CMOS technology, and the experimental results demonstrate a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy metric of the TCAM macro of 0.461 fJ/bit/search.

碩士
國立彰化師範大學
電子工程學系
104
Content-addressable memory (CAM) compares input search data in parallel against a table of stored data, and returns the address of the matching data. CAMs can be used in a wide variety of applications requiring high-speed parallel search. These applications include pattern recognition, data compression, and network address translation. The parallel search operation of CAM consumes a significant amount of energy due to the charging and discharging of the search lines and match lines with large capacitance. As the feature size continues to shrink and the corresponding transistor density increases, the planar MOSFET suffer from the increased subthershold and gate leakage currents. FinFET is considered as one of the best substitutes for planar MOSFET technology in the sub-20 nm regime. This thesis proposed two new sensing techniques for low power Ternary Content-Addressable Memory (TCAM). Matchline-Accelerating Sense Amplifiers (MLA-SA) using pulse current to reduce the power consumption of Matchlien in TCAM and employs the feedback network to boost the search speed of TCAM. We proposed a second Matchline sensing technique call “Matchline-Accelerating Low-Power sense amplifiers (MLA-LP-SA) “. MLA-LP-SA using the pulse current to charge the Matchlines and then detects the voltage development on Matchlines to determine whether the Matchline is matched. In contrast to conventional MLSAs, which adjust the charging current to the match lines based on matching result, MLA-LP-SA will not provide additional current to the match lines regardless of the matching result. We have employed Hspice to evaluate various Matchline sensing circuits using the Berkeley Short-channel IGFET Model (BSIM) common multi-gate (CMG) FinFETs with supply voltage of 0.6V and temperature of 25℃. The simulation results show that the proposed MLA-SA can reduce the energy consumption by 39%-65% and 25%-44% compared to the conventional Precharge MLSA and Current-Race MLSA. The proposed MLA-LP-SA can reduce the energy consumption by 66%-73% and 54%-63%, compared to the conventional Precharge MLSA and Current-Race MLSA. MLA-SA and MLA-LP-SA, respectively, can achieve a search time of 150.2 ps and 89.6 ps, and Energy-delay product of 0.775×10-27JS and 0.372×10-27JS, for conventional Precharge MLSA and Current-Race MLSA decreased by 64.38%, 51.65% and 82.9%, 76.79%. Keywords: Content-addressable memory, FinFET devices, Matchline Sense Amplifiers

碩士
國立交通大學
電子工程學系 電子研究所
104
Even though ternary content addressable (TCAM) is the power hungry circuitry, it still be extensively adopted in routing table of network systems by its high speed and unique. With the develop of the portable devices and the rise of Internet of Things (IoT), the issue of energy efficiency and low supply voltage become a major trend in SoC. If we want to introduce TCAM into IoT. Its power hungry problem should be solved first. However, conventional 6T SRAM is hard to work in low supply voltage duo to read/write ability degradation which caused by severely process variation in advance process. We realize our design in umc 28nm high-k metal-gate (HKMG) CMOS technology. We introduce the 6T Mini-array into TCAM and let it can even operate at 0.4V. Additionally, we use hierarchical PRE, power gating and ripple search-line in our design which let total energy consumption less.