Relevant bibliographies by topics / TCAD Design

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'TCAD Design'

Author: Grafiati
Published: 6 September 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'TCAD Design.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "TCAD Design"

1

Bellini, Marco, and Lars Knoll. "Advanced TCAD Design Techniques for the Performance Improvement of SiC MOSFETs." Materials Science Forum 1004 (July 2020): 865–71. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.865.

Full text
Abstract:
This paper introduces novel TCAD post-processing techniques for SiC MOSFETs with the aim of understanding which parts of the device limit the on-state performance. Typically, analytical models of MOSFETs are used as a starting point for the TCAD design process or as a simple way to understand the influence of complex design choices, as discussed in the works of [1-3]. These lumped element models result in a relatively straightforward approach because they explicitly identify the contributions of the regions of the transistor, facilitating the understanding of basic design choices and performance trade-offs. However, the simplifications introduced in analytical models limit their applicability to advanced device structures such as aggressively scaled transistors or trench MOSFETs with cellular layout. This paper presents mathematical techniques based on post-processing of TCAD simulations that combine the accuracy of numerical Finite Element studies with the interpretability of lumped element analytical models.
APA, Harvard, Vancouver, ISO, and other styles
2

Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

Full text
Abstract:
In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design and device operation in electrical circuits.
APA, Harvard, Vancouver, ISO, and other styles
3

Rehman, Atta Ur, Amna Siddiqui, Muhammad Nadeem, and Muhammad Usman. "Improved PERC Solar Cell Design by TCAD Simulation." Proceedings of the Pakistan Academy of Sciences: A. Physical and Computational Sciences 58, no. 4 (March 28, 2022): 61–67. http://dx.doi.org/10.53560/ppasa(58-4)637.

Full text
Abstract:
In this work, we aim to identify the performance limiting factors and consequently improve the performance of PERC solar cells through extensive TCAD based device simulation and modelling. Initially, a simplified planar PERC solar cell structure is simulated in Silvaco (Athena/Atlas), where the device geometry is selected according to an experimentally fabricated cell with an efficiency of 17.86%. The J-V curves and solar cell parameters such as Jsc, FF, Voc and efficiency (η) of the simulated cell are then fitted to the experimental performance parameters by incorporating relevant models as suggested by the literature. These include: carriers’ generation-recombination, mobility, statistics and bandgap narrowing. A good agreement is obtained, where the average percentage difference between simulated and experimental performance parameters is 0.65%. The solar cell performance is then improved to 21.52% by optimising the anti-reflective coating stack composition and thickness, and adding surface texturing. This increase in efficiency is attributed to lower surface recombination and reduced reflection due to light trapping. In addition, a textured front surface enhances the path-length of light, causing it to undergo multiple internal reflections which further increases light trapping, thus increasing Jsc by 7.31 mA/cm2.
APA, Harvard, Vancouver, ISO, and other styles
4

Pan, Zijin, Cheng Li, Mengfu Di, Feilong Zhang, and Albert Wang. "3D TCAD Analysis Enabling ESD Layout Design Optimization." IEEE Journal of the Electron Devices Society 8 (2020): 1289–96. http://dx.doi.org/10.1109/jeds.2020.3027034.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Woo, Sola, Juhee Jeon, and Sangsig Kim. "Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning." Micromachines 14, no. 3 (February 21, 2023): 504. http://dx.doi.org/10.3390/mi14030504.

Full text
Abstract:
In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current–voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.
APA, Harvard, Vancouver, ISO, and other styles
6

Singh, Vivek. "Relevance of technology computer aided design (TCAD) to process-aware design." Journal of Micro/Nanolithography, MEMS, and MOEMS 1, no. 3 (October 1, 2002): 290. http://dx.doi.org/10.1117/1.1508411.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Chen, Yu-Guang, Hui Geng, Kuan-Yu Lai, Yiyu Shi, and Shih-Chieh Chang. "Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 4 (April 2014): 507–18. http://dx.doi.org/10.1109/tcad.2013.2293881.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Wang, Ke, Haodong Jiang, Yiming Liao, Yue Xu, Feng Yan, and Xiaoli Ji. "Degradation Prediction of GaN HEMTs under Hot-Electron Stress Based on ML-TCAD Approach." Electronics 11, no. 21 (November 2, 2022): 3582. http://dx.doi.org/10.3390/electronics11213582.

Full text
Abstract:
In this paper, a novel approach that combines technology computer-aided design (TCAD) simulation and machine learning (ML) techniques is demonstrated to assist the analysis of the performance degradation of GaN HEMTs under hot-electron stress. TCAD is used to simulate the statistical effect of hot-electron-induced, electrically active defects on device performance, while the artificial neural network (ANN) algorithm is tested for reproducing the simulation results. The results show that the ML-TCAD approach can not only rapidly obtain the performance degradation of GaN HEMTs, but can accurately predict the progressive failure under the work conditions with a mean squared error (MSE) of 0.2, informing the possibility of quantitative failure data analysis and rapid defect extraction via the ML-TCAD approach.
APA, Harvard, Vancouver, ISO, and other styles
9

Ma, Qiang, and Evangeline F. Y. Young. "Multivoltage Floorplan Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 4 (April 2010): 607–17. http://dx.doi.org/10.1109/tcad.2010.2042895.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Nandi, Prajit, Hirak Talukdar, Dhiraj Kumar, and Ashvin Kumar G. Katakwar. "A Novel Approach to Design SAR-ADC: Design Partitioning Method." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 3 (March 2016): 346–56. http://dx.doi.org/10.1109/tcad.2015.2474379.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "TCAD Design"

1

Quiroga, Andrés. "Investigation and development of advanced Si/SiGe and Si/SiGeC Heterojunction Bipolar Transistors by means of Technology Modeling." Thesis, Paris 11, 2013. http://www.theses.fr/2013PA112273/document.

Full text
Abstract:
Le travail porte sur le développement et l’optimisation de transistors bipolaires à hétérojonction (TBH) SiGe et SiGeC par conception technologique assistée par ordinateur (TCAD). L'objectif est d'aboutir à un dispositif performant réalisable technologiquement, en tenant compte de tous les paramètres : étapes de fabrication technologiques, topologie du transistor, modèles physiques. Les études menées permettent d’atteindre les meilleures performances, en particulier une amélioration importante de la fréquence maximale d’oscillation (fMAX). Ce travail est la première approche développée pour la simulation des TBH SiGeC qui prend en compte l'impact de la contrainte et de la teneur en germanium et en carbone dans la base; conjointement pour les simulations des procédés de fabrication et les simulations électriques.Pour ce travail, nous avons développé et implémenté dans le simulateur TCAD des méthodes d'extraction de fMAX prenant en compte les éléments parasites intrinsèques et extrinsèques. Nous avons développé et implémenté un modèle pour la densité effective d’états fonction de la teneur en germanium et en carbone dans la base. Les modèles pour la bande interdite, la mobilité et le temps de relaxation de l'énergie sont calibrés sur la base de simulations Monte-Carlo.Les différentes analyses présentées dans cette thèse portent sur six variantes technologiques de TBH. Trois nouvelles architectures de TBH SiGeC avancés ont été élaborées et proposées pour des besoins basse et haute performance. Grace aux résultats obtenus, le meilleur compromis entre les différents paramètres technologiques et dimensionnels permettent de fabriquer un TBH SiGeC avec une valeur de fMAX de 500 GHz, réalisant ainsi l’objectif principal de la thèse
The present work investigates the technology development of state-of-the-art SiGe and SiGeC Heterojunction Bipolar Transistors (HBT) by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, a better understanding of charge transport, and to facilitate the development and optimization of SiGe and SiGeC HBT devices.The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.In this work we will work with the successive evolutions of B3T, B4T and B5T technologies. For each new device fMAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz, respectively.Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for fMAX and the carrier transport in extremely scaled HBTs.Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation.Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase fMAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of fMAX
APA, Harvard, Vancouver, ISO, and other styles
2

Lemoigne, Pascal. "Simulation de la variabilité du transistor MOS." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10214/document.

Full text
Abstract:
L’augmentation de la densité d’intégration des circuits intégrés nous a amené à étudier, dans le cadre du développement de la technologie CMOS 45 nm, les sources de variabilité inhérentes aux procédés de fabrication utilisés pour ce nœud technologique, et à en déterminer les composantes principales,dans le but ultime de permettre la simulation précise de l’impact de la variabilité technologique à la fois au niveau transistor et circuit. Après un état de l’art des sources de variabilité du transistor MOS et des moyens de simulation associés,ce travail s'est orienté sur les fluctuations d'un facteur technologique difficilement accessible à la mesure statistique qu'est le dopage canal. Ensuite le nœud 45 nm a été étudié expérimentalement via un plan d'expériences.Ceci a permis de connaitre les variations naturelles des facteurs technologiques mais surtout les sensibilités des performances électriques vis-à-vis de ces facteurs.Nous avons pu ainsi identifier les causes prépondérantes de variabilité dues au procédé.Enfin, nous proposons d’améliorer la prise en compte des déviations des facteurs process dans les simulations Monte-Carlo et pire-cas appliquées aux modèles compacts au regard de ces observations expérimentales
Continuous improvement in integrated circuits density of integration lead us to study process-induced variations in the framework of the 45 nm node, and to determine their principal contributions with the ultimate goal being to allow an accurate simulation of both transistor and circuit level variability. This work starts with a study of the state of the art of variability sources of the MOS transistor and associated simulation means. Then it focuses on the fluctuations of the channel doping, which is a difficult factor to measure statistically.After that we study the 45 nm node through a design of experiment which let us learn about natural variations of process factors but mostly about electrical performances sensitivity to those factors.Thanks to that we could identify major causes of process-induced variability at this stage of this node development. At last, with respect to those experimental results, we propose to enhance the taking in account of process variations in Monte-Carlo and corner simulations applied to compact models
APA, Harvard, Vancouver, ISO, and other styles
3

PEZZAROSSA, MICHELE. "The deep Al-based JTE: development and industrialization of a novel termination design for high-power semiconductor devices." Doctoral thesis, Politecnico di Torino, 2022. http://hdl.handle.net/11583/2964780.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Quiroga, Andres. "Investigation and development of advanced Si/SiGe and Si/SiGeC Heterojunction Bipolar Transistors by means of Technology Modeling." Phd thesis, Université Paris Sud - Paris XI, 2013. http://tel.archives-ouvertes.fr/tel-00938619.

Full text
Abstract:
The present work investigates the technology development of state-of-the-art SiGe and SiGeC Heterojunction Bipolar Transistors (HBT) by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, a better understanding of charge transport, and to facilitate the development and optimization of SiGe and SiGeC HBT devices.The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.In this work we will work with the successive evolutions of B3T, B4T and B5T technologies. For each new device fMAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz, respectively.Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for fMAX and the carrier transport in extremely scaled HBTs.Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation.Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase fMAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of fMAX.
APA, Harvard, Vancouver, ISO, and other styles
5

Cleveland, William Peter. "Improving pilot understanding of TCAS through the traffic situation display." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47726.

Full text
Abstract:
The goal of this thesis is to improve pilot understanding of the Traffic alert and Collision Avoidance System (TCAS) by changing the Traffic Situation Display (TSD). This is supported by two objectives. The first objective is to create an integrated, realistic air traffic environment. This serves as an experimental platform for testing and evaluating future TCAS TSDs. The simulator environment includes a desktop flight simulator, background air traffic simulator, and intruder aircraft. The intruder aircraft uses seven dimensional waypoints to robustly follow trajectories and cause specific resolution advisories. Second, the relative benefits of, and potential concerns with, new TCAS TSDs are explored using a structured, iterative design process with subject matter ex- perts (SMEs). Incremental changes to the TSD were implemented into the simulator environment. SMEs evaluated the displays and potential points of confusion were identified. Several display features are discussed and implemented for future evaluations. These include boundary lines of TCAS variables depicted on the TSD and on a vertical situation display, speed lines which vary with the TCAS estimate of time to closest point of approach, and a prediction of the safe altitude target during a resolution advisory. Scenarios which may be confusing or misleading are discussed. These scenarios may be ameliorated or exacerbated by display features. This information is useful to guide both design and certification or operational approval and is a starting place for future TCAS experiments.
APA, Harvard, Vancouver, ISO, and other styles
6

Musetha, Rendani D. "The design of CAN nodes for minimising cables on the SUNSAT's TCMD system." Thesis, Stellenbosch : Stellenbosch University, 2003. http://hdl.handle.net/10019.1/49793.

Full text
Abstract:
Thesis (MScEng)--Stellenbosch University, 2003.
ENGLISH ABSTRACT: The aim of this thesis is to investigate a design of a microcontroller based embedded system that will be used to minimise cable harness on the SUNSAT micro-satellite. The system is called CAN node. The CAN node(s) implements CAN (Controller Area Network) serial bus architecture protocol. The protocol is implemented on the two nodes to transport data from the TCMD tot he 0 ther trays 0 f SUNSAT. CAN node( s) design proj ect focuses on the TCMD tray, because it is the central point for data communication in SUNSAT and it acts as the eyes and hands of the satellite's operator. As a result most of the communication cables are located at this tray. The two nodes are called TX-node and RX-nodes. The TX-node is used to collect data from the TCMD tray and transmits them serially to RX-node. The RX-nodes receives the TCMD data from TX-node and transmits these data to their respective nodes. In application RX-nodes need to be ten, but only one is used for testing purpose. The design had its shortcomings, of which they are discussed in this thesis. The recommendations of an ideal system are also given to elaborate how the system should behave in the real situation. Despite its shortcomings, the CAN node(s) project has successfully proven that cable harness on the TCMD tray of SUNSAT can be minimised by using CAN technology.
AFRIKAANSE OPSOMMING: Die doel van hierdie tesis is om die ontwerp van 'n mikro-beheerder gebaseerde stelsel wat die SUNSA T mikro-satelliet kabel harnas sal verklein, te ondersoek. Die stelsel word die CAN nodus genoem. Die CAN nodus implementeer die CAN (Controller Area Network) bus argitektuur protokol. Die protokol is op twee nodusse geïmplementeer om data vanaf die TCMD na ander laaie van SUNSAT te voer. Die CAN nodus ontwerp fokus op die TCMD laai, want dit is die sentrale punt vir data kommunikasie in SUNSA T en dit tree soos die oog en hande van die satelliet operateur op. As 'n gevolg, is die meeste van die kommunikasie kabels in hierdie laai. Die twee nodusse is genoem TXnodus en RX-nodus. TX-nodus word gebruik om die data van die TCMD af te kollekteer en dan versprei hulle tot hulle onderskeie nodusse. In die toepaslik moet daar tien RX-nodusse wees, maar net een is gebruik terwille van die toets. Die ontwerp het sy eie tekortkomings, wat in hierdie tesis bespreek word. Die rekommendasie van 'n ideale stelsel is ook gemaak om te bewys hoe die stelsel dit in 'n ware situasie moet gedra. Ongeag die tekortkomings daarvan, het die CAN-nodus projek suksesvol bewys dat die kabel harnas in die TCMD laai van SUNSAT kan verminder word deur die gebruik van die CAN tegnologie.
APA, Harvard, Vancouver, ISO, and other styles
7

Rosenbaum, Tommy. "Performance prediction of a future silicon-germanium heterojunction bipolar transistor technology using a heterogeneous set of simulation tools and approaches." Thesis, Bordeaux, 2017. http://www.theses.fr/2017BORD0550/document.

Full text
Abstract:
Les procédés bipolaires semi-conducteurs complémentaires à oxyde de métal (BiCMOS) peuvent être considérés comme étant la solution la plus généralepour les produits RF car ils combinent la fabrication sophistiquée du CMOSavec la vitesse et les capacités de conduction des transistors bipolaires silicium germanium(SiGe) à hétérojonction (HBT). Les HBTs, réciproquement, sontles principaux concurrents pour combler partiellement l'écart de térahertzqui décrit la plage dans laquelle les fréquences générées par les transistors etles lasers ne se chevauchent pas (environ 0.3 THz à 30 THz). A_n d'évaluerles capacités de ces dispositifs futurs, une méthodologie de prévision fiable estsouhaitable. L'utilisation d'un ensemble hétérogène d'outils et de méthodes desimulations permet d'atteindre successivement cet objectif et est avantageusepour la résolution des problèmes. Plusieurs domaines scientifiques sont combinés, tel que la technologie de conception assistée par ordinateur (TCAO),la modélisation compacte et l'extraction des paramètres.Afin de créer une base pour l'environnement de simulation et d'améliorerla confirmabilité pour les lecteurs, les modèles de matériaux utilisés pour lesapproches hydrodynamiques et de diffusion par conduction sont introduits dèsle début de la thèse. Les modèles physiques sont principalement fondés surdes données de la littérature basées sur simulations Monte Carlo (MC) ou dessimulations déterministes de l'équation de transport de Boltzmann (BTE).Néanmoins, le module de TCAO doit être aussi étalonné sur les données demesure pour une prévision fiable des performances des HBTs. L'approchecorrespondante d'étalonnage est basée sur les mesures d'une technologie depointe de HBT SiGe pour laquelle un ensemble de paramètres spécifiques àla technologie du modèle compact HICUM/L2 est extrait pour les versionsdu transistor à haute vitesse, moyenne et haute tension. En s'aidant de cesrésultats, les caractéristiques du transistor unidimensionnel qui sont généréesservent de référence pour le profil de dopage et l'étalonnage du modèle. Enélaborant des comparaisons entre les données de références basées sur les mesureset les simulations, la thèse fait progresser l'état actuel des prévisionsbasées sur la technologie CAO et démontre la faisabilité de l'approche.Enfin, une technologie future de 28nm performante est prédite en appliquantla méthodologie hétérogène. Sur la base des résultats de TCAO, leslimites de la technologie sont soulignées
Bipolar complementary metal-oxide-semiconductor (BiCMOS) processescan be considered as the most general solution for RF products, as theycombine the mature manufacturing tools of CMOS with the speed and drivecapabilities of silicon-germanium (SiGe) heterojunction bipolar transistors(HBTs). HBTs in turn are major contenders for partially filling the terahertzgap, which describes the range in which the frequencies generated bytransistors and lasers do not overlap (approximately 0.3THz to 30 THz). Toevaluate the capabilities of such future devices, a reliable prediction methodologyis desirable. Using a heterogeneous set of simulation tools and approachesallows to achieve this goal successively and is beneficial for troubleshooting.Various scientific fields are combined, such as technology computer-aided design(TCAD), compact modeling and parameter extraction.To create a foundation for the simulation environment and to ensure reproducibility,the used material models of the hydrodynamic and drift-diffusionapproaches are introduced in the beginning of this thesis. The physical modelsare mainly based on literature data of Monte Carlo (MC) or deterministicsimulations of the Boltzmann transport equation (BTE). However, the TCADdeck must be calibrated on measurement data too for a reliable performanceprediction of HBTs. The corresponding calibration approach is based onmeasurements of an advanced SiGe HBT technology for which a technology specific parameter set of the HICUM/L2 compact model is extracted for thehigh-speed, medium-voltage and high-voltage transistor versions. With thehelp of the results, one-dimensional transistor characteristics are generatedthat serve as reference for the doping profile and model calibration. By performingelaborate comparisons between measurement-based reference dataand simulations, the thesis advances the state-of-the-art of TCAD-based predictionsand proofs the feasibility of the approach.Finally, the performance of a future technology in 28nm is predicted byapplying the heterogeneous methodology. On the basis of the TCAD results,bottlenecks of the technology are identified
Bipolare komplementäre Metall-Oxid-Halbleiter (BiCMOS) Prozesse bietenhervorragende Rahmenbedingungen um Hochfrequenzanwendungen zurealisieren, da sie die fortschrittliche Fertigungstechnik von CMOS mit derGeschwindigkeit und Treiberleistung von Silizium-Germanium (SiGe) Heterostruktur-Bipolartransistoren (HBTs) verknüpfen. Zudem sind HBTs bedeutendeWettbewerber für die teilweise Überbrückung der Terahertz-Lücke, derFrequenzbereich zwischen Transistoren (< 0.3 THz) und Lasern (> 30 THz).Um die Leistungsfähigkeit solcher zukünftigen Bauelemente zu bewerten, isteine zuverlässige Methodologie zur Vorhersage notwendig. Die Verwendungeiner heterogenen Zusammenstellung von Simulationstools und Lösungsansätzenerlaubt es dieses Ziel schrittweise zu erreichen und erleichtert die Fehler-_ndung. Verschiedene wissenschaftliche Bereiche werden kombiniert, wie zumBeispiel der rechnergestützte Entwurf für Technologie (TCAD), die Kompaktmodellierungund Parameterextraktion.Die verwendeten Modelle des hydrodynamischen Simulationsansatzes werdenzu Beginn der Arbeit vorgestellt, um die Simulationseinstellung zu erläuternund somit die Nachvollziehbarkeit für den Leser zu verbessern. Die physikalischenModelle basieren hauptsächlich auf Literaturdaten von Monte Carlo(MC) oder deterministischen Simulationen der Boltzmann-Transportgleichung(BTE). Für eine zuverlässige Vorhersage der Eigenschaften von HBTs muss dieTCAD Kon_guration jedoch zusätzlich auf der Grundlage von Messdaten kalibriertwerden. Der zugehörige Ansatz zur Kalibrierung beruht auf Messungeneiner fortschrittlichen SiGe HBT Technologie, für welche ein technologiespezifischer HICUM/L2 Parametersatz für die high-speed, medium-voltage undhigh-voltage Transistoren extrahiert wird. Mit diesen Ergebnissen werden eindimensionaleTransistorcharakteristiken generiert, die als Referenzdaten fürdie Kalibrierung von Dotierungspro_len und physikalischer Modelle genutztwerden. Der ausführliche Vergleich dieser Referenz- und Messdaten mit Simulationengeht über den Stand der Technik TCAD-basierender Vorhersagenhinaus und weist die Machbarkeit des heterogenen Ansatzes nach.Schlieÿlich wird die Leistungsfähigkeit einer zukünftigen Technologie in28nm unter Anwendung der heterogenen Methodik vorhergesagt. Anhand derTCAD Ergebnisse wird auf Engpässe der Technologie hingewiesen
APA, Harvard, Vancouver, ISO, and other styles
8

Gnawali, Krishna Prasad. "EMERGING MEMORY-BASED DESIGNS AND RESILIENCY TO RADIATION EFFECTS IN ICS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1863.

Full text
Abstract:
The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..
APA, Harvard, Vancouver, ISO, and other styles
9

Guyonneau, David. "Contribution à la détermination de surfaces conjuguées pour la transmission de puissance." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4134.

Full text
Abstract:
Les travaux présentés à travers ce manuscrit s'inscrivent dans un contexte de recherches exploratoires sur l'optimisation des surfaces engrenantes. Après une étude approfondie de l'emploi des engrenages dans un environnement aéronautique, l'élaboration d'une nouvelle méthodologie de génération de profils de denture est proposée. Les travaux s'attachent à caractériser le comportement mécanique spécifique d'un montage d'engrenages dans les Boites de Transmission de Puissances (BTP) d'hélicoptère.Un outil informatique a été créé dans le module VBA (Visual Basic Application) d'Excel. Il permet de créer automatiquement des profils de denture conjugués et optimisés. Il a l'avantage de définir analytiquement plusieurs grandeurs physiques. L'outil a ainsi pour objectif de proposer des profils de denture optimisés selon plusieurs critères. Les « objectifs » retenus sont le rendement et la contrainte équivalente de Hertz au contact suivant le critère de Von Mises.Les travaux s'articulent autour de trois axes : - la reconstruction de profils conjugués de denture par une approche novatrice basée sur le « contact », - la construction de critères physiques (glissement, pression, contrainte, …), - la recherche de profils de denture optimaux en utilisant la simulation de Monte Carlo.Enfin, la perspective de rendre générique cette méthode afin qu'elle puisse générer n'importe quels types d'engrenage est envisagée en fin de manuscrit
The work described in the present manuscript is part of exploratory researches dealing with gears meshing surfaces optimization. After a short study of gears used in an aeronautical environment, the development of an innovative tool for tooth profile design is defined. Then, the specific behavior of a gear mesh within a helicopter main gearbox (MGB) is evaluated.A VBA software has been coded under MS Excel to generate conjugated and optimized gear tooth profiles. It advantageously defines and uses several physical parameters with their analytical formulation. The software provides at the user optimized tooth profiles according to a couple of criteria. The two “objective” functions evaluated are the efficiency and the Hertz equivalent stress within the contact using the Von Mises criterion.The work has been focused on three aspects:- The design of conjugated tooth profiles by contact sharing,- The definition of the relevant physical parameters,- The optimization of tooth profiles using Monte Carlo SimulationEventually, a generic method to design gear profiles, taking into account any physical parameters related to a gear mesh, could be expected as a future of this thesis work
APA, Harvard, Vancouver, ISO, and other styles
10

Delomier, Florent. "Jeux pédagogiques collaboratifs situés : conception et mise en oeuvre dirigées par les modèles." Phd thesis, Ecole Centrale de Lyon, 2013. http://tel.archives-ouvertes.fr/tel-00995808.

Full text
Abstract:
Un jeu pédagogique constitue une déclinaison relative à l'apprentissage du concept de jeu sérieux (serious game). Ce type d'outil permet la ludification (gamification) de l'activité afin d'utiliser des éléments de jeu dans un contexte non ludique et conduit à catalyser l'attention, faire accroître l'engagement et augmenter la motivation des joueurs-apprenants dans les situations d'apprentissage. Les jeux pédagogiques reposent sur la mise en situation et l'immersion des apprenants, utilisant les ressorts ludiques dans des simulations axées vers la résolution de problèmes. Parmi des recherches antérieures, certains retours d'expériences font écho d'une trop grande artificialité de l'activité notamment par manque de contextualisation de l'apprentissage dans l'environnement d'utilisation des connaissances apprises. Nous avons proposé la mise en place un environnement mixte (physique et numérique) et l'utilisation de techniques collaboratives pour raffiner l'approche pédagogique. Ces orientations nous ont menés à la mise en place de ce que nous appelons des "Jeux Pédagogiques Collaboratifs Situés " (JPCS). Les deux questions de recherche qui nous ont été posées dans le cadre du projet SEGAREM et qui sont devenues les nôtres sont : 1/ comment accompagner les jeux sérieux par l'approche Réalité Augmentée (RA) et l'approche Interface Tangible (IT)? 2/ comment rendre la conception et la mise en œuvre des JPCS (Jeux Pédagogiques Collaboratifs Situés) plus explicite et plus systématique ? Les réponses que nous présentons dans cette thèse sont les suivantes : 1/ la conception et la mise en œuvre des pupitres interactifs supportant des objets réels augmentés, associés à un protocole de communication existant, proposant un support générique des techniques d'interaction détectée et de prise en compte du contexte physique d'utilisation ; 2/ une approche de production de JPCS se situant après l'étape de scénarisation ludo-pédagogique qui constitue notre cahier des charges. Nous avons basé notre approche sur des modèles pour permettre un support d'expression qui précise les caractéristiques des JPCS. Ces modèles sont soutenus par des éditeurs contextuels et produisent comme résultat des fichiers de descriptions en XML. La projection des descriptions obtenues sur une architecture générique d'exécution du JPCS permet une spécialisation pour obtenir une version exécutable. Dans les six modèles, certains sont adaptés des travaux antérieurs de l'équipe, d'autres issues de la littérature et les derniers sont directement proposés ici. Ces six modèles décrivent l'activité (un modèle d'orchestration de l'activité et un modèle de tâches), la structure de différents environnements, l'état initial de l'environnement et les conditions nécessaires d'un état final et les interactions possibles entre les joueurs et l'environnement. Nos travaux tant sur les pupitres que sur les modèles et le support d'exécution ont été concrétisés dans la mise en place de Lea(r)nIt. Ce JPCS avait pour but de consolider des acquis méthodologiques en Lean Manufacturing par l'utilisation et l'optimisation d'une chaîne de production simulée sur pupitres (supportant interactions tactiles, interactions tangibles et pouvant être assemblés) et sur téléphones mobiles (permettant la mobilité des joueurs-apprenants).
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "TCAD Design"

1

K, Maiti C., and Institution of Engineering and Technology, eds. TCAD for Si, SiGe and GaAs integrated circuits. London: Institution of Engineering and Technology, 2007.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Saad, Yves. TCAD-based three-dimensional modeling of nonvolatile memories. Konstanz: Hartung-Gorre, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Hellings, Geert. High Mobility and Quantum Well Transistors: Design and TCAD Simulation. Dordrecht: Springer Netherlands, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Gappisch, Steffen. TCAD-based development of a flash-EPROM technology. Konstanz: Hartung-Gorre, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Gull, Ronald Dumeng. TCAD based development of a polysilicon emitter transistor in a BiCMOS technology. Konstanz: Hartung-Gorre, 1997.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Maiti, Chinmay K. Introducing Technology Computer-Aided Design (TCAD). Jenny Stanford Publishing, 2017. http://dx.doi.org/10.1201/9781315364506.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Hellings, Geert, and Kristin De Meyer. High Mobility and Quantum Well Transistors: Design and TCAD Simulation. Springer, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Hellings, Geert, and Kristin De Meyer. High Mobility and Quantum Well Transistors: Design and TCAD Simulation. Springer Netherlands, 2015.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Li, Simon, and Suihua Li. 3D TCAD Simulation for Semiconductor Processes, Devices and Optoelectronics. Springer, 2011.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

Li, Simon, and Suihua Li. 3D TCAD Simulation for Semiconductor Processes, Devices and Optoelectronics. Springer, 2016.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "TCAD Design"

1

Masuda, H., H. Pimingstorfer, H. Sato, K. Tsuneno, K. Ichikawa, H. Tobe, H. Miyazawa, et al. "Applied TCAD in Mega-Bits Memory Design." In Simulation of Semiconductor Devices and Processes, 21–24. Vienna: Springer Vienna, 1993. http://dx.doi.org/10.1007/978-3-7091-6657-4_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

López-Serrano, José, and Andrzej J. Strojwas. "Layout Design Rule Generation with TCAD Tools for Manufacturing." In Simulation of Semiconductor Devices and Processes, 62–65. Vienna: Springer Vienna, 1995. http://dx.doi.org/10.1007/978-3-7091-6619-2_14.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Miura, N., H. Hayashi, H. Komatsubara, M. Mochizuki, H. Matsuhashi, Y. Kajita, and K. Fukuda. "Tcad Driven Process Design of 0.15μm Fully-Depleted Soi Transistor for Low Power Applications." In Simulation of Semiconductor Processes and Devices 2001, 284–87. Vienna: Springer Vienna, 2001. http://dx.doi.org/10.1007/978-3-7091-6244-6_63.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Srivastava, Ajay Kumar. "Si Detector for HEP and Photon Science Experiments: How to Design Detectors by TCAD Simulation." In Si Detectors and Characterization for HEP and Photon Science Experiment, 149–72. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-19531-1_11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Malavena, Gerardo. "Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks." In Special Topics in Information Technology, 43–53. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-85918-3_4.

Full text
Abstract:
AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.
APA, Harvard, Vancouver, ISO, and other styles
6

Jin, Du Seok, Jung-lok Yu, Jun-hyung Lee, Jongsuk Ruth Lee, Kumwon Cho, and Hoon Ryu. "On Development of an Open Platform for High Performance Computing Services: Design of TCAD Meta-Data Schema and Its Application to Computational Nanoelectronics." In Lecture Notes in Electrical Engineering, 921–29. Dordrecht: Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6516-0_101.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Huang, Yi, Peng Wen, Bo Song, and Yan Li. "An Auto TCD Probe Design and Visualization." In Brain Informatics, 486–95. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-05587-5_46.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Luo, Donghua, Junling Pan, and Xingwei Zhou. "Design of TCD Spectrum Analysis System Based on FPGA and ARM9." In The 2021 International Conference on Machine Learning and Big Data Analytics for IoT Security and Privacy, 746–52. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-89508-2_96.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Li, Jie, Xianfen Diao, Kai Zhan, and Zhengdi Qin. "A Full Digital Design of TCD Ultrasound System Using Normal Pulse and Coded Excitation." In IFMBE Proceedings, 136–39. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-12262-5_38.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Ghosh, Puja, and P. Rangababu. "Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video Processing." In Communications in Computer and Information Science, 557–69. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_54.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "TCAD Design"

1

Singh, Vivek K., and Jorge Garcia-Colevatti. "Relevance of TCAD to process-aware design." In Design, Process Integration, and Characterization for Microelectronics, edited by Alexander Starikov and Kenneth W. Tobin, Jr. SPIE, 2002. http://dx.doi.org/10.1117/12.475675.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Massey, J. Greg, Lan Luo, Peter Smith, and Richard Wachnik. "Large-Scale Thermal TCAD Simulations of 7nm Circuits." In 2021 IEEE Microelectronics Design & Test Symposium (MDTS). IEEE, 2021. http://dx.doi.org/10.1109/mdts52103.2021.9476141.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Triltsch, U., and S. Buttgenbach. "Next generation of TCAD environments for MEMS design." In 2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (MEMS/MOEMS). IEEE, 2008. http://dx.doi.org/10.1109/dtip.2008.4752959.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Kalaivani, R., J. Charles Pravin, S. Ashok Kumar, and R. Sridevi. "Design and Simulation of 22nm FinFET Structure Using TCAD." In 2020 5th International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2020. http://dx.doi.org/10.1109/icdcs48716.2020.243600.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Li, Cheng, Zijin Pan, Mengfu Di, Feilong Zhang, Zhiguo Li, Ning Jiang, and Albert Wang. "ESD Device Layout Design Guidelines by 3D TCAD Simulation." In 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2020. http://dx.doi.org/10.1109/edtm47692.2020.9117912.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Liu, Kaiping, Jeff Z. Wu, Jihong Chen, Amitabh Jain, and Manoj Mehrotra. "Improving device performance and process manufacturability through the use of TCAD." In Design, Process Integration, and Characterization for Microelectronics, edited by Alexander Starikov and Kenneth W. Tobin, Jr. SPIE, 2002. http://dx.doi.org/10.1117/12.475676.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Asenov, Asen, Karim El Sayed, Ricardo Borges, Plamen Asenov, Campbell Millar, and Terry Ma. "TCAD based Design-Technology Co-Optimisations in advanced technology nodes." In 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2017. http://dx.doi.org/10.1109/vlsi-dat.2017.7939691.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Sanudin, Rahmat, Muhammad Suhaimi Sulong, Marlia Morsin, and Mohd Helmy Abd Wahab. "Simulation study on NMOS gate length variation using TCAD tool." In 2009 1st Asia Symposium on Quality Electronic Design (ASQED 2009). IEEE, 2009. http://dx.doi.org/10.1109/asqed.2009.5206255.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Hong, Teoh Chin, and Razali Ismail. "Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools." In 2006 IEEE International Conference on Semiconductor Electronics. IEEE, 2006. http://dx.doi.org/10.1109/smelec.2006.380770.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Lim, W. H., A. L. Ziebell, I. Cornelius, M. I. Reinhard, D. A. Prokopovich, A. S. Dzurak, and A. B. Rosenfeld. "Cylindrical silicon-on-insulator microdosimeter: Design, fabrication and TCAD modeling." In 2007 IEEE Nuclear Science Symposium Conference Record. IEEE, 2007. http://dx.doi.org/10.1109/nssmic.2007.4437312.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "TCAD Design"

1

Klein, J. E. Conceptual Design for Consolidation TCAP. Office of Scientific and Technical Information (OSTI), February 1999. http://dx.doi.org/10.2172/4820.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Koomar, Saalim, Winston Massam, Kristeen Chachage, Gervace Anthony, WinifridaJacob Mrope, Mustafa Malibiche, Emmanuel Mutura, et al. TCPD in Tanzania: Design-Based Implementation Research Cycle 1 Recommendations Policy Brief. EdTech Hub, May 2023. http://dx.doi.org/10.53832/edtechhub.0166.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

SHOWALTER, STEVEN K., DOLORES CRUZ, FRED GELBARD, RONALD P. MANGINELL, DOUGLAS R. ADKINS, RICHARD KOTTENSTETTE, KIM S. RAWLINSON, GEORGE R. DULLECK, JR, DANIEL S. HORSCHEL, and WAYNE EINFELD. Design and Testing of a Micro Thermal Conductivity Detector (TCD) System. Office of Scientific and Technical Information (OSTI), March 2003. http://dx.doi.org/10.2172/809627.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'TCAD Design' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography