Journal articles on the topic 'Systems on chip (SoCs)'
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Piguet, Christian. "Power consumption reduction in systems on Chip (SoCs)." Annales Des Télécommunications 59, no. 7-8 (July 2004): 884–902. http://dx.doi.org/10.1007/bf03180026.
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Hansson, Andreas, Kees Goossens, and Andrei Rădulescu. "Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip." VLSI Design 2007 (April 30, 2007): 1–10. http://dx.doi.org/10.1155/2007/95859.
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Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions introduce message dependencies that affect deadlock properties of the SoC as a whole. Even when NoC and IP dependency graphs are cycle-free in isolation, put together they may still create cycles. Traditionally, SoCs rely solely on request-response protocols. However, emerging SoCs adopt higher-level protocols for cache coherency, slave locking, and peer-to-peer streaming, thereby increasing the complexity in the interaction between the NoC and the IPs. In this paper, we analyze message-dependent deadlock, arising due to protocol interactions between the NoC and the IP modules. We compare the possible solutions and show that deadlock avoidance, in the presence of higher-level protocols, poses a serious challenge for many current NoC architectures. We evaluate the solutions qualitatively, and for a number of designs we quantify the area cost for the two most economical solutions, strict ordering and end-to-end flow control. We show that the latter, which avoids deadlock for all protocols, adds an area and power cost of 4% and 6%, respectively, of a typical Æthereal NoC instance.
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Boutekkouk, Fateh, Mohammed Benmohammed, Sebastien Bilavarn, and Michel Auguin. "UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)." Journal of Object Technology 8, no. 1 (2009): 135. http://dx.doi.org/10.5381/jot.2009.8.1.a1.
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Maity, Srijeeta, Anirban Ghose, Soumyajit Dey, and Swarnendu Biswas. "Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–28. http://dx.doi.org/10.1145/3477028.
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Recent trends in real-time applications have raised the demand for high-throughput embedded platforms with integrated CPU-GPU based Systems-On-Chip (SoCs). The enhanced performance of such SoCs, however, comes at the cost of increased power consumption, resulting in significant heat dissipation and high on-chip temperatures. The prolonged occurrences of high on-chip temperature can cause accelerated in-circuit ageing, which severely degrades the long-term performance and reliability of the chip. Violation of thermal constraints leads to on-board dynamic thermal management kicking-in, which may result in timing unpredictability for real-time tasks due to transient performance degradation. Recent work in adaptive software design have explored this issue from a control theoretic stand-point, striving for smooth thermal envelopes by tuning the core frequency. Existing techniques do not handle thermal violations for periodic real-time task sets in the presence of dynamic events like change of task periodicity, more so in the context of heterogeneous SoCs with integrated CPU-GPUs. This work presents an OpenCL runtime extension for thermal-aware scheduling of periodic, real-time tasks on heterogeneous multi-core platforms. Our framework mitigates dynamic thermal violations by adaptively tuning task mapping parameters, with the eventual control objective of satisfying both platform-level thermal constraints and task-level deadline constraints. We consider multiple platform-level control actions like task migration, frequency tuning and idle slot insertion as the task mapping parameters. To the best of our knowledge, this is the first work that considers such a variety of task mapping control actions in the context of heterogeneous embedded platforms. We evaluate the proposed framework on an Odroid-XU4 board using OpenCL benchmarks and demonstrate its effectiveness in reducing thermal violations.
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Bogdan, Paul, Tudor Dumitraş, and Radu Marculescu. "Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip." VLSI Design 2007 (April 22, 2007): 1–17. http://dx.doi.org/10.1155/2007/95348.
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As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for Systems-on-Chip (SoCs) are rapidly increasing. Relaxing the requirement of 100% correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires SoCs to be designed with some degree of system-level fault-tolerance. Towards this end, this paper introduces a novel communication paradigm for SoCs, called stochastic communication. This scheme separates communication from computation by allowing the on-chip interconnect to be designed as a reusable IP and also provides a built-in tolerance to DSM failures, without a significant performance penalty. By using this communication scheme, a large percentage of data upsets, packet losses due to buffers overflow, and severe levels of synchronization failures can be tolerated, while providing high levels of performance.
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Si, Qilin, Santosh Shetty, and Benjamin Carrion Schaefer. "Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs." Electronics 10, no. 14 (July 20, 2021): 1746. http://dx.doi.org/10.3390/electronics10141746.
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High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and Digital Signal Processing (DSP) image processing accelerators. Unfortunately, HLS is a single process (component) synthesis method. Thus, the integration of these accelerators has to be performed at the RT level (Verilog or VHDL). This implies that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS. To address this, this work presents a methodology to generate entire heterogeneous SoCs in C. This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of synthesizable bus interfaces that allow any component in the system to send or receive data through the bus. Moreover, this work investigates the generation of processors and interfaces (peripherals) at the behavioral level as these are important parts of any SoCs, but have long been thought not to be efficiently synthesizable using HLS. Generating complete SoCs in C has significant advantages over traditional approaches. First, it enables the generation of fast cycle-accurate simulation models of the entire SoC, making the verification faster and easier. Second, it allows completely isolating the bus implementation details from the developers’ view, allowing the change between bus protocols with only minor changes in the designers’ code. Thirdly, it allows generating different SoC variants quickly by only changing the HLS synthesis options. Experimental results highlight these benefits.
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Touati, Djallel Eddine, Aziz Oukaira, Ahmad Hassan, Mohamed Ali, Ahmed Lakhssassi, and Yvon Savaria. "Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors." Electronics 12, no. 13 (July 6, 2023): 2978. http://dx.doi.org/10.3390/electronics12132978.
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The reliability and lifetime of systems-on-chip (SoCs) are being seriously threatened by thermal issues. In modern SoCs, dynamic thermal management (DTM) uses the thermal data captured by thermal sensors to constantly track the hot spots and thermal peak locations in real time. Estimating peak temperatures and the location of these peaks can play a crucial role for DTM systems, as temperature underestimation can cause SoCs to fail and have shortened lifetime. In this paper, a novel sensor allocation algorithm (called thermal gradient tracker, TGT), based on the recursive elimination of regions that likely do not contain any thermal peaks, is proposed for determining regions that potentially contain thermal peaks. Then, based on an empirical source temperature detection technique called GDS (gradient direction sensor), a hybrid algorithm for detecting the position and temperature of thermal peaks is also proposed to increase the accuracy of temperature sensing while trying to keep the number of thermal sensors to a minimum. The essential parameters, H and R, of the GDS technique are determined using an automated search algorithm based on simulated annealing. The proposed algorithm has been applied in a system-on-chip (SoC) in which four heat sources are present, and for temperatures ranging between 45 °C and 115 °C, in a chip area equal to 25 mm2. The simulation results show that our proposed sensor allocation scheme can detect on-chip peaks with a maximum error of 1.48 °C and an average maximum error of 0.49 °C by using 15 thermal sensors.
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Tong, Huyan. "An Overview on On-chip Network Routing Optimisation." Applied and Computational Engineering 8, no. 1 (August 1, 2023): 191–95. http://dx.doi.org/10.54254/2755-2721/8/20230123.
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As the number of cores in multi-core systems increases, bus-based systems face significant challenges in terms of scalability, average transmission latency and power consumption. In this context, on-chip networks emerged as a suitable communication architecture for System On Chip (SoC) based entirely on the communication ideas in computer networks and taking into account the characteristics of the system on chip in SoCs. With the introduction of on-chip networks, related research has been developed, such as on-chip network topology, communication quality of service, on-chip network routing algorithms, and on-chip network fault tolerance. He then introduces on-chip network routing algorithms and fault-tolerant routing algorithms from different perspectives, and finally points out the directions of fault-tolerant routing algorithms worthy of research.
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Lu, Jian, Hongwei Jia, Andres Arias, Xun Gong, and Z. John Shen. "On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip." International Journal of Power Management Electronics 2008 (July 16, 2008): 1–9. http://dx.doi.org/10.1155/2008/678415.
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A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC). We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.
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Nandi, Purab, K. R. Anupama, Himanish Agarwal, Arav Jain, and Siddharth Paliwal. "Use of the k-nearest neighbour and its analysis for fall detection on Systems on a Chip for multiple datasets." Acta IMEKO 12, no. 3 (September 18, 2023): 1–11. http://dx.doi.org/10.21014/actaimeko.v12i3.1489.
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Fall of an elderly person often leads to serious injuries and death. Many falls occur in the home environment, and hence a reliable fall detection system that can raise alarms with minimum latency is a necessity. Wrist-worn accelerometer-based fall detection systems and multiple datasets are available, but no attempt has been made to analyze the accuracy and precision. Wherever the comparison does exist, it has been run on a cloud. No analysis of the models, convergence, and dataset analysis on Systems on a Chip (SoCs) has ever been attempted. In this paper, we attempt to present why Machine Learning (ML) algorithms in their current state cannot be run on existing SoCs. We have used Snapdragon 410c SoC to do our analytics. In this paper, we have used the kth-nearest neighbour to prove that ML cannot be directly run on SoCs. We have looked at the effect of distance metrics and neighbors as well as the effect of feature extraction on the accuracies and the latencies. In this paper, we establish the need for model compression and data pruning for fall detection using ML/Deep Learning algorithms on SoCs. We have done this by analyzing various datasets on varying architectural parameters.
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Gonzalez-Martinez, Guillermo, Remberto Sandoval-Arechiga, Luis Octavio Solis-Sanchez, Laura Garcia-Luciano, Salvador Ibarra-Delgado, Juan Ramon Solis-Escobedo, Jose Ricardo Gomez-Rodriguez, and Viktor Ivan Rodriguez-Abdala. "A Survey of MPSoC Management toward Self-Awareness." Micromachines 15, no. 5 (April 26, 2024): 577. http://dx.doi.org/10.3390/mi15050577.
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Managing Multi-Processor Systems-on-Chip (MPSoCs) is becoming increasingly complex as demands for advanced capabilities rise. This complexity is due to the involvement of more processing elements and resources, leading to a higher degree of heterogeneity throughout the system. Over time, management schemes have evolved from simple to autonomous systems with continuous control and monitoring of various parameters such as power distribution, thermal events, fault tolerance, and system security. Autonomous management integrates self-awareness into the system, making it aware of its environment, behavior, and objectives. Self-Aware Cyber-Physical Systems-on-Chip (SA-CPSoCs) have emerged as a concept to achieve highly autonomous management. Communication infrastructure is also vital to SoCs, and Software-Defined Networks-on-Chip (SDNoCs) can serve as a base structure for self-aware systems-on-chip. This paper presents a survey of the evolution of MPSoC management over the last two decades, categorizing research works according to their objectives and improvements. It also discusses the characteristics and properties of SA-CPSoCs and explains why SDNoCs are crucial for these systems.
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Wegner, Tim, Martin Gag, and Dirk Timmermann. "Performance Analysis of Temperature Management Approaches in Networks-on-Chip." International Journal of Embedded and Real-Time Communication Systems 3, no. 4 (October 2012): 19–41. http://dx.doi.org/10.4018/jertcs.2012100102.
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With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.
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R, Anala M., Amit N. Subrahmanya, and Allbright D’Souza. "Performance Analysis of Mesh-based NoC’s on Routing Algorithms." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (October 1, 2018): 3368. http://dx.doi.org/10.11591/ijece.v8i5.pp3368-3373.
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The advent of System-on-Chip (SoCs), has brought about a need to increase the scale of multi-core chip networks. Bus Based communications have proved to be limited in terms of performance and ease of scalability, the solution to both bus – based and Point-to-Point (P2P) communication systems is to use a communication infrastructure called Network-on-Chip (NoC). Performance of NoC depends on various factors such as network topology, routing strategy and switching technique and traffic patterns. In this paper, we have taken the initiative to compile together a comparative analysis of different Network on Chip infrastructures based on the classification of routing algorithm, switching technique, and traffic patterns. The goal is to show how varied combinations of the three factors perform differently based on the size of the mesh network, using NOXIM, an open source SystemC Simulator of mesh-based NoC. The analysis has shown tenable evidence highlighting the novelty of XY routing algorithm.
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Gomez-Rodriguez, Jose Ricardo, Remberto Sandoval-Arechiga, Salvador Ibarra-Delgado, Viktor Ivan Rodriguez-Abdala, Jose Luis Vazquez-Avila, and Ramon Parra-Michel. "A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities." Micromachines 12, no. 2 (February 12, 2021): 183. http://dx.doi.org/10.3390/mi12020183.
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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.
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Zhang, Wei, Zihao Jiang, Zhiguang Chen, Nong Xiao, and Yang Ou. "NUMA-Aware DGEMM Based on 64-Bit ARMv8 Multicore Processors Architecture." Electronics 10, no. 16 (August 17, 2021): 1984. http://dx.doi.org/10.3390/electronics10161984.
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Double-precision general matrix multiplication (DGEMM) is an essential kernel for measuring the potential performance of an HPC platform. ARMv8-based system-on-chips (SoCs) have become the candidates for the next-generation HPC systems with their highly competitive performance and energy efficiency. Therefore, it is meaningful to design high-performance DGEMM for ARMv8-based SoCs. However, as ARMv8-based SoCs integrate increasing cores, modern CPU uses non-uniform memory access (NUMA). NUMA restricts the performance and scalability of DGEMM when many threads access remote NUMA domains. This poses a challenge to develop high-performance DGEMM on multi-NUMA architecture. We present a NUMA-aware method to reduce the number of cross-die and cross-chip memory access events. The critical enabler for NUMA-aware DGEMM is to leverage two levels of parallelism between and within nodes in a purely threaded implementation, which allows the task independence and data localization of NUMA nodes. We have implemented NUMA-aware DGEMM in the OpenBLAS and evaluated it on a dual-socket server with 48-core processors based on the Kunpeng920 architecture. The results show that NUMA-aware DGEMM has effectively reduced the number of cross-die and cross-chip memory access, resulting in enhancing the scalability of DGEMM significantly and increasing the performance of DGEMM by 17.1% on average, with the most remarkable improvement being 21.9%.
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Amoretti, Michele. "Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/982569.
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Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evaluation methodologies rely heavily on analytical modeling and simulation. Unfortunately, there is no standard modeling framework. In this paper we illustrate how to design and evaluate NoCs by integrating the Discrete Event System Specification (DEVS) modeling framework and the simulation environment called DEUS. The advantage of such an approach is that both DEVS and DEUS support modularity—the former being a sound and complete modeling framework and the latter being an open, general-purpose platform, characterized by a steep learning curve and the possibility to simulate any system at any level of detail.
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ELRABAA, MUHAMMAD E. S., and ABDELHAFID BOUHRAOUA. "BUFFER ENGINEERING FOR MODIFIED FAT TREE NoCs FOR MANY-CORE SYSTEMS-ON-CHIP." Journal of Circuits, Systems and Computers 23, no. 07 (June 2, 2014): 1450105. http://dx.doi.org/10.1142/s0218126614501059.
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As networks-on-chips (NoCs) are expected to provide the necessary scalable communication medium for future many-core systems-on-chips (SoCs) optimizing their resources is of great importance. What is really needed is an efficient NoC architecture with optimized resources that requires very little customization by the SoC developers. One of the most important area and power hungry resources is the NoC's buffers. In this work, a new Modified Fat Tree (MFT) NoC architecture with buffers engineered for maximum efficiency (performance versus area) is presented. Extensive simulations are used to show optimum buffer design/placement under different conditions of traffic types and NoC sizes.
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Zhou, Xinbing, Peng Hao, and Dake Liu. "PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs." Micromachines 14, no. 3 (February 21, 2023): 501. http://dx.doi.org/10.3390/mi14030501.
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Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.
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Nesrine, Toubaline, Bennouar Djamel, and Mahdoum Ali. "A Classification and Evaluation Framework for NoC Mapping Strategies." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1730001. http://dx.doi.org/10.1142/s021812661730001x.
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Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been proposed but selecting the best technique for a given NoC remains a challenging problem. This paper attempts to provide an answer to this issue. It motivates and presents a definition and a classification according to some criteria: (i) the algorithms used for solving the mapping problem, (ii) the moment in which the mapping is executed, (iii) the impact of combining mapping with other phases during NoC design and (iv) the target architecture.
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SHI, ZAIFENG, TAO LUO, YUANQING LI, YAN XU, and SUYING YAO. "AN ON-CHIP BUS MODELING AND PARAMETER SIMULATION METHOD BASED ON UTILIZATION ANALYSIS." Journal of Circuits, Systems and Computers 22, no. 10 (December 2013): 1340031. http://dx.doi.org/10.1142/s0218126613400318.
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In system level design or architecture design stage of SoCs, it is important to estimate the system parameters such as bus utilization and buffer capacity. A novel bus modeling method which was derived from Markov model for obtaining these parameters of an on-chip-bus system has been proposed in this paper. This modeling approach employs Markov chain to describe the state change of the system. This method was used in architecture design verification of a video format converting (VFC) chip. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method were verified, and more than 55% of FIFOs size are saved. It is suitable for analyzing various bus systems, such as user-defined buses, industrial standard buses, multi-core and multi-bus systems.
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Melo, Douglas R., Cesar A. Zeferino, Luigi Dilillo, and Eduardo A. Bezerra. "Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design." Sensors 19, no. 24 (December 9, 2019): 5416. http://dx.doi.org/10.3390/s19245416.
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Reducing component size and increasing the operating frequency of integrated circuits makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and errors can be propagated and lead to a system failure. SoCs employing many cores rely on a Network-on-Chip (NoC) as the interconnect architecture. In this context, this study explores alternatives to implement the flow regulation, routing, and arbitration controllers of an NoC router aiming at minimizing error propagation. For this purpose, a router with Finite-State Machine (FSM)-based controllers was developed targeting low use of logical resources and design flexibility for implementation in FPGA devices. We elaborated and compared the synthesis and simulation results of architectures that vary their controllers on Moore and Mealy FSMs, as well as the Triple Modular Redundancy (TMR) hardening application. Experimental results showed that the routing controller was the most critical one and that migrating a Moore to a Mealy controller offered a lower error propagation rate and higher performance than the application of TMR. We intended to use the proposed router architecture to integrate cores in a fault-tolerant NoC-based system for data processing in harsh environments, such as in space applications.
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Clair, Judicael, Guy Eichler, and Luca P. Carloni. "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip." ACM Transactions on Embedded Computing Systems 22, no. 5s (September 9, 2023): 1–22. http://dx.doi.org/10.1145/3609101.
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Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed with limited concerns to the problem of integrating it with other components in a heterogeneous System-on-Chip (SoC). Building on a state-of-the-art reconfigurable neuromorphic architecture, we present the design of a neuromorphic hardware accelerator equipped with a programmable interface that simplifies both the integration into an SoC and communication with the processor present on the SoC. To optimize the allocation of on-chip resources, we develop an optimizer to restructure existing neuromorphic models for a given hardware architecture, and perform design-space exploration to find highly efficient implementations. We conduct experiments with various FPGA-based prototypes of many-accelerator SoCs, where Linux-based applications running on a RISC-V processor invoke Pareto-optimal implementations of our accelerator alongside third-party accelerators. These experiments demonstrate that our neuromorphic hardware, which is up to 89× faster and 170× more energy efficient after applying our optimizer, can be used in synergy with other accelerators for different application purposes.
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Parmar, Harikrishna, and Usha Mehta. "ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC." Journal of Low Power Electronics and Applications 9, no. 2 (June 17, 2019): 19. http://dx.doi.org/10.3390/jlpea9020019.
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Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.
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Bhat, Ganapati, Sumit K. Mandal, Sai T. Manchukonda, Sai V. Vadlamudi, Ayushi Agarwal, Jun Wang, and Umit Y. Ogras. "Per-Core Power Modeling for Heterogenous SoCs." Electronics 10, no. 19 (October 7, 2021): 2428. http://dx.doi.org/10.3390/electronics10192428.
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State-of-the-art mobile platforms, such as smartphones and tablets, are powered by heterogeneous system-on-chips (SoCs). These SoCs are composed of many processing elements, including multiple CPU core clusters (e.g., big.LITTLE cores), graphics processing units (GPUs), memory controllers and other on-chip resources. On the one hand, mobile platforms need to provide a swift response time for interactive apps and high throughput for graphics-oriented workloads; on the other hand, the power consumption must be under tight control to prevent high skin temperatures and energy consumption. Therefore, commercial systems feature a range of mechanisms for dynamic power and temperature control. However, these techniques rely on simple indicators, such as core utilization and total power consumption. System architects are typically limited to the total power consumption, since multiple resources share the same power rail. More importantly, most of the power rails are not exposed to the input/output pins. To address this challenge, this paper presents a thorough methodology to model the power consumption of major resources in heterogeneous SoCs. The proposed models utilize a wide range of performance counters to capture the workload dynamics accurately. Experimental validation on a Nexus 6P phone, powered by an octa-core Snapdragon 810 SoC, showed that the proposed models can estimate the power consumption within a 10% error margin.
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A., Rahul, and Shripriyadarshini J. "Environmental Impact Assessment of Chiplet-Based VLSI." International Research Journal of Computer Science 11, no. 04 (April 5, 2024): 364–70. http://dx.doi.org/10.26562/irjcs.2024.v1104.44.
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In this paper, we explore the revolutionary shift in VLSI design brought about by chiplet-based architectures, which are superior to the older, single-piece designs in many ways. This type of architecture not only boosts performance and allows for greater system expansion but also plays a significant role in promoting environmental sustainability. Chiplet-based designs lead to more resource-efficient, less wasteful, and more energy-efficient semiconductor technologies, steering the industry towards a more environmentally friendly path. The adoption of eco-chips enhances these environmental benefits, leading to a notable decrease in the carbon emissions associated with electronic devices and systems. This shift is pivotal in achieving the twin goals of advancing technology and upholding environmental stewardship in VLSI. We introduce HI as a strategy for achieving sustainable computing, creating chiplet-based systems that have a smaller carbon footprint than traditional System on Chips (SoCs). We also present ECO-CHIP, a tool we developed for estimating the carbon footprint of these systems, accounting for both their construction and operational phases, including the carbon costs of advanced packaging. In Section VI, we illustrate how ECO-CHIP can be used for breaking down systems into smaller parts and for exploring different design options, and we have integrated it with other tools for estimating the costs of chiplet-based designs. ECO-CHIP is freely available as open-source software and can be found in an anonymous repository [21]. We contend that ECO-CHIP will facilitate the creation of more environmentally friendly design practices for the next generation of complex systems.
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Ruaro, Marcelo, Anderson Sant’ana, Axel Jantsch, and Fernando Gehm Moraes. "Modular and Distributed Management of Many-Core SoCs." ACM Transactions on Computer Systems 38, no. 1-2 (July 2021): 1–16. http://dx.doi.org/10.1145/3458511.
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Many-Core Systems-on-Chip increasingly require Dynamic Multi-objective Management (DMOM) of resources. DMOM uses different management components for objectives and resources to implement comprehensive and self-adaptive system resource management. DMOMs are challenging because they require a scalable and well-organized framework to make each component modular, allowing it to be instantiated or redesigned with a limited impact on other components. This work evaluates two state-of-the-art distributed management paradigms and, motivated by their drawbacks, proposes a new one called Management Application (MA) , along with a DMOM framework based on MA. MA is a distributed application, specific for management, where each task implements a management role. This paradigm favors scalability and modularity because the management design assumes different and parallel modules, decoupled from the OS. An experiment with a task mapping case study shows that MA reduces the overhead of management resources (-61.5%), latency (-66%), and communication volume (-96%) compared to state-of-the-art per-application management. Compared to cluster-based management (CBM) implemented directly as part of the OS, MA is similar in resources and communication volume, increasing only the mapping latency (+16%). Results targeting a complete DMOM control loop addressing up to three different objectives show the scalability regarding system size and adaptation frequency compared to CBM, presenting an overall management latency reduction of 17.2% and an overall monitoring messages’ latency reduction of 90.2%.
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Kordzadeh, Atefeh, Dominik Holzmann, Alfred Binder, Thomas Moldaschl, Johannes Sturm, and Ali Roshanghias. "Miniaturized On-Chip NFC Antenna versus Screen-Printed Antenna for the Flexible Disposable Sensor Strips." IoT 1, no. 2 (October 28, 2020): 309–19. http://dx.doi.org/10.3390/iot1020018.
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With the ongoing trend toward miniaturization via system-on-chip (SoC), both radio-frequency (RF) SoCs and on-chip multi-sensory systems are gaining significance. This paper compares the inductance of a miniaturized on-chip near field communication (NFC) antenna versus the conventional screen-printed on-substrate ones that have been used for the transfer of sensory data from a chip to a cell phone reader. Furthermore, the transferred power efficiency in a coupled NFC system is calculated for various chip coil geometries and the results are compared. The proposed NFC antenna was fabricated via a lithography process for an application-specific integrated circuit (ASIC) chip. The chip had a small area of 2.4 × 2.4 mm2, therefore a miniaturized NFC antenna was designed, whereas the screen-printed on-substrate antennas had an area of 35 × 51 mm2. This paper investigates the effects of different parameters such as conductor thickness and materials, double layering, and employing ferrite layers with different thicknesses on the performance of the on-chip antennas using full-wave simulations. The presence of a ferrite layer to increase the inductance of the antenna and mitigate the interactions with backplates has proven useful. The best performance was obtained via double-layering of the coils, which was similar to on-substrate antennas, while a size reduction of 99.68% was gained. Consequently, the coupling factors and maximum achievable power transmission efficiency of the on-chip antenna and on-substrate antenna were studied and compared.
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Zhang, Zhun, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu, and Jinhui Ma. "High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems." Micromachines 12, no. 5 (May 15, 2021): 560. http://dx.doi.org/10.3390/mi12050560.
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Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.
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Malik, Arsalan Ali, Anees Ullah, Ali Zahir, Affaq Qamar, Shadan Khan Khattak, and Pedro Reviriego. "Isolation Design Flow Effectiveness Evaluation Methodology for Zynq SoCs." Electronics 9, no. 5 (May 15, 2020): 814. http://dx.doi.org/10.3390/electronics9050814.
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Static Random-Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) are increasingly being used in many application domains due to their higher logic density and reconfiguration capabilities. However, with state-of-the-art FPGAs being manufactured in the latest technology nodes, reliability is becoming an important issue, particularly for safety-critical avionics, automotive, aerospace, industrial robotics, medical, and financial systems. Therefore, fault tolerant system design methodologies have become essential in the aforementioned application domains. The Isolation Design Flow (IDF) is one such design methodology that has promising prospects due to its ability to isolate logic design modules at the physical level for fault containment purposes. This paper proposes a methodology to evaluate the effectiveness of the IDF. To do so, reverse engineering is used to enable fault injection on the IDF designs with minimal changes in the bit-stream. This reduces the time needed to inject a fault significantly thus accelerating the evaluation process. Then this methodology is applied to a case study of a single-chip cryptography application on a ZynQ SoC. Specifically, an Advanced Encryption Standard (AES) Duplication With Comparison (DWC) design is physically isolated with IDF and subsequently subjected to frame-level Fault Injection (FI) in the configuration memory.
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Ayachi, Riadh, Ayoub Mhaouch, and Abdessalem Ben Abdelali. "Lightweight Cryptography for Network-on-Chip Data Encryption." Security and Communication Networks 2021 (May 19, 2021): 1–10. http://dx.doi.org/10.1155/2021/9943713.
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System-on-chip (SoC) is the main processor for most recent applications such as the Internet of things (IoT). SoCs are composed of multiple blocks that communicate with each other through an integrated router. Data routing from a block to another poses many challenges. The network-on-chip (NoC) was used for the transmission of data from a source to a destination with high reliability, high speed, low power consumption, and low hardware occupation. An NoC is composed of a router, network links (NL), and network interface (NI). The main component of the NoC, the NI, is composed of an input/output FIFO, a finite state machine (FSM), pack, and depack modules. Data transmission from a block to another poses a security problem such as secret information extraction. In this paper, we proposed a data encryption framework for NoC based on a light encryption device (LED) algorithm. The main advantages of the proposed algorithm are to reduce the implementation area and to achieve high speed while reducing the power consumption. The proposed encryption framework was simulated Verilog/VHDL on the Xilinx ISE and implemented on the Xilinx Virtex 5 XC5VFX200T. The obtained results have shown that the proposed framework has a smaller area and higher speed compared to existing works. The proposed algorithm has reduced the NI implementation area and enhanced the network performance in terms of speed and security.
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BHAGAVAT, MILIND. "Packaging Renaissance with Chiplets." International Symposium on Microelectronics 2019, S1 (October 1, 2019): S1—S17. http://dx.doi.org/10.4071/2380-4505-2019.1.keynote000001.
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Abstract With ever shrinking advanced CMOS nodes and evolution of systems with increasing complexity, the traditional SoC paradigm is facing extensive challenges in terms of yields and heterogeneity. The emerging industry solution to this has been to partition the SoCs into smaller units, with each unit performing a certain (though exclusive) function. This drove the birth of “chiplets”. With advent of chiplets, the traditional function of packaging as an after-thought to chip development has got a revolutionary face-lift. Packaging is now enabling interconnects to replace on-chip global interconnects. The onus now is on packaging to get the chiplets to integrate and communicate with each other such that the net performance is equivalent to or better than SoC. This has spawned a renaissance in field of semiconductor packaging, with newer multi-die packaging technologies being productized to realize newer and better interconnects. Some examples of these emerging technologies include advanced flip-chip, 2.5D, 2.1D, 3D, Wafer Level Fan-Out, and Bridge Technologies. AMD is at forefront of chiplet technologies, with extensive 7nm chiplet based product portfolio catering to the HPC market. This talk will discuss the current state of chiplet packaging technologies.
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Cirstea, Marcian, Khaled Benkrid, Andrei Dinu, Romeo Ghiriti, and Dorin Petreus. "Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends." Micromachines 15, no. 2 (February 7, 2024): 247. http://dx.doi.org/10.3390/mi15020247.
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This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.
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Shahane, Priti, and Rakhi Kurup. "Design of fault tolerant algorithm for network on chip router using field programmable gate array." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 1 (March 1, 2024): 1. http://dx.doi.org/10.11591/ijres.v13.i1.pp1-8.
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<p class="Abstract">Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).</p>
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Dondo Gazzano, Julio, Fernando Rincon, Carlos Vaderrama, Felix Villanueva, Julian Caba, and Juan Carlos Lopez. "Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques." Scientific World Journal 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/164059.
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In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.
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Neuenhahn, M. C., H. Blume, and T. G. Noll. "Quantitative design space exploration of routing-switches for Network-on-Chip." Advances in Radio Science 6 (May 26, 2008): 145–50. http://dx.doi.org/10.5194/ars-6-145-2008.
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Abstract. Future Systems-on-Chip (SoC) will consist of many embedded functional units like e.g. embedded processor cores, memories or FPGA like structures. These SoCs will have huge communication demands, which can not be fulfilled by bus-based communication systems. Possible solutions to this problem are so called Networks-on-Chip (NoC). These NoCs basically consist of network-interfaces which integrate functional units into the NoC and routing-switches which connect the network-interfaces. Here, VLSI-based routing-switch implementations are presented. The characteristics of these NoCs like performance and costs (e.g. silicon area respectively logic elements, power dissipation) depend on a variety of parameters. As a routing-switch is a key component of a NoC, the costs and performance of routing-switches are compared for different parameter combinations. Evaluated parameters are for example data word length, architecture of the routing-switch (parallel vs. centralized implementation) and routing-algorithm. The performance and costs of routing-switches were evaluated using an FPGA-based NoC-emulator. In addition different routing-switches were implemented using a 90 nm standard-cell library to determine the maximum clock frequency, power-dissipation and area of a VLSI-implementation. The power consumption was determined by simulating the extracted layout of the routing-switches. Finally, these results are benchmarked to other routing-switch implementations like Aetheral and xpipes.
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Ramos, Alberto, Honorio Martín, Carmen Cámara, and Pedro Peris-Lopez. "Stimulated Microcontroller Dataset for New IoT Device Identification Schemes through On-Chip Sensor Monitoring." Data 9, no. 5 (April 28, 2024): 62. http://dx.doi.org/10.3390/data9050062.
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Legitimate identification of devices is crucial to ensure the security of present and future IoT ecosystems. In this regard, AI-based systems that exploit intrinsic hardware variations have gained notable relevance. Within this context, on-chip sensors included for monitoring purposes in a wide range of SoCs remain almost unexplored, despite their potential as a valuable source of both information and variability. In this work, we introduce and release a dataset comprising data collected from the on-chip temperature and voltage sensors of 20 microcontroller-based boards from the STM32L family. These boards were stimulated with five different algorithms, as workloads to elicit diverse responses. The dataset consists of five acquisitions (1.3 billion readouts) that are spaced over time and were obtained under different configurations using an automated platform. The raw dataset is publicly available, along with metadata and scripts developed to generate pre-processed T–V sequence sets. Finally, a proof of concept consisting of training a simple model is presented to demonstrate the feasibility of the identification system based on these data.
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Pitre, Boisy, and Martin Margala. "A Novel Approach to Managing System-on-Chip Sub-Blocks Using a 16-Bit Real-Time Operating System." Electronics 13, no. 10 (May 18, 2024): 1978. http://dx.doi.org/10.3390/electronics13101978.
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Embedded computers are ubiquitous in products across various industries, including the automotive and medical industries, and in consumer goods such as appliances and entertainment devices. These specialized computing systems utilize Systems on Chips (SoCs), devices that are made up of one or more main microprocessor cores. SoCs are augmented with sub-blocks that perform dedicated tasks to support the system. Sub-blocks contain custom logic or small-footprint microprocessors, depending upon their complexity, and perform support functions such as clock generation, device testing, phase-locked loop synchronization and peripheral management for interfaces such as a Universal Serial Bus (USB) or Serial Peripheral Interface (SPI). SoC designers have traditionally obtained sub-blocks from commercial vendors. While these sub-blocks have well-defined interfaces, their internal implementations are opaque. Without visibility of the specifics of the implementation, SoC designers are limited to the degree to which they can optimize these off-the-shelf sub-blocks. The result is that power and area constraints are dictated by the design of a third-party vendor. This work introduces a novel idea: using an open-source, small, multitasking, real-time operating system inside an SoC sub-block to manage multiple processes, thereby conserving code space. This OS is TurbOS, a new operating system whose primary goal is to provide the highest performance using the least amount of space. It is written in the assembly language of a new pipelined 16-bit microprocessor developed at the University of Florida, the Turbo9. TurbOS is derived from and incorporates the design benefits of an existing operating system called NitrOS-9, and reduces the code size from its progenitor by nearly 20%. Furthermore, it is over 80% smaller than the popular FreeRTOS operating system. TurbOS delivers a rich feature set for managing memory and process resources that are useful in SoC sub-block applications in an extremely small footprint of only 3 kilobytes.
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Cesini, Daniele, Elena Corni, Antonio Falabella, Andrea Ferraro, Lucia Morganti, Enrico Calore, Sebastiano Fabio Schifano, et al. "Power-Efficient Computing: Experiences from the COSA Project." Scientific Programming 2017 (2017): 1–14. http://dx.doi.org/10.1155/2017/7206595.
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Energy consumption is today one of the most relevant issues in operating HPC systems for scientific applications. The use of unconventional computing systems is therefore of great interest for several scientific communities looking for a better tradeoff between time-to-solution and energy-to-solution. In this context, the performance assessment of processors with a high ratio of performance per watt is necessary to understand how to realize energy-efficient computing systems for scientific applications, using this class of processors. Computing On SOC Architecture (COSA) is a three-year project (2015–2017) funded by the Scientific Commission V of the Italian Institute for Nuclear Physics (INFN), which aims to investigate the performance and the total cost of ownership offered by computing systems based on commodity low-power Systems on Chip (SoCs) and high energy-efficient systems based on GP-GPUs. In this work, we present the results of the project analyzing the performance of several scientific applications on several GPU- and SoC-based systems. We also describe the methodology we have used to measure energy performance and the tools we have implemented to monitor the power drained by applications while running.
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Prasad Acharya, Gobinda, Muddapu Asha Rani, Ganjikunta Ganesh Kumar, and Lavanya Poluboyina. "Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (April 1, 2022): 96. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp96-104.
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<span lang="EN-US">The technology shrinkage and the increased demand for high storage memory devices in today’s system on-chips (SoCs) has been the challenges to the designers not only in the design cycle but also to the test engineers in testing these memory devices against the permanent faults, intermittent and soft errors. Around 90% of the chip area in today’s SoCs is being occupied by the embedded memories, and the cost for testing these memory devices contributes a major factor in the overall cost and the time to market. This paper</span><span lang="EN-US">proposes a strategy to develop a word-oriented March SS algorithm-basedmemory built-in self-test (MBIST), which is then applied for memory built-in self-test and repair (MBISTR) strategy. The implementation details for 1 KB of single-port static random-access memory (SRAM) depict that the modified March-SS algorithm based MBISTR-enabled SRAM facilitates self-test and self-repair of embedded memories with a marginal hardware overhead (<1%) in terms of look up tables and slice registers when compared to that of standard SRAM.</span>
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Li, Peng, Wei Xi, Xianggen Yin, Hao Yao, and Huafeng Chen. "Design of a CMOS Lineal Hall Sensor Front-End Working in Current Mode with Programmable Gain Stage for Power Specific Chip." Journal of Sensors 2021 (February 1, 2021): 1–5. http://dx.doi.org/10.1155/2021/6618206.
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With the continuous intelligentization of power systems, the demand for the integration of digital chips and sensor chips such as the Internet of Things is also increasing. A CMOS lineal magnetic Hall sensor front-end working in current mode with programmable gain stage is designed and implemented with SMIC 55 nm standard CMOS technology. By using a spinning-current technique, chopper technique, and digital calibration technique to eliminate the offset voltage and nonlinearity, this magnetic Hall sensor can be easily integrated into digital systems like SoCs. This work has already finished the circuit simulation and layout design, and all simulation indicators basically reach the expected value. The maximum gain of proposed sensor systems can be up to 33.9 dB. The total power is less than 4 mW. And the total area is less than 0.113 μm2. The magnetic Hall sensor can be easily integrated into chips such as the power Internet of Things to form a single-chip-level SoC design, which is mainly used in applications such as circuit breakers and electric energy measurement.
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Ohmura, Itta, Gentaro Morimoto, Yousuke Ohno, Aki Hasegawa, and Makoto Taiji. "MDGRAPE-4: a special-purpose computer system for molecular dynamics simulations." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2021 (August 6, 2014): 20130387. http://dx.doi.org/10.1098/rsta.2013.0387.
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We are developing the MDGRAPE-4, a special-purpose computer system for molecular dynamics (MD) simulations. MDGRAPE-4 is designed to achieve strong scalability for protein MD simulations through the integration of general-purpose cores, dedicated pipelines, memory banks and network interfaces (NIFs) to create a system on chip (SoC). Each SoC has 64 dedicated pipelines that are used for non-bonded force calculations and run at 0.8 GHz. Additionally, it has 65 Tensilica Xtensa LX cores with single-precision floating-point units that are used for other calculations and run at 0.6 GHz. At peak performance levels, each SoC can evaluate 51.2 G interactions per second. It also has 1.8 MB of embedded shared memory banks and six network units with a peak bandwidth of 7.2 GB s −1 for the three-dimensional torus network. The system consists of 512 (8×8×8) SoCs in total, which are mounted on 64 node modules with eight SoCs. The optical transmitters/receivers are used for internode communication. The expected maximum power consumption is 50 kW. While MDGRAPE-4 software has still been improved, we plan to run MD simulations on MDGRAPE-4 in 2014. The MDGRAPE-4 system will enable long-time molecular dynamics simulations of small systems. It is also useful for multiscale molecular simulations where the particle simulation parts often become bottlenecks.
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Alraho, Senan, Qummar Zaman, Hamam Abd, and Andreas König. "Integrated Sensor Electronic Front-Ends with Self-X Capabilities." Chips 1, no. 2 (August 12, 2022): 83–120. http://dx.doi.org/10.3390/chips1020008.
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The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.
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Bernardi, Paolo, Augusto Maria Guerriero, Giorgio Insinga, Giovanni Paganini, Giambattista Carnevale, Matteo Coppetta, Walter Mischo, and Rudolf Ullmann. "Built-In Self-Test Architecture Enabling Diagnosis for Massive Embedded Memory Banks in Large SoCs." Electronics 13, no. 2 (January 10, 2024): 303. http://dx.doi.org/10.3390/electronics13020303.
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This paper describes a hardware/software strategy for the effective and efficient management of several distributed Memory Built-In Self-Test (MBIST) units orchestrated by a single CPU to enable the parallel testing of several memory banks. Experimental testing of the implementation on an Infineon chip shows up to a 25% test time reduction compared to traditional strategies, especially in cases for which there are a large number of failures affecting several banks. Additionally, it permits balanced failure collection from different banks in cases for which there are limitations to the storage of failure-related information.
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Krishna, Banoth, Sandeep Singh Gill, and Amod Kumar. "Design of Low-Power High-Speed 8 Bit CMOS Current Steering DAC for AI Applications." International Journal of Software Science and Computational Intelligence 14, no. 1 (January 1, 2022): 1–18. http://dx.doi.org/10.4018/ijssci.304801.
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This paper describes a current steering 8-bit DAC architecture for low power and high-speed assistance in AI networks. This design is most suitable for 5G and next-generation high-speed communication systems on chip (SoCs). This DAC keeps a constant load current and leads to faster operations in wideband portable device applications. The design is based on weighted current transmission through current mirrors wherein current reduces from MSB to LSB continuously. By choosing a low current for LSB, the power dissipation reduces. Power and area are also reduced by using a 2-bit binary to thermometer decoder. The DAC's integral nonlinearity (INL) and differential nonlinearity (DNL) are found to be within 0.4 and 0.9 LSB, respectively. The DAC's highest operating speed is 1GHz, with a power dissipation of around 24.2 mW with the supply voltage of 1.8v using 180nm CMOS technology.
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Kumar, N. Ashok, G. Shyni, Geno Peter, Albert Alexander Stonier, and Vivekananda Ganji. "Architecture of Network-on-Chip (NoC) for Secure Data Routing Using 4-H Function of Improved TACIT Security Algorithm." Wireless Communications and Mobile Computing 2022 (March 9, 2022): 1–9. http://dx.doi.org/10.1155/2022/4737569.
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In the technical world, NoC (network-on-chip) is a noticeable communication subsystem based on integrated circuits. It is mainly used in improving the performance of system-on-chip (SoC) by bridging the intellectual properties in the SoCs. But there is a need of protected architecture which is dealing with routing and processing data in the multicore system-on-chip (SoC). The recent issue with the above is there is still a drawback in enabling a better network routing system for accessing physical networks. The methodology of NoC mainly depends on the routing scheme, switching techniques, and structuring topologies. In this paper, we propose a new technique in implementing the chip in order to maintain the data privacy of NoC routers. There are many works with different algorithms that were evolved in enabling the secureness of NoCs, but due to the key size and block size, it is still not able to reach the expected effectiveness. Our proposed work is intended in designing a NoC architecture by means of embedding advanced TACIT security algorithm in Virtex-5 FPGA. Here, we used a hash function which is under a 4 hash function (4-H) scheme. The main advantage of this key generation scheme is it is applicable for block size and key size up to ‘ n ’ bit. Thus, this TACIT security algorithm enables ‘ n ’ bit using the software VHDL programming language in Xilinx ISE 14.2 and Modelsim 10.1 b which are applicable for 1024 bit and ‘ N ’ bits of block size on Virtex-5 FPGA systems. This design system can be enhanced by improving the factors like timing parameters, supporting memory, higher frequencies, and utilized summaries.
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Sharma, Dimple, and Lev Kirischian. "A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature Variations." International Journal of Reconfigurable Computing 2021 (September 1, 2021): 1–29. http://dx.doi.org/10.1155/2021/5512938.
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One of the growing areas of application of embedded systems in robotics, aerospace, military, etc. is autonomous mobile systems. Usually, such embedded systems have multitask multimodal workloads. These systems must sustain the required performance of their dynamic workloads in presence of varying power budget due to rechargeable power sources, varying die temperature due to varying workloads and/or external temperature, and varying hardware resources due to occurrence of hardware faults. This paper proposes a run-time decision-making method, called Decision Space Explorer, for FPGA-based Systems-on-Chip (SoCs) to support changing workload requirements while simultaneously mitigating unpredictable variations in power budget, die temperature, and hardware resource constraints. It is based on the concept of Run-Time Structural Adaptation (RTSA); whenever there is a change in a system’s set of constraints, Explorer selects a suitable hardware processing circuit for each active task at an appropriate operating frequency such that all the constraints are satisfied. Explorer has been experimentally deployed on the ARM Cortex-A9 core of Xilinx Zynq XC7Z020 SoC. Its worst-case decision-making time for different scenarios ranges from tens to hundreds of microseconds. Explorer is thus suitable for enabling RTSA in systems where specifications of multiple objectives must be maintained simultaneously, making them self-sustainable.
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Galatenko, V. A., and K. A. Kostyukhin. "Hardware Debugging: an Overview of Modern Approaches." Programmnaya Ingeneria 13, no. 9 (November 7, 2022): 415–24. http://dx.doi.org/10.17587/prin.13.415-424.
Full textAbstract:
The ubiquity of complex devices built on systems on chip (SoC) with multiple processor cores poses new challenges for developers of embedded systems. New development tools specifically designed for complex systems on chip can help solve them, but these tools are usually limited by the functionality of debugging support tools. High-quality debugging support with advanced features is necessary to take full advantage of complex SoC devices while reducing development time. The article discusses various mechanisms and ways to implement support for debugging systems on chip designed for complex real-time systems used, for example, in the Internet of Things (IoT) paradigm. This review includes an assessment of the available solutions and their suitability for use with the next generation of complex systems on chip with multiple processor cores. It is shown that many existing solutions do not allow developers to easily take advantage of complex functions integrated into the next-generation SoC. The basic debugging support functions for multicore SoCs are summarized and discussed. Recommendations are given for SoC developers and for the future direction of research in this area in order to provide a more suitable basis for new development tools. Such tools are extremely necessary for all embedded hard real-time systems and are of high importance for minimizing the complexity of their development. Modern systems and devices implementing the Internet of Things paradigm are increasingly required to have sufficiently high real-time performance while maintaining low power consumption. These requirements lead to the creation of multicore SoC solutions with support for a wide range of peripheral devices and communication protocols. The systems are limited by the requirements for working in harsh conditions, such as, for example, in the engine compartment of a car or on a radar tower. The development of embedded hard real-time systems, in which a task that fails to be completed on time can lead to physical damage of the device, is a complex process. Effective tools, such as interactive debuggers and profilers, are an integral part of solving these problems and are vital for developing reliable embedded systems. Modern technologies now allow the integration of the entire system on a single silicon chip, known as a system on a chip (SoC), which leads to the relocation of existing external interfaces, widely used for development purposes, to the chip. Traditionally, communication within an embedded system is carried out using an external processor system bus, which is implemented in the form of tracks on a printed circuit board. The printed circuit board must support the appropriate interfaces of development tools that require a physical connection, such as, for example, logic analyzers and oscilloscopes. Previously, placing external interfaces on a chip left fewer options for external analysis tools and, in fact, makes developers "blind" to the internal state of the SoC. Without a reliable and consistent representation of the state of the embedded system, the detection of defects or errors in the system may become difficult or even impossible. The main solution to the problem of the lack of external interfaces is to provide access to internal nodes from outside the system through existing interfaces. There are many different approaches to achieving the required visibility, and they are outlined in this review.
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Iyer (Subu), Subramanian S. "Packaging without the Package - A More Holistic Moore's Law." International Symposium on Microelectronics 2017, S1 (October 1, 2017): 1–40. http://dx.doi.org/10.4071/isom-2017-slide-2.
Full textAbstract:
Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.
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Nawaz, Gareeb, and Chhagan Charan. "The Design of An LDO Regulator." ITM Web of Conferences 54 (2023): 02010. http://dx.doi.org/10.1051/itmconf/20235402010.
Full textAbstract:
In today’s modern systems on chip (SOCs), a crucial power management circuit is the low-dropout (LDO) regulator. Of course, the need for supply voltage regulation, goes back many years in the past since the circuits have been designed. Today, LDO based voltage regulators are frequently used in a number of mixed-signal systems to produce local supply voltages that feed different building blocks. LDOs try to isolate the noise of the circuit and noise from the global supply and try to reduce their effect on device performance. For the state of desired achievement, each LDO’s architecture is circuited to the specific cell it feeds. An LDO designed to feed a flash analog-to-digital converter, for instance, differs greatly from one designed to input a VCO. In this paper, we direct an LDO for a VCO of 5-GHz LC and point the particulars of 1.2 V as input voltage, produces 1V as output voltage, 5 mA of maximum output current, power supply rejection greater than 40 dB up to 10 MHz and noise voltage present at output that is less than 25nV/√Hz at 1 MHz.
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Ahmed, Mohammed Altaf, and Suleman Alnatheer. "Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM." Micromachines 13, no. 6 (June 19, 2022): 971. http://dx.doi.org/10.3390/mi13060971.
Full textAbstract:
Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-In Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-In Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.