Relevant bibliographies by topics / Systems on chip (SoCs)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
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  5. Conference papers
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Academic literature on the topic 'Systems on chip (SoCs)'

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Published: 25 May 2024

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Journal articles on the topic "Systems on chip (SoCs)"

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Piguet, Christian. "Power consumption reduction in systems on Chip (SoCs)." Annales Des Télécommunications 59, no. 7-8 (July 2004): 884–902. http://dx.doi.org/10.1007/bf03180026.

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Hansson, Andreas, Kees Goossens, and Andrei Rădulescu. "Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip." VLSI Design 2007 (April 30, 2007): 1–10. http://dx.doi.org/10.1155/2007/95859.

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Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions introduce message dependencies that affect deadlock properties of the SoC as a whole. Even when NoC and IP dependency graphs are cycle-free in isolation, put together they may still create cycles. Traditionally, SoCs rely solely on request-response protocols. However, emerging SoCs adopt higher-level protocols for cache coherency, slave locking, and peer-to-peer streaming, thereby increasing the complexity in the interaction between the NoC and the IPs. In this paper, we analyze message-dependent deadlock, arising due to protocol interactions between the NoC and the IP modules. We compare the possible solutions and show that deadlock avoidance, in the presence of higher-level protocols, poses a serious challenge for many current NoC architectures. We evaluate the solutions qualitatively, and for a number of designs we quantify the area cost for the two most economical solutions, strict ordering and end-to-end flow control. We show that the latter, which avoids deadlock for all protocols, adds an area and power cost of 4% and 6%, respectively, of a typical Æthereal NoC instance.
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Boutekkouk, Fateh, Mohammed Benmohammed, Sebastien Bilavarn, and Michel Auguin. "UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs)." Journal of Object Technology 8, no. 1 (2009): 135. http://dx.doi.org/10.5381/jot.2009.8.1.a1.

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Maity, Srijeeta, Anirban Ghose, Soumyajit Dey, and Swarnendu Biswas. "Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–28. http://dx.doi.org/10.1145/3477028.

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Recent trends in real-time applications have raised the demand for high-throughput embedded platforms with integrated CPU-GPU based Systems-On-Chip (SoCs). The enhanced performance of such SoCs, however, comes at the cost of increased power consumption, resulting in significant heat dissipation and high on-chip temperatures. The prolonged occurrences of high on-chip temperature can cause accelerated in-circuit ageing, which severely degrades the long-term performance and reliability of the chip. Violation of thermal constraints leads to on-board dynamic thermal management kicking-in, which may result in timing unpredictability for real-time tasks due to transient performance degradation. Recent work in adaptive software design have explored this issue from a control theoretic stand-point, striving for smooth thermal envelopes by tuning the core frequency. Existing techniques do not handle thermal violations for periodic real-time task sets in the presence of dynamic events like change of task periodicity, more so in the context of heterogeneous SoCs with integrated CPU-GPUs. This work presents an OpenCL runtime extension for thermal-aware scheduling of periodic, real-time tasks on heterogeneous multi-core platforms. Our framework mitigates dynamic thermal violations by adaptively tuning task mapping parameters, with the eventual control objective of satisfying both platform-level thermal constraints and task-level deadline constraints. We consider multiple platform-level control actions like task migration, frequency tuning and idle slot insertion as the task mapping parameters. To the best of our knowledge, this is the first work that considers such a variety of task mapping control actions in the context of heterogeneous embedded platforms. We evaluate the proposed framework on an Odroid-XU4 board using OpenCL benchmarks and demonstrate its effectiveness in reducing thermal violations.
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Bogdan, Paul, Tudor Dumitraş, and Radu Marculescu. "Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip." VLSI Design 2007 (April 22, 2007): 1–17. http://dx.doi.org/10.1155/2007/95348.

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As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design and verification for Systems-on-Chip (SoCs) are rapidly increasing. Relaxing the requirement of 100% correctness for devices and interconnects drastically reduces the costs of design but, at the same time, requires SoCs to be designed with some degree of system-level fault-tolerance. Towards this end, this paper introduces a novel communication paradigm for SoCs, called stochastic communication. This scheme separates communication from computation by allowing the on-chip interconnect to be designed as a reusable IP and also provides a built-in tolerance to DSM failures, without a significant performance penalty. By using this communication scheme, a large percentage of data upsets, packet losses due to buffers overflow, and severe levels of synchronization failures can be tolerated, while providing high levels of performance.
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Si, Qilin, Santosh Shetty, and Benjamin Carrion Schaefer. "Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs." Electronics 10, no. 14 (July 20, 2021): 1746. http://dx.doi.org/10.3390/electronics10141746.

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High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and Digital Signal Processing (DSP) image processing accelerators. Unfortunately, HLS is a single process (component) synthesis method. Thus, the integration of these accelerators has to be performed at the RT level (Verilog or VHDL). This implies that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS. To address this, this work presents a methodology to generate entire heterogeneous SoCs in C. This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of synthesizable bus interfaces that allow any component in the system to send or receive data through the bus. Moreover, this work investigates the generation of processors and interfaces (peripherals) at the behavioral level as these are important parts of any SoCs, but have long been thought not to be efficiently synthesizable using HLS. Generating complete SoCs in C has significant advantages over traditional approaches. First, it enables the generation of fast cycle-accurate simulation models of the entire SoC, making the verification faster and easier. Second, it allows completely isolating the bus implementation details from the developers’ view, allowing the change between bus protocols with only minor changes in the designers’ code. Thirdly, it allows generating different SoC variants quickly by only changing the HLS synthesis options. Experimental results highlight these benefits.
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Touati, Djallel Eddine, Aziz Oukaira, Ahmad Hassan, Mohamed Ali, Ahmed Lakhssassi, and Yvon Savaria. "Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors." Electronics 12, no. 13 (July 6, 2023): 2978. http://dx.doi.org/10.3390/electronics12132978.

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The reliability and lifetime of systems-on-chip (SoCs) are being seriously threatened by thermal issues. In modern SoCs, dynamic thermal management (DTM) uses the thermal data captured by thermal sensors to constantly track the hot spots and thermal peak locations in real time. Estimating peak temperatures and the location of these peaks can play a crucial role for DTM systems, as temperature underestimation can cause SoCs to fail and have shortened lifetime. In this paper, a novel sensor allocation algorithm (called thermal gradient tracker, TGT), based on the recursive elimination of regions that likely do not contain any thermal peaks, is proposed for determining regions that potentially contain thermal peaks. Then, based on an empirical source temperature detection technique called GDS (gradient direction sensor), a hybrid algorithm for detecting the position and temperature of thermal peaks is also proposed to increase the accuracy of temperature sensing while trying to keep the number of thermal sensors to a minimum. The essential parameters, H and R, of the GDS technique are determined using an automated search algorithm based on simulated annealing. The proposed algorithm has been applied in a system-on-chip (SoC) in which four heat sources are present, and for temperatures ranging between 45 °C and 115 °C, in a chip area equal to 25 mm2. The simulation results show that our proposed sensor allocation scheme can detect on-chip peaks with a maximum error of 1.48 °C and an average maximum error of 0.49 °C by using 15 thermal sensors.
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Tong, Huyan. "An Overview on On-chip Network Routing Optimisation." Applied and Computational Engineering 8, no. 1 (August 1, 2023): 191–95. http://dx.doi.org/10.54254/2755-2721/8/20230123.

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As the number of cores in multi-core systems increases, bus-based systems face significant challenges in terms of scalability, average transmission latency and power consumption. In this context, on-chip networks emerged as a suitable communication architecture for System On Chip (SoC) based entirely on the communication ideas in computer networks and taking into account the characteristics of the system on chip in SoCs. With the introduction of on-chip networks, related research has been developed, such as on-chip network topology, communication quality of service, on-chip network routing algorithms, and on-chip network fault tolerance. He then introduces on-chip network routing algorithms and fault-tolerant routing algorithms from different perspectives, and finally points out the directions of fault-tolerant routing algorithms worthy of research.
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Lu, Jian, Hongwei Jia, Andres Arias, Xun Gong, and Z. John Shen. "On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip." International Journal of Power Management Electronics 2008 (July 16, 2008): 1–9. http://dx.doi.org/10.1155/2008/678415.

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A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC). We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.
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Nandi, Purab, K. R. Anupama, Himanish Agarwal, Arav Jain, and Siddharth Paliwal. "Use of the k-nearest neighbour and its analysis for fall detection on Systems on a Chip for multiple datasets." Acta IMEKO 12, no. 3 (September 18, 2023): 1–11. http://dx.doi.org/10.21014/actaimeko.v12i3.1489.

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Fall of an elderly person often leads to serious injuries and death. Many falls occur in the home environment, and hence a reliable fall detection system that can raise alarms with minimum latency is a necessity. Wrist-worn accelerometer-based fall detection systems and multiple datasets are available, but no attempt has been made to analyze the accuracy and precision. Wherever the comparison does exist, it has been run on a cloud. No analysis of the models, convergence, and dataset analysis on Systems on a Chip (SoCs) has ever been attempted. In this paper, we attempt to present why Machine Learning (ML) algorithms in their current state cannot be run on existing SoCs. We have used Snapdragon 410c SoC to do our analytics. In this paper, we have used the kth-nearest neighbour to prove that ML cannot be directly run on SoCs. We have looked at the effect of distance metrics and neighbors as well as the effect of feature extraction on the accuracies and the latencies. In this paper, we establish the need for model compression and data pruning for fall detection using ML/Deep Learning algorithms on SoCs. We have done this by analyzing various datasets on varying architectural parameters.
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Dissertations / Theses on the topic "Systems on chip (SoCs)"

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Yoon, Jang-Sup. "Embedded test circuit and methods for radio frequency (RF) systems-on-a-chip (SoCs)." [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0015657.

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Weiss, Alexander. "Effiziente externe Beobachtung von CPU-Aktivitäten auf SoCs." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-184227.

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Die umfassende Beobachtbarkeit von System‐on‐Chips (SoCs) ist eine wichtige Voraussetzung für das effiziente Testen und Debuggen eingebetteter Systeme. Ausgehend von einer Analyse verschiedener Anwendungsfälle ergibt sich ein Katalog von Anforderungen an die Beobachtbarkeit von SoCs. Ein wichtiges Kriterium ist hier die Vollständigkeit der Beobachtung und umfasst die Aktivitäten der CPU (ausgeführte Instruktionen, gelesene und geschriebene Daten, Verhalten des Caches, Ausführungszeiten), des Bussystems und von Umgebungsbedingungen. Weitere Kriterien sind die Echtzeitfähigkeit und die Kontinuität der Beobachtung sowie die gleichzeitige Durchführung verschiedener Beobachtungsaufgaben. Dabei soll es zu einer möglichst geringen Beeinflussung des SoCs kommen. Weitere wichtige Aspekt sind die Kosten der Lösung, die Universalität, die Skalierbarkeit sowie die Latenz der Verfügbarkeit der Beobachtungsergebnisse. Für viele Anwendungen, besonders in sicherheitskritischen Bereichen, muss zudem nachgewiesen werden, dass das Beobachtungsverfahren kein Fehlverhalten des SoCs bewirkt bzw. ein solches maskiert. Eine besondere Herausforderung stellen Multiprozessor‐SoCs (MPSoCs) dar, da hier die Kommunikation zwischen den einzelnen CPUs im Inneren des SoC stattfindet und entsprechend schwierig für einen externen Bobachter sichtbar zu machen ist. Der Stand der Technik zur Beobachtung von SoCs wird im Wesentlichen durch zwei Verfahren dargestellt. Bei der Software‐Instrumentierung wird zum funktionalen Programmcode zusätzlicher Code hinzugefügt, welcher zur Beobachtung des Programms dient. Diese Methode ist einfach und universell anwendbar, erfüllt aber die genannten Kriterien nur sehr eingeschränkt. Nachteilig ist hier der Ressourcenverbrauch im Falle des Verbleibs der Instrumentierung im fertigen Produkt. Wird die Instrumentierung nur temporär dem Code hinzugefügt, muss sichergestellt werden, dass das Beobachtungsergebnis auch für den finalen Code anwendbar ist – was besonders bei ressourcen‐abhängigen Integrationstests nur schwierig erfüllbar ist. Eine alternative Lösung stellt eine spezielle Hardware‐Unterstützung in SoCs („embedded Trace“) dar. Hier werden im SoC Zustandsinformationen (z.B. Taskwechsel, ausgeführte Instruktionen, Datentransfers) gesammelt und mittels Trace‐Nachrichten an den Beobachter übermittelt. Dabei stellt die Bandbreite, die zur Ausgabe der Trace‐Nachrichten vom SoC verfügbar ist, ein entscheidendes Nadelöhr dar ‐ im SoC sind viel mehr den Beobachter interessierende Informationen verfügbar als nach außen transferiert werden können. Damit haben beide dem gegenwärtige Stand der Technik entsprechende Beobachtungsverfahren eine Reihe von Einschränkungen, die sich besonders bei der Vollständigkeit der Beobachtung, der Flexibilität, der Kontinuität und der Unterstützung von MPSoCs zeigen. In dieser Arbeit wird nun ein neuer Ansatz vorgestellt, welcher gegenüber dem Stand der Technik in einigen Bereichen deutliche Verbesserungen bietet. Dabei werden die Trace‐Daten nicht vom zu beobachtenden SoC direkt, sondern aus einer parallel mitlaufenden Emulation gewonnen. Die Bandbreite der für die Synchronisation der Emulation erforderlichen Daten ist in vielen Fällen deutlich geringer als bei der Ausgabe von umfassenden Trace‐Nachrichten mittels „embedded Trace“‐Lösungen. Gleichzeitig ist eine vollständige, äußerst detaillierte Beobachtung der Vorgänge innerhalb des SoC möglich. Das neue Beobachtungsverfahren wurde mittels verschiedener FPGA-basierter Implementierungen evaluiert, hier konnte auch die Anwendbarkeit für MPSoCs gezeigt werden.
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Bolzani, Leticia Maria Veiras. "Explorando uma solução híbrida: hardware+software para a detecção de falhas tempo real em systems-on-chip (SoCs)." Pontifícia Universidade Católica do Rio Grande do Sul, 2005. http://hdl.handle.net/10923/3146.

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The always increasing number of computer-based safety-critical applications has intensified the research over fault tolerance techniques. While those systems are working, the probability of both permanent and transient faults happens due to the presence of all sort of interference. The common faults are those which affect data and/or modify the expected program execution flow. Thus, the use of techniques allowing detecting these type of faults presents them from propagating to system output. Basically, these techniques are categorized in two groups: software-based approaches and hardware-based approaches. Considering the above introduced, the goal of this work is to specify and to implement a hybrid approach, which combines software-based techniques and hardware-based ones, capable to detect run time data and algorithm control flow faults. It is settled around the techniques proposed in (REBAUDENGO, 2004) and (GOLOUBEVA, 2003). Nevertheless, the proposed approach implements part of its code-transformation rules via software and hardware. These redundant information is added to the software portion and consistency checks are implemented via hardware. Summary, we propose the development of an I-IP (infrastructure intellectual property) core, such as watchdog, to correctly execute the consistency checks concurrently to the application execution. In this work, three different versions of the I-IP were implemented in VHDL and analyzed by means of fault injection experiments. The first implemented version allows data fault detection and, as any prototype, has its limitations. The second version also detects data faults, but eliminates the problems of the former version. The third I-IP version adds the capability of detecting control flow faults to the previous versions of the I-IP. Finally, after implementing these three versions, a fourth version was specified. It adds dependability and robustness to the IIP by using Built-in Self-Test (BIST) techniques. The results obtained from evaluating the different I-IP core versions guarantee that the hybrid approach is efficient, because it features high fault coverage and surpasses the main problems present in software-based techniques proposed in the literature, such as, performance degradation and code/data memory overhead. Finally, this work is a partial result of a joint research project carried by the SiSC Group – PUCRS and CAD – Politecnico di Torino, under the scope of the Alfa Project (##AML/B7-311- 97/0666/II-0086-FI, from 2002 to 2005).
Nos últimos anos, o crescente aumento do número de aplicações críticas baseadas em sistemas eletrônicos, intensificou a pesquisa sobre técnicas de tolerância à falhas. Durante o período de funcionamento destes sistemas, a probabilidade de ocorrerem falhas transientes e permanentes devido à presença de interferências dos mais variados tipos é bastante grande. Dentre as falhas mais freqüentes, salientam-se as falhas que corrompem os dados e as falhas que alteram o fluxo de controle do processador que executa a aplicação. Assim, a utilização de técnicas capazes de detectarem estes tipos de falhas evita que as mesmas se propaguem pelo sistema e acabem gerando saídas incorretas. Basicamente, estas técnicas são classificadas em dois grandes grupos: soluções baseadas em software e soluções baseadas em hardware. Neste contexto, o objetivo principal deste trabalho é especificar e implementar uma solução híbrida, parte em software e parte em hardware, capaz de detectar em tempo de execução eventuais falhas em dados e no fluxo de controle do algoritmo. Esta solução baseia-se nas técnicas propostas em (REBAUDENGO, 2004) e (GOLOUBEVA, 2003) e implementa parte de suas regras de transformação de código via software e parte via hardware. Assim, informações redundantes são agregadas ao código da aplicação e testes de consistência são implementados via hardware. Em resumo, este trabalho propõe o desenvolvimento de um núcleo I-IP (infrastructure intellectual property), tal como um watchdog, para executar os testes de consistência concorrentemente à execução da aplicação. Para isto, três versões diferentes do I-IP foram implementadas em linguagem de descrição de hardware (VHDL) e avaliadas através de experimentos de injeção de falhas.A primeira versão implementada provê a detecção de falhas em dados e, como todo protótipo, este também apresenta algumas restrições e limitações. A segunda versão também detecta falhas em dados, entretanto, supera todos os problemas da versão anterior. A terceira versão do I-IP agrega à versão anterior a capacidade de detectar falhas de fluxo de controle. Finalmente, após a implementação das versões anteriores, foi especificada uma quarta versão que agrega confiabilidade e robustez ao I-IP desenvolvido através da utilização de algumas técnicas de tolerância a falhas e da especificação de um auto-teste funcional. Os resultados obtidos a partir da avaliação das versões do I-IP garantem que a metodologia proposta neste trabalho é bastante eficiente, pois apresenta uma alta cobertura de falhas e supera os principais problemas presentes nas soluções baseadas em software propostas na literatura, ou seja, degradação de desempenho e maior consumo de memória. Finalmente, cabe mencionar que esta dissertação é o resultado parcial de atividades que fazem parte do escopo do Projeto Alfa (#AML/B7-311-97/0666/II-0086-FI) mantido entre os Grupos SiSC – PUCRS (Brasil) e CAD – Politecnico di Torino (Itália) no período de 2002-2005.
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Reehal, Gursharan Kaur. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.

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Bolzani, Leticia Maria Veiras. "Explorando uma solu??o h?brida : hardware+software para a detec??o de falhas tempo real em systems-on-chip (SoCs)." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2005. http://tede2.pucrs.br/tede2/handle/tede/3001.

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Nos ?ltimos anos, o crescente aumento do n?mero de aplica??es cr?ticas baseadas em sistemas eletr?nicos, intensificou a pesquisa sobre t?cnicas de toler?ncia ? falhas. Durante o per?odo de funcionamento destes sistemas, a probabilidade de ocorrerem falhas transientes e permanentes devido ? presen?a de interfer?ncias dos mais variados tipos ? bastante grande. Dentre as falhas mais freq?entes, salientam-se as falhas que corrompem os dados e as falhas que alteram o fluxo de controle do processador que executa a aplica??o. Assim, a utiliza??o de t?cnicas capazes de detectarem estes tipos de falhas evita que as mesmas se propaguem pelo sistema e acabem gerando sa?das incorretas. Basicamente, estas t?cnicas s?o classificadas em dois grandes grupos: solu??es baseadas em software e solu??es baseadas em hardware. Neste contexto, o objetivo principal deste trabalho ? especificar e implementar uma solu??o h?brida, parte em software e parte em hardware, capaz de detectar em tempo de execu??o eventuais falhas em dados e no fluxo de controle do algoritmo. Esta solu??o baseia-se nas t?cnicas propostas em (REBAUDENGO, 2004) e (GOLOUBEVA, 2003) e implementa parte de suas regras de transforma??o de c?digo via software e parte via hardware. Assim, informa??es redundantes s?o agregadas ao c?digo da aplica??o e testes de consist?ncia s?o implementados via hardware. Em resumo, este trabalho prop?e o desenvolvimento de um n?cleo I-IP (infrastructure intellectual property), tal como um watchdog, para executar os testes de consist?ncia concorrentemente ? execu??o da aplica??o. Para isto, tr?s vers?es diferentes do I-IP foram implementadas em linguagem de descri??o de hardware (VHDL) e avaliadas atrav?s de experimentos de inje??o de falhas. A primeira vers?o implementada prov? a detec??o de falhas em dados e, como todo prot?tipo, este tamb?m apresenta algumas restri??es e limita??es. A segunda vers?o tamb?m detecta falhas em dados, entretanto, supera todos os problemas da vers?o anterior. A terceira vers?o do I-IP agrega ? vers?o anterior a capacidade de detectar falhas de fluxo de controle. Finalmente, ap?s a implementa??o das vers?es anteriores, foi especificada uma quarta vers?o que agrega confiabilidade e robustez ao I-IP desenvolvido atrav?s da utiliza??o de algumas t?cnicas de toler?ncia a falhas e da especifica??o de um auto-teste funcional. Os resultados obtidos a partir da avalia??o das vers?es do I-IP garantem que a metodologia proposta neste trabalho ? bastante eficiente, pois apresenta uma alta cobertura de falhas e supera os principais problemas presentes nas solu??es baseadas em software propostas na literatura, ou seja, degrada??o de desempenho e maior consumo de mem?ria. Finalmente, cabe mencionar que esta disserta??o ? o resultado parcial de atividades que fazem parte do escopo do Projeto Alfa (#AML/B7-311-97/0666/II-0086-FI) mantido entre os Grupos SiSC PUCRS (Brasil) e CAD Politecnico di Torino (It?lia) no per?odo de 2002-2005.
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Terosiet, Medhi. "Conception d'un oscillateur robuste contrôlé numériquement pour l'horlogerie des SoCs." Phd thesis, Université Pierre et Marie Curie - Paris VI, 2012. http://tel.archives-ouvertes.fr/tel-00836916.

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L'intégration d'un plus grand nombre de fonctions sur des circuits intégrés plus rapides à chaque nouvelle génération. Malheureusement, elles ont rendu la tâche des concepteurs plus difficile, avec notamment la montée de la puissance consommée et des temps de propagation des signaux à travers la puce. La distribution de l'horloge, assurant le synchronisme des opérations du circuit, en est l'élément le plus symptomatique. La génération distribuée de l'horloge apparaît comme une alternative aux solutions classiques. Elle repose sur la mise en place d'un réseau de N oscillateurs géographiquement distribués sur l'ensemble de la puce. Chaque oscillateur génère localement une horloge pour la zone de la puce dans laquelle il se trouve. La phase d'une horloge est accordée sur celle de ces proches voisines. Ainsi, l'horloge n'a plus à parcourir de long chemin. Toutefois, les performances du circuit d'horloge sont liées, non pas à un, mais à N oscillateurs évoluant dans un environnement hostile (variations de l'alimentation, de la température, etc.). Aussi, les travaux de cette thèse portent sur la conception d'un oscillateur contrôlé numériquement. Plus précisément, notre problématique est : " Comment concevoir un DCO (Digitally Controlled Oscillator) robuste soumis à l'environnement hostile d'un SoC en technologie CMOS submicronique ? ". Pour répondre à cette question, nous proposons, dans un premier temps, la modélisation d'une topologie d'oscillateur contrôlé numériquement ; le but étant de déterminer sa pertinence quant à notre application d'horlogerie. Comme cette dernière est émergente, il n'y a à l'heure actuelle aucune théorie la caractérisant. A travers notre analyse, nous mettons en évidence ses faiblesses et la nécessité de lui adjoindre des circuits de protection. De ce fait, les performances du circuit d'horloge ne sont plus seulement dépendantes de l'oscillateur, mais aussi des dispositifs mis en place pour le protéger des agressions des circuits environnants. Ce constat a motivé le développement d'une alternative qui ne serait pas soumise aux mêmes contraintes. Nous proposons finalement un oscillateur contrôlé numériquement robuste à la fois contre les variations de l'alimentation et de la température. Cet oscillateur est conçu à partir de blocs analogiques connus et bien décrits par la littérature. Pour limiter l'influence de la tension d'alimentation et de la température à laquelle évolue l'oscillateur, nous tirons profit des effets de canal court propres aux technologies submicroniques.
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Aghaee, Ghaleshahi Nima. "Thermal Issues in Testing of Advanced Systems on Chip." Doctoral thesis, Linköpings universitet, Institutionen för datavetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-120798.

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deep-submicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis. Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors. Advanced SoCs manufactured as 3D stacked ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be artificially accelerated using gradient-based, burn-in like, operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. A schedule-based technique that enforces the temperature-gradients for burn-in like operations is proposed in this thesis. This technique is further developed to support testing for delay-related defects while appropriate gradients are enforced. The last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safety-critical applications to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced. All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC’02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the costs, in particular the costs related to addressing thermal issues and early-life failures. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the schedule generation time by more than half.
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MEDARDONI, Simone. "Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip." Doctoral thesis, Università degli studi di Ferrara, 2009. http://hdl.handle.net/11392/2389197.

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The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout.
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Tambara, Lucas Antunes. "Caracterização de circuitos programáveis e sistemas em chip sob radiação." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/86477.

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Este trabalho consiste em um estudo acerca dos efeitos da radiação em circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SoC), baseados em FPGAs (Field-Programmable Gate Array). Dentre os diversos efeitos que podem ensejar falhas nos circuitos integrados, destacam-se a ocorrência de Single Event Effects (SEEs), Efeitos Transitórios em tradução livre, e a Dose Total Ionizante, do inglês Total Ionizing Dose (TID). SEEs podem ocorrer em razão da incidência de nêutrons originários de interações de raios cósmicos com a atmosfera terrestre, íons pesados provenientes do espaço e prótons originários do Sol (vento solar) e dos cinturões de Van Allen. A Dose Total Ionizante diz respeito à exposição prolongada de um circuito integrado à radiação ionizante e cuja consequência é a alteração das características elétricas de partes do dispositivo em razão das cargas elétricas induzidas pela radiação e acumuladas nas interfaces dos semicondutores. Dentro desse contexto, este trabalho descreve em detalhes a caracterização do SoC-FPGA baseado em memória FLASH e de sinais mistos SmartFusion A2F200-FG484, da empresa Microsemi, quando exposto à radiação (SEEs e TID) através do uso da técnica de Redundância Diversificada visando a detecção de erros. Também, uma arquitetura que utiliza um esquema baseado em Redundância Modular Tripla e Diversificada é testada através da sua implementação no FPGA baseado em memória SRAM da família Spartan-6, modelo LX45, da empresa Xilinx, visando a detecção e correção de erros causados pela radiação (SEEs). Os resultados obtidos mostram que os diversos blocos funcionais que compõe SoC SmartFusion apresentam diferentes níveis de tolerância à radiação e que o uso das técnicas de Redundância Modular Tripla e Redundância Diversificada em conjunto mostrou-se extremamente eficiente no que se refere a tolerância a SEEs.
This work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.
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Cota, Erika Fernandes. "Reuse-based test planning for core-based systems-on-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2003. http://hdl.handle.net/10183/4180.

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O projeto de sistemas eletrônicos atuais segue o paradigma do reuso de componentes de hardware. Este paradigma reduz a complexidade do projeto de um chip, mas cria novos desafios para o projetista do sistema em relação ao teste do produto final. O acesso aos núcleos profundamente embutidos no sistema, a integração dos diversos métodos de teste e a otimização dos diversos fatores de custo do sistema são alguns dos problemas que precisam ser resolvidos durante o planejamento do teste de produção do novo circuito. Neste contexto, esta tese propõe duas abordagens para o planejamento de teste de sistemas integrados. As abordagens propostas têm como principal objetivo a redução dos custos de teste através do reuso dos recursos de hardware disponíveis no sistema e da integração do planejamento de teste no fluxo de projeto do circuito. A primeira abordagem considera os sistemas cujos componentes se comunicam através de conexões dedicadas ou barramentos funcionais. O método proposto consiste na definição de um mecanismo de acesso aos componentes do circuito e de um algoritmo para exploração do espaço de projeto. O mecanismo de acesso prevê o reuso das conexões funcionais, o uso de barramentos de teste locais, núcleos transparentes e outros modos de passagem do sinal de teste. O algoritmo de escalonamento de teste é definido juntamente com o mecanismo de acesso, de forma que diferentes combinações de custos sejam exploradas. Além disso, restrições de consumo de potência do sistema podem ser consideradas durante o escalonamento dos testes. Os resultados experimentais apresentados para este método mostram claramente a variedade de soluções que podem ser exploradas e a efi- ciência desta abordagem na otimização do teste de um sistema complexo. A segunda abordagem de planejamento de teste propõe o reuso de redes em-chip como mecanismo de acesso aos componentes dos sistemas construídos sobre esta plataforma de comunicação. Um algoritmo de escalonamento de teste que considera as restrições de potência da aplicação é apresentado e a estratégia de teste é avaliada para diferentes configurações do sistema. Os resultados experimentais mostram que a capacidade de paralelização da rede em-chip pode ser explorada para reduzir o tempo de teste do sistema, enquanto os custos de área e pinos de teste são drasticamente minimizados. Neste manuscrito, os principais problemas relacionados ao teste dos sistemas integrados baseados em componentes virtuais são identificados e as soluções já apresentadas na literatura são discutidas. Em seguida, os problemas tratados por este traballho são listados e as abordagens propostas são detalhadas. Ambas as técnicas são validadas através dos sistemas disponíveis no ITC’02 SoC Test Benchmarks. As técnicas propostas são ainda comparadas com outras abordagens de teste apresentadas recentemente. Esta comparação confirma a eficácia dos métodos desenvolvidos nesta tese.
Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.
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Books on the topic "Systems on chip (SoCs)"

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Modeling embedded systems and SoCs: Concurrency and time in models of computation. San Francisco: Morgan Kaufmann, 2004.

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Kempf, Torsten, Gerd Ascheid, and Rainer Leupers. Multiprocessor Systems on Chip. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8153-0.

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Allard, Bruno, ed. Power Systems-On-Chip. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.

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Vermeulen, Bart, and Kees Goossens. Debugging Systems-on-Chip. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-06242-6.

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Abderazek, Ben A. Multicore systems on chip. Trivandrum, Kerala, India: Transworld Research Network, 2007.

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Ben Abdallah, Abderazek. Advanced Multicore Systems-On-Chip. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2.

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Silveira, Luis Miguel, Srinivas Devadas, and Ricardo Reis, eds. VLSI: Systems on a Chip. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9.

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Bou-Sleiman, Sleiman. Built-in-Self-Test and Digital Self-Calibration for RF SoCs. New York, NY: Springer Science+Business Media, LLC, 2012.

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Knipfer, Brent J. Multichip packaging and bare chip systems. Norwalk, CT: Business Communications Co., 1994.

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Lim, Leycheoh. Chip interleaving for CDMA cellular systems. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1999.

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Book chapters on the topic "Systems on chip (SoCs)"

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Ben Abdallah, Abderazek. "Multicore SoCs Design Methods." In Advanced Multicore Systems-On-Chip, 19–37. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_2.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "Application-specific SOCs." In System on Chip (SOC) Architecture, 49–63. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_4.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "Storage in SOCs." In System on Chip (SOC) Architecture, 65–73. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_5.

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Ben Abdallah, Abderazek. "Power Optimization Techniques for Multicore SoCs." In Advanced Multicore Systems-On-Chip, 225–44. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6092-2_8.

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Ben Abdallah, Abderazek. "Multicore SoCs Design Methods." In Multicore Systems On-Chip: Practical Software/Hardware Design, 19–35. Paris: Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3_2.

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Ben Abdallah, Abderazek. "Power Optimization Techniques for Multicore SoCs." In Multicore Systems On-Chip: Practical Software/Hardware Design, 175–93. Paris: Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3_8.

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Ben Abdallah, Abderazek. "Soft-Core Processor for Low-Power Embedded Multicore SoCs." In Multicore Systems On-Chip: Practical Software/Hardware Design, 195–213. Paris: Atlantis Press, 2013. http://dx.doi.org/10.2991/978-94-91216-92-3_9.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "Introduction to Systems." In System on Chip (SOC) Architecture, 1–15. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_1.

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Kirchner, Aljoscha. "Stand der Technik." In Entwicklung von Methoden zur abstrakten Modellierung von Automotive Systems-on-Chips, 49–64. Wiesbaden: Springer Fachmedien Wiesbaden, 2022. http://dx.doi.org/10.1007/978-3-658-38437-1_3.

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ZusammenfassungDie in dieser Arbeit entwickelte modellbasierte Entwicklungsmethode soll über alle Phasen der Entwicklung hinweg durch einen modellbasierten Ansatz Defizite im aktuellen Flow beseitigen und die Effizienz der SoC-Entwicklung in Gesamtheit steigern. Nach aktuellem Stand gibt es nach Wissen des Autors keine existierende Lösung für die modellbasierte Systementwicklung von Automotive SoCs, welche dabei den gesamten Entwicklungs-Flow von der Analyse der Kundenanforderungen bis zum Systementwurf berücksichtigt und dabei eine Automatisierung des Entwurfs sowie der Verifikationserstellung ermöglicht. Daher erfolgt in diesem Kapitel eine Betrachtung von Lösungsansätzen aus der Literatur, welche Teilbereiche des SoC-Entwicklungs-Flows abdecken bzw. einen Teil der gestellten Anforderungen erfüllen.
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Nourani, Mehrdad, Amir Attarha, and Krishnendu Chakrabarty. "Signal Integrity: Fault Modeling and Testing in High-Speed SoCs." In SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 175–90. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-6527-4_12.

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Conference papers on the topic "Systems on chip (SoCs)"

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Abraham, Jacob A. "“Manufacturing test of systems-on-a-chip (SoCs)”." In 2011 IEEE 24th International SOC Conference (SOCC). IEEE, 2011. http://dx.doi.org/10.1109/socc.2011.6085148.

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Nautiyal, Vivek. "W2B: Design methodologies for SoCs." In 2017 30th IEEE International System-on-Chip Conference (SOCC). IEEE, 2017. http://dx.doi.org/10.1109/socc.2017.8226006.

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Forsell, Martti. "Realizing Multioperations for Step Cached MP-SOCs." In 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.321972.

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Zhong, Wei, Song Chen, Fei Ma, Takeshi Yoshimura, and Satoshi Goto. "Floorplanning driven Network-on-Chip synthesis for 3-D SoCs." In 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5937785.

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Fox, Paul J., A. Theodore Markettos, and Simon W. Moore. "Reliably prototyping large SoCs using FPGA clusters." In 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2014. http://dx.doi.org/10.1109/recosoc.2014.6861350.

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Liao, Xiongfei, Jun Zhou, and Xin Liu. "Exploring AMBA AXI on-Chip interconnection for TSV-based 3D SoCs." In 2011 IEEE International 3D Systems Integration Conference (3DIC). IEEE, 2012. http://dx.doi.org/10.1109/3dic.2012.6263036.

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Mishra, S., V. Sankatali, B. Vermeersch, M. Brunion, M. Lofrano, D. Abdi, H. Oprins, et al. "Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs)." In 2023 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2023. http://dx.doi.org/10.1109/irps48203.2023.10117979.

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Tomoutzoglou, Othon, Dimitrios Bakoyannis, George Kornaros, and Marcello Coppola. "Efficient communication in heterogeneous SoCs with unified address space." In 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2016. http://dx.doi.org/10.1109/recosoc.2016.7533904.

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Orsila, H., T. Kangas, and T. D. Hamalainen. "Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCs." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595665.

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Orsila, Heikki, Tero Kangas, Erno Salminen, and Timo Hamalainen. "Parameterizing Simulated Annealing for Distributing Task Graphs on Multiprocessor SoCs." In 2006 International Symposium on System-on-Chip. IEEE, 2006. http://dx.doi.org/10.1109/issoc.2006.321971.

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Reports on the topic "Systems on chip (SoCs)"

1

Bambha, Neal K., and Shuvra S. Bhattacharyya. Interconnect Synthesis for Systems on Chip. Fort Belvoir, VA: Defense Technical Information Center, July 2004. http://dx.doi.org/10.21236/ada448078.

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Bambha, Neal K., Shuvra S. Bhattacharyya, and Gary Euliss. Design Considerations for Optically Connected Systems on Chip. Fort Belvoir, VA: Defense Technical Information Center, June 2003. http://dx.doi.org/10.21236/ada457628.

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Anton Carl Greenwald. MEMS CHIP CO2 SENSOR FOR BUILDING SYSTEMS INTEGRATION. Office of Scientific and Technical Information (OSTI), September 2005. http://dx.doi.org/10.2172/860161.

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Kirshberg, Jeffrey A. Microelectromechanical Systems (MEMS)-Based Microcapillary Pumped Loop for Chip-Level Temperature Control. Fort Belvoir, VA: Defense Technical Information Center, January 2002. http://dx.doi.org/10.21236/ada405777.

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Papapolymerou, Ioannis. Instrumentation for the Development of Reconfigurable Microwave/MM-Wave FGC Passive Elements Using MEMS Switches for 'Smart' Systems on a Chip. Fort Belvoir, VA: Defense Technical Information Center, July 2001. http://dx.doi.org/10.21236/ada394800.

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