Journal articles: 'System-on-chips'

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Koyanagi, M., H. Kurino, Kang Wook Lee, K. Sakuma, N. Miyakawa, and H. Itani. "Future system-on-silicon LSI chips." IEEE Micro 18, no. 4 (1998): 17–22. http://dx.doi.org/10.1109/40.710867.

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Miller, Chris P., Woojung Shin, Eun Hyun Ahn, Hyun Jung Kim, and Deok-Ho Kim. "Engineering Microphysiological Immune System Responses on Chips." Trends in Biotechnology 38, no. 8 (August 2020): 857–72. http://dx.doi.org/10.1016/j.tibtech.2020.01.003.

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Thomas, Anitta, and Shinoj J Vattakuzhi. "Simulation Results for a Crosstalk Avoidance and Low Power Coding Scheme for System on Chips." Bonfring International Journal of Research in Communication Engineering 6, no. 1 (February 29, 2016): 01–05. http://dx.doi.org/10.9756/bijrce.10444.

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Li, Chun Guang, Xiao Ming Ma, and Hai Jun Tang. "Experimental Research on Energy Spectrum Analysis on Chips from Aeroengine Oil System." Applied Mechanics and Materials 635-637 (September 2014): 957–61. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.957.

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Inspection on chips from oil system is an important method for modern aeroengine condition monitoring. Energy spectrum analysis technique is the most widely used and effective method in inspection on metal chips. In this method, size and quantity of chips are observed by scanning electronic microscope and qualitative and quantitative analysis of element contents are finished by energy dispersive spectrometer. Through above experiments, material type of metal chips can be analyzed and material mark can be determined by comparison with the materials list used in the aeroengine. In this article, characteristics and advantages of energy spectrum analysis technology are systematically introduced and typical appearance feature and energy spectrum curve of common l chips are summarized in engineering practice. In addition, problems and prospects of energy spectrum analysis technique are proposed.

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Liu, Kan, and Hao You. "Real-Time Micro-Fluidic Chip Pressure Control System Base on the Optical Interference." Applied Mechanics and Materials 494-495 (February 2014): 1274–77. http://dx.doi.org/10.4028/www.scientific.net/amm.494-495.1274.

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This article introduces a measurement system based on LabVIEW used for optical interference fringe on micro-fluidic chips. This system mainly uses cameras to capture real-time images of wedge interference fringe on micro-fluidic chips, then the collected images will be binarized by LabVIEW. The processed images will be divided by zone , determine the flatness and gap thickness of the micro-fluidic chips by interference fringes with different directions of deflection and numbers. Finally, feedback from measured data will be used to adjust the flatness and gap thickness of micro-fluidic chips in order to meet the requirement of tests.

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Xiao, Hao, Huajuan Zhang, Fen Ge, and Ning Wu. "A MapReduce architecture for embedded multiprocessor system-on-chips." IEICE Electronics Express 13, no. 2 (2016): 20151025. http://dx.doi.org/10.1587/elex.13.20151025.

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PIONTECK, THILO, CARSTEN ALBRECHT, ROMAN KOCH, and ERIK MAEHLE. "ADAPTIVE COMMUNICATION ARCHITECTURES FOR RUNTIME RECONFIGURABLE SYSTEM-ON-CHIPS." Parallel Processing Letters 18, no. 02 (June 2008): 275–89. http://dx.doi.org/10.1142/s0129626408003387.

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For exploiting the inherent parallelism enclosed in System-on-Chip designs, special architectural prerequisites have to be met. These prerequisites mainly affect the communication infrastructure, as parallel processing of all hardware modules accounts for a continuous and sufficient provision of data. While traditional communication architectures may fulfill these requirements for a fixed System-on-Chip design, changing composition, number and locations of processing modules in runtime reconfigurable System-on-Chips require new communication paradigms. Special communication architectures especially for use in runtime reconfigurable System-on-Chip designs are presented in this article. Their analysis provides a basis for the design of CoNoChi, a runtime reconfigurable Network-on-Chip dedicated for the usage in FPGA-based designs. CoNoChi supports the adaptation of the network topology during runtime by providing mechanisms to add or remove switches from the network during runtime without stopping or stalling the network. The applicability of CoNoChi is shown on the basis of a complex runtime reconfigurable System-on-Chip for networking applications. Prototyping results demonstrate that CoNoChi is a promising alternative to existing communication architectures supporting both a high degree of adaptability during runtime and a high concurrency of data transfers.

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Javaid, Haris, Aleksander Ignjatovic, and Sri Parameswaran. "Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs)." IEEE Transactions on Parallel and Distributed Systems 25, no. 8 (August 2014): 2159–68. http://dx.doi.org/10.1109/tpds.2013.268.

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Ravi, Srivaths, Rubin Parekhji, and Jayashree Saxena. "Low Power Test for Nanometer System-on-Chips (SoCs)." Journal of Low Power Electronics 4, no. 1 (April 1, 2008): 81–100. http://dx.doi.org/10.1166/jolpe.2008.155.

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Brekling, Aske, Michael R. Hansen, and Jan Madsen. "Models and formal verification of multiprocessor system-on-chips." Journal of Logic and Algebraic Programming 77, no. 1-2 (September 2008): 1–19. http://dx.doi.org/10.1016/j.jlap.2008.05.002.

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Guerrieri, Andrea, Sahand Kashani-Akhavan, Mikhail Asiatici, and Paolo Ienne. "Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips." IEEE Access 7 (2019): 103938–47. http://dx.doi.org/10.1109/access.2019.2931475.

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Mansouri, Imen, Pascal Benoit, Diego Puschini, Lionel Torres, Fabien Clermidy, and Gilles Sassatelli. "Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips." Journal of Low Power Electronics 6, no. 4 (December 1, 2010): 564–77. http://dx.doi.org/10.1166/jolpe.2010.1106.

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Nursito, Jabal, Rini Hustiany, and Alan Dwi Wibowo. "Active Packaging System from Activated Oil Palm Shells Charcoal Shaped Sachet on Cassava Chips." Jurnal Teknologi dan Industri Pertanian Indonesia 13, no. 2 (October 5, 2021): 50–57. http://dx.doi.org/10.17969/jtipi.v13i2.17631.

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Cassava chips are a type of snack that is fried and prone to rancidity if stored for a while. Cassava chips are added to the material that can adsorb gases, such as oxygen and water vapor, to reduce the occurrence of rancidity using a sachet-shaped adsorbent material. Activated charcoal is one of the gas adsorbents. Activated charcoal used is activated charcoal made from oil palm shells and activated with 20% phosphoric acid. This study aims to analyze the decrease in the quality of cassava chips with an active packaging system during storage for 30 days at 45oC. A total of 30 g cassava chips were packed with a standing pouch in polypropylene type and added activated charcoal from oil palm shells activated by 20% phosphoric acid as much as 1.5 g or 0.75 g which was packed with metalized aluminum plastic or LDPE plastic in the form of sachets. Storage of cassava chips with an active packaging system for 30 days and stored at a temperature of 45oC with a humidity of about 60% and observations are every 3 days in aroma and texture scoring test, moisture content, free fatty acid levels, fat content, and peroxide number. During storage from day 0 to day 30, the cassava chips have decreased the quality of the aroma from typical cassava chips to slightly rancid and the texture from crisp to somewhat not crisp. Moisture content, free fatty acid levels, and peroxide numbers during storage have increased. The fat content has decreasedduring storage. Based on this, cassava chips with the addition of 1.5 g activated charcoal and packaged with metalized aluminum plastic become the best active packaging system.

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Lee, Kangho, and Seung H. Kang. "Development of Embedded STT-MRAM for Mobile System-on-Chips." IEEE Transactions on Magnetics 47, no. 1 (January 2011): 131–36. http://dx.doi.org/10.1109/tmag.2010.2075920.

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Gong, Shihua, Diyi Zhou, Ziyue Wang, Delong Li, and Huaiqing Lu. "Research on error Analysis of LED chips visual positioning system." IOP Conference Series: Materials Science and Engineering 592 (September 10, 2019): 012149. http://dx.doi.org/10.1088/1757-899x/592/1/012149.

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Laouamri, Oussama, and Chouki Aktouf. "Towards a Complete SNMP-Based Supervision of System-on-Chips." Journal of Network and Systems Management 13, no. 4 (November 15, 2005): 373–86. http://dx.doi.org/10.1007/s10922-005-9001-x.

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Sun, Guanyi, Shengnan Xu, Xu Wang, Dawei Wang, Eugene Tang, Yangdong Deng, and Sun Chan. "A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips." VLSI Design 2011 (September 15, 2011): 1–17. http://dx.doi.org/10.1155/2011/726014.

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Today's System-on-Chips (SoCs) design is extremely challenging because it involves complicated design tradeoffs and heterogeneous design expertise. To explore the large solution space, system architects have to rely on system-level simulators to identify an optimized SoC architecture. In this paper, we propose a system-level simulation framework, System Performance Simulation Implementation Mechanism, or SPSIM. Based on SystemC TLM2.0, the framework consists of an executable SoC model, a simulation tool chain, and a modeling methodology. Compared with the large body of existing research in this area, this work is aimed at delivering a high simulation throughput and, at the same time, guaranteeing a high accuracy on real industrial applications. Integrating the leading TLM techniques, our simulator can attain a simulation speed that is not slower than that of the hardware execution by a factor of 35 on a set of real-world applications. SPSIM incorporates effective timing models, which can achieve a high accuracy after hardware-based calibration. Experimental results on a set of mobile applications proved that the difference between the simulated and measured results of timing performance is within 10%, which in the past can only be attained by cycle-accurate models.

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Liu, Kan, and Yi Fang. "Development of Valve Controlled Microfluidics Based on STM32 Dual-Core ARM." Applied Mechanics and Materials 727-728 (January 2015): 725–28. http://dx.doi.org/10.4028/www.scientific.net/amm.727-728.725.

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This article describes a precisely microfluidic control system based on a dual-core STM32F10x microcontroller. The system consists of 32 independent microfluidic valve controlled output, human-computer interaction display, ethernet module, WIFI module, CAN module, USB module and graphical control interface. Using this microfluidic control system, the biological and medical workers precisely and conveniently control liquid in microfluidic chips. The microfluidic control system would be widely used for microfluidic chips.

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Gehrer, Stefan, and Georg Sigl. "Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs." Journal of Circuits, Systems and Computers 25, no. 01 (November 15, 2015): 1640002. http://dx.doi.org/10.1142/s0218126616400028.

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Physically unclonable functions (PUFs) are an innovative way to generate device unique keys using uncontrollable production tolerances. In this work, we present a method to use PUFs on modern FPGA-based system-on-chips (SoCs). The processor system part of the SoC is used to configure the FPGA part. We propose a reconfigurable PUF design that can be changed by using the partial reconfiguration (PR) feature of modern FPGAs. Multiple ring oscillator PUF (RO PUF) designs are loaded on the same logic blocks of the FPGA in order to make use of different resources, i.e., sources of entropy, on the FPGA. Their frequencies are read out individually and the differences between neighbored oscillators are used to generate a bit response. The responses of each design can be concatenated to a larger response vector that can be used to generate a cryptographic key. We present an implementation that is able to decrease the needed resources by 87.5% on a Xilinx Zynq.

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Floridia, Andrea, and Ernesto Sanchez. "On-line self-test mechanism for Dual-Core Lockstep System-on-Chips." Microelectronics Reliability 112 (September 2020): 113770. http://dx.doi.org/10.1016/j.microrel.2020.113770.

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Tong, Jin Ge, Jian Yun He, Peng Cheng Xie, Jing Hui Zhang, Zeng Qiang Shen, Jia Jia Wang, and Han Zhuo Xu. "Microfluidic Chip Injection Photo Solidification Molding Study on Reaction Kinetics." Key Engineering Materials 814 (July 2019): 481–86. http://dx.doi.org/10.4028/www.scientific.net/kem.814.481.

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Microfluidic chip injection photocuring is a new method for microfluidic chip fabrication. The accuracy of microfluidic chip photocuring has an important impact on the reliability of microfluidic chip. The reaction rate of photocuring system directly affects the final quality and efficiency of microfluidic chip. The rapid reaction rate of photocuring system will lead to poor feeding effect of the reaction system. The forming accuracy is affected, and the reaction rate is too slow, which will increase the forming time and affect the forming efficiency. In this paper, the conversion rate and reaction rate of different active monomers and oligomers used in the formulation system of microfluidic chips were measured on-line. The photocuring reaction kinetics of microfluidic chips was studied, and the influence of the formulation system on the photocuring reaction was explored, which laid a foundation for optimizing the formulation of microfluidic chips.

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Lo, Shu-Cheng, En-Hung Lin, Pei-Kuen Wei, and Wan-Shao Tsai. "A compact imaging spectroscopic system for biomolecular detections on plasmonic chips." Analyst 141, no. 21 (2016): 6126–32. http://dx.doi.org/10.1039/c6an01434h.

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In this study, we demonstrate a compact imaging spectroscopic system for high-throughput detection of biomolecular interactions on plasmonic chips, based on a curved grating as the key element of light diffraction and light focusing.

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Zhang, Hai Wei, Ai Guo Wu, and Q. Z. Ding. "Design of Microfluidic Chip Rapid Laser Carving Worktable." Applied Mechanics and Materials 743 (March 2015): 214–18. http://dx.doi.org/10.4028/www.scientific.net/amm.743.214.

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Miniaturize systems analysis (TAS) is subject to research micromation, automation, portable of the chemical analys from the sample processing system to test. A special worktable for Microfluidic chips achieve to make chips with lithography technology. According to a rapid flow of chips, based on MCS it is complete with the worktable system of hardware, software , control interface, and debugging, etc.

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Sung, Wen-Tsai, Jui-Ho Chen, and Kung-Wei Chang. "Study on a Real-Time BEAM System for Diagnosis Assistance Based on a System on Chips Design." Sensors 13, no. 5 (May 16, 2013): 6552–77. http://dx.doi.org/10.3390/s130506552.

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Vangal, Sriram, Somnath Paul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, James Tschanz, and Vivek De. "Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips." Journal of Low Power Electronics and Applications 10, no. 2 (May 14, 2020): 16. http://dx.doi.org/10.3390/jlpea10020016.

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Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches the threshold voltage (VT) of the CMOS transistors. The improved silicon energy efficiency promises to fit more cores in a given power envelope. As a result, many-core Near-threshold computing (NTC) has emerged as an attractive paradigm. Realizing energy-efficient heterogenous system on chips (SoCs) necessitates key NTV-optimized ingredients, recipes and IP blocks; including CPUs, graphic vector engines, interconnect fabrics and mm-scale microcontroller (MCU) designs. We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs. Evaluation results spanning Intel’s 32-, 22- and 14-nm CMOS technologies across four test chips are presented, confirming substantial energy benefits that scale well with Moore’s law.

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Zheng, Jianfeng, Bichao Bai, and Han Zhang. "Multi-channel drive system of phased array based on DDS chips." Applied Acoustics 182 (November 2021): 108199. http://dx.doi.org/10.1016/j.apacoust.2021.108199.

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Lahiri, K., A. Raghunathan, G. Lakshminarayana, and S. Dey. "Design of High-Performance System-On-Chips Using Communication Architecture Tuners." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 5 (May 2004): 620–36. http://dx.doi.org/10.1109/tcad.2004.826585.

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Lee, Jaehwan John, and Xiang Xiao. "Instant Multiunit Resource Hardware Deadlock Detection Scheme for System-on-Chips." ACM Transactions on Embedded Computing Systems 11, no. 3 (September 2012): 1–24. http://dx.doi.org/10.1145/2345770.2345780.

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Motamedi, Mohammad, Daniel Fong, and Soheil Ghiasi. "Cappuccino: Efficient CNN Inference Software Synthesis for Mobile System-on-Chips." IEEE Embedded Systems Letters 11, no. 1 (March 2019): 9–12. http://dx.doi.org/10.1109/les.2018.2815954.

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Orsila, Heikki, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, and Marko Hännikäinen. "Automated memory-aware application distribution for Multi-processor System-on-Chips." Journal of Systems Architecture 53, no. 11 (November 2007): 795–815. http://dx.doi.org/10.1016/j.sysarc.2007.01.013.

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García-Alonso, Javier, Rawil F. Fakhrullin, Vesselin N. Paunov, Zheng Shen, Joerg D. Hardege, Nicole Pamme, Stephen J. Haswell, and Gillian M. Greenway. "Microscreening toxicity system based on living magnetic yeast and gradient chips." Analytical and Bioanalytical Chemistry 400, no. 4 (October 6, 2010): 1009–13. http://dx.doi.org/10.1007/s00216-010-4241-3.

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Lu, Ruibing, Aiqun Cao, and Cheng-Kok Koh. "SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 1 (January 2007): 69–79. http://dx.doi.org/10.1109/tvlsi.2007.891091.

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Huang, Chao-Da, Jin-Fu Li, and Tsu-Wei Tseng. "ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 10 (October 2007): 1135–43. http://dx.doi.org/10.1109/tvlsi.2007.903940.

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Wu, Xiao. "LED Chips Locating Algorithm Based on Wavelet Transformation." Advanced Materials Research 816-817 (September 2013): 1105–10. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.1105.

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LED chips position is of crucial significance in chip testing, scribing, die spreading, and die bonding. It’s a great solution to indicate electrical characteristics of chips, examine whether the chip pins are up to the standard, and distinguish LED chip quality. Concerning this, an LED chip positioning method based on wavelet transform is proposed in this paper. Firstly, CCD, light and motion control module are adopted to construct and acquire the visual system of LED chip images. Then the images are processed with lowpass filtering and normalization to obtain Hi-Q chips image, and image features are extracted by further using multi-scale wavelet transform. Lastly, high accuracy positioning of LED chips is achieved by employing high-accuracy point pattern matching algorithm. Experimental results show that the LED chip image positioning error is less than 1μm and the position speed is faster than 5 particles per second, which offer new approaches for high-accuracy chip positioning system of detection machines, sorting machines, die bonders, etc.

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Kameyama, Michitaka. "Special Issue on Computer Architecture for Robotics." Journal of Robotics and Mechatronics 2, no. 6 (December 20, 1990): 417. http://dx.doi.org/10.20965/jrm.1990.p0417.

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In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.

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Pan, Hai Peng, Le Wang, and Dong Dong Chen. "Outdoor Personnel Positioning System Based on GPS." Applied Mechanics and Materials 385-386 (August 2013): 1537–40. http://dx.doi.org/10.4028/www.scientific.net/amm.385-386.1537.

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With the comparison of wireless positioning technology such as Wi-Fi, ZigBee, GPS, this paper presents an outdoor personnel positioning system based on GPS. It is composed of electronic wristbands (used for detainees), handsets (used for supervisors) and monitoring software of the host computer. In order to improve the positioning accuracy and reduce power consumption of the system, high-precision GPS chips and low power microcontroller chips are applied. Handsets can exchange data with electronic wristbands through self-prepared communication protocol. It also can work out the distance through a precise latitude and longitude distance algorithm. Finally, the monitoring software will reproduce personnel routes in Google Earth. The system can achieve the positioning of fixed groups and moving groups, which is suitable for the detention center to supervise, escort or chase detainees.

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Li, Jiashen, and Yun Pan. "Optimal scheduling algorithms of system chip power density based on network on chip." Izvestiya vysshikh uchebnykh zavedenii. Fizika, no. 9 (2021): 120–27. http://dx.doi.org/10.17223/00213411/64/9/120.

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The improvement of chip integration leads to the increase of power density of system chips, which leads to the overheating of system chips. When dispatching the power density of system chips, some working modules are selectively closed to avoid all modules on the chip being turned on at the same time and to solve the problem of overheating. Taking 2D grid-on-chip network as the research object, an optimal scheduling algorithm of system-on-chip power density based on network-on-chip (NoC) is proposed. Under the constraints of thermal design power (TDP) and system, dynamic programming algorithm is used to solve the optimal application set throughput allocation from bottom to top by dynamic programming for the number and frequency level of each application configuration processor under the given application set of network-on-chip. On this basis, the simulated annealing algorithm is used to complete the application mapping aiming at heat dissipation effect and communication delay. The open and closed processor layout is determined. After obtaining the layout results, the TDP is adjusted. The maximum TDP constraint is iteratively searched according to the feedback loop of the system over-hot spots, and the power density scheduling performance of the system chip is maximized under this constraint, so as to ensure the system core. At the same time, chip throughput can effectively solve the problem of chip overheating. The experimental results show that the proposed algorithm increases the system chip throughput by about 11%, improves the system throughput loss, and achieves a balance between the system chip power consumption and scheduling time.

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Satya, Ririn Regiana Dwi, Eriyatno Eriyatno, Andes Ismayana, and Marimin Marimin. "Design of traceability system models for potato chips agro-industry based on fuzzy system approach." TELKOMNIKA (Telecommunication Computing Electronics and Control) 20, no. 4 (August 1, 2022): 797. http://dx.doi.org/10.12928/telkomnika.v20i4.23316.

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Li, Xiaolong, Yan Zheng, Jun Cai, and Yunfei Yi. "TrackCC: A Practical Wireless Indoor Localization System Based on Less-Expensive Chips." Sensors 17, no. 6 (June 15, 2017): 1391. http://dx.doi.org/10.3390/s17061391.

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Lee, Kyu-Bae, Jina Park, Eunjin Choi, Mingi Jeon, and Woojoo Lee. "Developing a TEI-Aware PMIC for Ultra-Low-Power System-on-Chips." Energies 15, no. 18 (September 16, 2022): 6780. http://dx.doi.org/10.3390/en15186780.

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As the demand for ultra-low-power (ULP) devices has increased tremendously, system-on-chip (SoC) designs based on ultra-low-voltage (ULV) operation have been receiving great attention. Moreover, research has shown the remarkable potential that even more power savings can be achieved in ULV SoCs by exploiting the temperature effect inversion (TEI) phenomenon, i.e., the delay of the ULV SoCs decreases with increasing temperature. However, TEI-aware low-power (TEI-LP) techniques have a critical limitation in practical terms, in that dedicated power management-integrated circuits (PMICs) have not yet been developed. In other words, it is essential to develop PMICs that automatically bring out the full potential of the TEI-LP techniques as the chip temperature changes. With the aim of designing such PMICs, this paper first conducted a study to find the most suitable DC-DC converter for PMICs and then developed a control algorithm to maximize the effectiveness of the TEI-LP techniques. Furthermore, we have developed a compact hardware controller for the algorithm to operate most energy efficiently on ULP-SoCs.

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Ahmadinia, Ali, and Hernando Fernandez-Canque. "Optimization of reconfigurable multi-core system-on-chips for multi-standard applications." International Journal of Knowledge-based and Intelligent Engineering Systems 15, no. 2 (May 5, 2011): 89–98. http://dx.doi.org/10.3233/kes-2010-0214.

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ZHAO, Peng, Ming YAN, and Si-Kun LI. "Performance Optimization of Application Algorithms for Heterogeneous Multi-Processor System-on-Chips." Journal of Software 22, no. 7 (July 15, 2011): 1475–87. http://dx.doi.org/10.3724/sp.j.1001.2011.03847.

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Chenchang Zhan and Wing-Hung Ki. "Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator for System-on-Chips." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 5 (May 2010): 1017–28. http://dx.doi.org/10.1109/tcsi.2010.2046204.

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Chen, Ming-Fu, Chih-Wen Chen, Chih-Chung Chou, Chih-Yen Chen, and Yen-Chi Chiu. "An Optical Inspection System Development for Defects on Multi-surfaces of Chips." MATEC Web of Conferences 68 (2016): 12003. http://dx.doi.org/10.1051/matecconf/20166812003.

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Wang, Shuo, and Jiliang Luo. "Synthesis of mobile robot control system on embedded chips via Petri nets." Journal of the Chinese Institute of Engineers 41, no. 6 (August 18, 2018): 442–51. http://dx.doi.org/10.1080/02533839.2018.1498022.

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Nourani, M., and A. R. Attarha. "Detecting signal-overshoots for reliability analysis in high-speed system-on-chips." IEEE Transactions on Reliability 51, no. 4 (December 2002): 494–504. http://dx.doi.org/10.1109/tr.2002.804491.

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Lahbib, Younes, Meriam Kallel, Ayoub Dhouib, Maher Hechkel, Antoine Perrin, and Rached Tourki. "System on Chips optimization using ABV and automatic generation of SystemC codes." Microprocessors and Microsystems 31, no. 7 (November 2007): 433–44. http://dx.doi.org/10.1016/j.micpro.2006.12.008.

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Nedjah, Nadia, Lech Jóźwiak, and Luiza de Macedo Mourelle. "Application-specific processors and system-on-chips for embedded and pervasive applications." Microprocessors and Microsystems 37, no. 6-7 (August 2013): 672–73. http://dx.doi.org/10.1016/j.micpro.2013.08.004.

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Yazawa, Yoshiaki, Tadashi Oonishi, Kazuki Watanabe, Akiko Shiratori, Sohei Funaoka, and Masao Fukushima. "System-on-fluidics immunoassay device integrating wireless radio-frequency-identification sensor chips." Journal of Bioscience and Bioengineering 118, no. 3 (September 2014): 344–49. http://dx.doi.org/10.1016/j.jbiosc.2014.02.010.

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Gray, Ian, Gary Plumbridge, and Neil C. Audsley. "Toolchain‐based approach to handling variability in embedded multiprocessor system on chips." IET Computers & Digital Techniques 9, no. 1 (January 2015): 82–92. http://dx.doi.org/10.1049/iet-cdt.2014.0070.

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Journal articles on the topic 'System-on-chips'

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