Relevant bibliographies by topics / System-on-chips

Academic literature on the topic 'System-on-chips'

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Published: 10 December 2022
Last updated: 10 March 2023

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Journal articles on the topic "System-on-chips"

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Koyanagi, M., H. Kurino, Kang Wook Lee, K. Sakuma, N. Miyakawa, and H. Itani. "Future system-on-silicon LSI chips." IEEE Micro 18, no. 4 (1998): 17–22. http://dx.doi.org/10.1109/40.710867.

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Miller, Chris P., Woojung Shin, Eun Hyun Ahn, Hyun Jung Kim, and Deok-Ho Kim. "Engineering Microphysiological Immune System Responses on Chips." Trends in Biotechnology 38, no. 8 (August 2020): 857–72. http://dx.doi.org/10.1016/j.tibtech.2020.01.003.

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Thomas, Anitta, and Shinoj J Vattakuzhi. "Simulation Results for a Crosstalk Avoidance and Low Power Coding Scheme for System on Chips." Bonfring International Journal of Research in Communication Engineering 6, no. 1 (February 29, 2016): 01–05. http://dx.doi.org/10.9756/bijrce.10444.

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Li, Chun Guang, Xiao Ming Ma, and Hai Jun Tang. "Experimental Research on Energy Spectrum Analysis on Chips from Aeroengine Oil System." Applied Mechanics and Materials 635-637 (September 2014): 957–61. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.957.

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Inspection on chips from oil system is an important method for modern aeroengine condition monitoring. Energy spectrum analysis technique is the most widely used and effective method in inspection on metal chips. In this method, size and quantity of chips are observed by scanning electronic microscope and qualitative and quantitative analysis of element contents are finished by energy dispersive spectrometer. Through above experiments, material type of metal chips can be analyzed and material mark can be determined by comparison with the materials list used in the aeroengine. In this article, characteristics and advantages of energy spectrum analysis technology are systematically introduced and typical appearance feature and energy spectrum curve of common l chips are summarized in engineering practice. In addition, problems and prospects of energy spectrum analysis technique are proposed.
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Liu, Kan, and Hao You. "Real-Time Micro-Fluidic Chip Pressure Control System Base on the Optical Interference." Applied Mechanics and Materials 494-495 (February 2014): 1274–77. http://dx.doi.org/10.4028/www.scientific.net/amm.494-495.1274.

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This article introduces a measurement system based on LabVIEW used for optical interference fringe on micro-fluidic chips. This system mainly uses cameras to capture real-time images of wedge interference fringe on micro-fluidic chips, then the collected images will be binarized by LabVIEW. The processed images will be divided by zone , determine the flatness and gap thickness of the micro-fluidic chips by interference fringes with different directions of deflection and numbers. Finally, feedback from measured data will be used to adjust the flatness and gap thickness of micro-fluidic chips in order to meet the requirement of tests.
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Xiao, Hao, Huajuan Zhang, Fen Ge, and Ning Wu. "A MapReduce architecture for embedded multiprocessor system-on-chips." IEICE Electronics Express 13, no. 2 (2016): 20151025. http://dx.doi.org/10.1587/elex.13.20151025.

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PIONTECK, THILO, CARSTEN ALBRECHT, ROMAN KOCH, and ERIK MAEHLE. "ADAPTIVE COMMUNICATION ARCHITECTURES FOR RUNTIME RECONFIGURABLE SYSTEM-ON-CHIPS." Parallel Processing Letters 18, no. 02 (June 2008): 275–89. http://dx.doi.org/10.1142/s0129626408003387.

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For exploiting the inherent parallelism enclosed in System-on-Chip designs, special architectural prerequisites have to be met. These prerequisites mainly affect the communication infrastructure, as parallel processing of all hardware modules accounts for a continuous and sufficient provision of data. While traditional communication architectures may fulfill these requirements for a fixed System-on-Chip design, changing composition, number and locations of processing modules in runtime reconfigurable System-on-Chips require new communication paradigms. Special communication architectures especially for use in runtime reconfigurable System-on-Chip designs are presented in this article. Their analysis provides a basis for the design of CoNoChi, a runtime reconfigurable Network-on-Chip dedicated for the usage in FPGA-based designs. CoNoChi supports the adaptation of the network topology during runtime by providing mechanisms to add or remove switches from the network during runtime without stopping or stalling the network. The applicability of CoNoChi is shown on the basis of a complex runtime reconfigurable System-on-Chip for networking applications. Prototyping results demonstrate that CoNoChi is a promising alternative to existing communication architectures supporting both a high degree of adaptability during runtime and a high concurrency of data transfers.
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Javaid, Haris, Aleksander Ignjatovic, and Sri Parameswaran. "Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs)." IEEE Transactions on Parallel and Distributed Systems 25, no. 8 (August 2014): 2159–68. http://dx.doi.org/10.1109/tpds.2013.268.

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Ravi, Srivaths, Rubin Parekhji, and Jayashree Saxena. "Low Power Test for Nanometer System-on-Chips (SoCs)." Journal of Low Power Electronics 4, no. 1 (April 1, 2008): 81–100. http://dx.doi.org/10.1166/jolpe.2008.155.

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Brekling, Aske, Michael R. Hansen, and Jan Madsen. "Models and formal verification of multiprocessor system-on-chips." Journal of Logic and Algebraic Programming 77, no. 1-2 (September 2008): 1–19. http://dx.doi.org/10.1016/j.jlap.2008.05.002.

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Dissertations / Theses on the topic "System-on-chips"

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Ludewig, Ralf. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips /." Aachen : Shaker, 2006. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=014632870&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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An, Xin. "High level design and control of adaptive multiprocessor system-on-chips." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENM023/document.

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La conception de systèmes embarqués modernes est de plus en plus complexe, car plus de fonctionnalités sont intégrées dans ces systèmes. En même temps, afin de répondre aux exigences de calcul tout en conservant une consommation d'énergie de faible niveau, MPSoCs sont apparus comme les principales solutions pour tels systèmes embarqués. En outre, les systèmes embarqués sont de plus en plus adaptatifs, comme l’adaptabilité peut apporter un certain nombre d'avantages, tels que la flexibilité du logiciel et l'efficacité énergétique. Cette thèse vise la conception sécuritaire de ces MPSoCs adaptatifs. Tout d'abord, chaque configuration de système doit être analysée en ce qui concerne ses propriétés fonctionnelles et non fonctionnelles. Nous présentons un cadre abstraite de conception et d’analyse qui permet des décisions d’implémentation plus rapide et plus rentable. Ce cadre est conçu comme un support de raisonnement intermédiaire pour les environnements de co-conception de logiciel / matériel au niveau de système. Il peut élaguer l'espace de conception à sa plus grande portée, et identifier les candidats de solutions de conception de manière rapide et efficace. Dans ce cadre, nous utilisons un codage basé sur l’horloge abstrait pour modéliser les comportements du système. Différents scénarios d'applications de mapping et de planification sur MPSoCs sont analysés via les traces d'horloge qui représentent les simulations du système. Les propriétés d'intérêt sont l’exactitude du comportement fonctionnel, la performance temporelle et la consommation d'énergie. Deuxièmement, la gestion de la reconfiguration de MPSoCs adaptatifs doit être abordée. Nous sommes particulièrement intéressés par les MPSoCs implémentés sur des architectures reconfigurables de hardware (ex. FPGA tissus) qui offrent une bonne flexibilité et une efficacité de calcul pour les MPSoCs adaptatifs. Nous proposons un cadre général de conception basésur la technique de la synthèse de contrôleurs discrets (SCD) pour résoudre ce problème. L’avantage principal de cette technique est qu'elle permet une synthèse d'un contrôleur automatique vis-à-vis d’une spécification donnée des objectifs de contrôle. Dans ce cadre, le comportement de reconfiguration du système est modélisé en termes d'automates synchrones en parallèle. Le problème de calcul de la gestion reconfiguration vis-à-vis de multiples objectifs concernant, par exemple, les usages des ressources, la performance et la consommation d’énergie est codé comme un problème de SCD . Le langage de programmation BZR existant et l’outil Sigali sont employés pour effectuer SCD et générer un contrôleur qui satisfait aux exigences du système. Finalement, nous étudions deux façons différentes de combiner les deux cadres de conception proposées pour MPSoCs adaptatifs. Tout d'abord, ils sont combinés pour construire un flot de conception complet pour MPSoCs adaptatifs. Deuxièmement, ils sont combinés pour présenter la façon dont le gestionnaire d'exécution conçu dans le second cadre peut être intégré dans le premier cadre de sorte que les simulations de haut niveau peuvent être effectuées pour évaluer le gestionnaire d'exécution
The design of modern embedded systems is getting more and more complex, as more func- tionality is integrated into these systems. At the same time, in order to meet the compu- tational requirements while keeping a low level power consumption, MPSoCs have emerged as the main solutions for such embedded systems. Furthermore, embedded systems are be- coming more and more adaptive, as the adaptivity can bring a number of benefits, such as software flexibility and energy efficiency. This thesis targets the safe design of such adaptive MPSoCs. First, each system configuration must be analyzed concerning its functional and non- functional properties. We present an abstract design and analysis framework, which allows for faster and cost-effective implementation decisions. This framework is intended as an intermediate reasoning support for system level software/hardware co-design environments. It can prune the design space at its largest, and identify candidate design solutions in a fast and efficient way. In the framework, we use an abstract clock-based encoding to model system behaviors. Different mapping and scheduling scenarios of applications on MPSoCs are analyzed via clock traces representing system simulations. Among properties of interest are functional behavioral correctness, temporal performance and energy consumption. Second, the reconfiguration management of adaptive MPSoCs must be addressed. We are specially interested in MPSoCs implemented on reconfigurable hardware architectures (i.e., FPGA fabrics), which provide a good flexibility and computational efficiency for adap- tive MPSoCs. We propose a general design framework based on the discrete controller syn- thesis (DCS) technique to address this issue. The main advantage of this technique is that it allows the automatic controller synthesis w.r.t. a given specification of control objectives. In the framework, the system reconfiguration behavior is modeled in terms of synchronous parallel automata. The reconfiguration management computation problem w.r.t. multiple objectives regarding e.g., resource usages, performance and power consumption is encoded as a DCS problem. The existing BZR programming language and Sigali tool are employed to perform DCS and generate a controller that satisfies the system requirements. Finally, we investigate two different ways of combining the two proposed design frame- works for adaptive MPSoCs. Firstly, they are combined to construct a complete design flow for adaptive MPSoCs. Secondly, they are combined to present how the designed run-time manager by the second framework can be integrated into the first framework so that high level simulations can be performed to assess the run-time manager
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Bai, Xiaoliang. "Modeling and testing for signal integrity in nanometer system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3112828.

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Chen, Li. "Software-based self-test and diagnosis for processors and system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3090436.

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Rech, Paolo. "Soft Errors Induced By Neutrons and Alpha Particles in System on Chips." Doctoral thesis, Università degli studi di Padova, 2010. http://hdl.handle.net/11577/3421895.

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This Manuscript presents a new low-cost test setup for the radiation tests of System on Chips composed of different functional modules of different nature. Particular attention is given to radiation experiments results of embedded SRAM cores, embedded logic cores and embedded microprocessor cores, highlighting the dissimilar test protocols required to characterize their sensitivity to radiation. The main issues when testing a System on Chip are the cores reduced accessibility and the physical constraints test facilities may impose to the test setup. Manufacturers heavily employ Design for Testability techniques, based on built-in test structures, to enable exhaustive devices testing while minimizing application costs. We reused some of the Design for Testability built-in structures to deeply characterize the cores composing the System on Chip and the overall chip behaviours when exposed to radiation. Our strategy can be applied to any kind of integrated core, and we also present some guidelines on how built-in structures may be fruitfully applied to radiation experiments. Moreover, the monolithic shape of our test board makes it easy to be mounted in most of available particle accelerators chambers or radiation test facilities. As the test structures are built-in and thanks to the efficient interfaces strategy that takes advantage of both JTAG and Wrappers standards, tests are performed at high frequency, thus avoiding Single Event Transients underestimation, but without the need of high-speed connections between a host PC and the DUT, drastically reducing the overall setup costs. This thesis also shows and discusses the results gained during massive radiation experiments campaigns on the available System on Chip manufactured by STMicroelectronics in a 90 nm CMOS technology. As device is meant to be part of a complex automotive design, it may be affected by ground level radiation. We then exposed the chips both to neutron and alpha particles fluxes. With our low-cost setup we measured the SRAM core cross section to alphas and neutrons, and found out that the former one is higher than the latter. We have also characterized the microprocessors behaviour when exposed to alphas. The static test stated that registers flip-flops have a higher radiation induced error rate with respect to code and user RAM one. This result is of great importance, and should be taken into account when building a fault-injection platform. To understand how the corruption of the different memory resources affects codes executions, we designed different benchmark codes and performed a dynamic test. Results demonstrate that, in a typical application, the bit-flips in the code RAM are definitely predominant with respect to the ones in registers. Moreover, we show how code RAM and register bits are not always critical, and their corruption does not necessarily propagate to outputs. Finally, we have considered hardening techniques efficiency and costs. In particular, we have studied how Design For Manufacturing layout modifications and Triple Module Redundancy affect the radiation sensitivity of microprocessors. We considered chips built with different Design For Manufacturing maturity levels, and experimental results demonstrate that an higher level of optimization enhances the resilience to alpha radiation. Hardening techniques, however, come to a cost. The decision on which hardening technique to adopt when building a complex device is a hard-earned trade-off between costs, performance and, of course, reliability. Mitigation strategies for a product then depends on its requirements and on its mission environment.
Questa tesi presenta un innovativo setup a basso costo per effettuare dei test sotto radiazione di System on Chips in cui siano integrati moduli di diversa natura e con diverse funzionalità. In particolare sono stati svolti numerosi test sotto radiazione di memorie SRAM integrate, di moduli logici integrati e di microprocessori integrati, analizzando i diversi protocolli di test necessari per poter caratterizzare al meglio la loro sensibilità alla radiazione. Uno dei problemi maggiori che si riscontrano quando si deve testare un System on Chip è la ridotta accessibilità dei vari moduli integrati e i vincoli fisici che devono essere rispettati per effettuare il test stesso e che rendono le procedure di analisi molto difficili. I costruttori, per riuscire a verificare la funzionalità dei vari moduli integrati, usano molto spesso delle tecniche chiamate Design for Testability bastate su strutture di test integrate che permettono un’esaustiva verifica della funzionalità dei moduli minimizzando allo stesso tempo i costi del test. Durante gli esperimenti presentati in questo lavoro abbiamo riutilizzato alcune strutture integrate del tipo Design for Testability per caratterizzare nel dettaglio sia tutti i singoli moduli che compongono un System on Chip che il comportamento globale del dispositivo quando viene esposto a radiazione. La strategia che è proposta in questa tesi può essere generalizzata e applicata a qualunque tipo di modulo integrato e sono presentati anche alcuni suggerimenti sul come applicare le strutture di test DfT agli esperimenti di radiazione. Quando si effettua un esperimenti di radiazione tipicamente ci sono diversi vincoli che, in base al laboratorio in cui gli esperimenti vengono eseguiti, possono essere imposti al setup di test. La scheda di test che abbiamo sviluppato ha una forma monolitica, che la rende facile da posizionare nella maggior parte delle camere di irraggiamento degli acceleratori di particelle utilizzati per questo tipo di esperienze. Inoltre, grazie da un lato all’integrazione delle strutture di test nel System on Chip da caratterizzare e, dall’altro, ad una strategia d’interfaccia che si basa sia sul JTAG che sui Wrappers, i test possono essere eseguiti ad alta frequenza usando però solamente connessioni lente fra un PC e il dispositivo da testare, diminuendo così drasticamente il costo globale degli esperimenti. Questa tesi mostra e discute i risultati ottenuti da molte campagne di esperimenti di radiazione su un System on Chip costruito in tecnologia CMOS a 90 nm da STMicroelectronics. Tale dispositivo è stato pensato e realizzato per essere parte di un complesso progetto automotive; ci siamo dunque focalizzati sulle problematiche derivanti dall’impatto che la radiazione terrestre può avere in questo dispositivo. Abbiamo quindi esposto il chip sia a flussi di neutroni che di particelle alfa. Grazie ai dati ottenuti dagli esperimenti, abbiamo calcolato la sensibilità del modulo SRAM sia a particelle alfa che a neutroni, e abbiamo scoperto che quest’ultima è decisamente inferiore della prima. Abbiamo quindi caratterizzato il comportamento del microprocessore quando è esposto a particelle alfa. Il test statico ha dimostrato che i flip-flop che costituiscono i registri interni del microprocessore hanno un tasso di errore indotto da radiazione più elevato rispetto al modulo memoria utente e memoria codice. Questo risultato è di grande importanza e deve essere considerato, per esempio, quando si costruisce una piattaforma di fault-injection. Per effettuare il test dinamico del microprocessore abbiamo costruito due diversi codici di riferimento, in modo da capire come la corruzione delle riverse risorse di memorizzazione influenzi l’esecuzione del codice. I risultati ottenuti dimostrano che, in una tipica applicazione, gli errori nella memoria codice sono decisamente predominanti rispetto a quelli nei registri interni. Inoltre abbiamo visto che i bit di memoria codice e dei registri non sono sempre critici, e la loro corruzione non necessariamente si propaga all’uscita. Infine, abbiamo considerato l’efficacia e i costi di diverse tecniche di irrobustimento. In particolare, abbiamo studiato come l’ottimizzazione del layout proposta del Design For Manufacturing o la Triple Module Redundancy influenzino la sensibilità alla radiazione del microprocessore. Abbiamo considerato dei chip costruiti con diversi livelli di maturità del Design For Manufacturing e i risultati sperimentali dimostrano che un più alto livello di ottimizzazione aumenta la resistenza del dispositivo alla radiazione alfa. Le tecniche di irrobustimento, comunque, hanno un costo. La decisione su quale tecnica adottare quando si costruisce un dispositivo complesso è un trade-off fra costi, performance e, ovviamente, affidabilità. Le strategie da adottare per un particolare prodotto dipendono quindi dai suoi requisiti e dall’ambiente in cui dovrà essere impiegato.
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Sunwoo, John Stroud Charles E. "Built-In Self-Test of programmable resources in microcontroller based System-on-Chips." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/SUNWOO_JOHN_31.pdf.

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Ludewig, Ralf [Verfasser]. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips / Ralf Ludewig." Aachen : Shaker, 2006. http://d-nb.info/118658789X/34.

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SEU, GIOVANNI PIETRO. "Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces." Doctoral thesis, Università degli studi di Genova, 2019. http://hdl.handle.net/11567/943352.

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High-density microelectrode arrays (HDMEAs) feature thousands of recording electrodes in a single chip with an area of few square millimeters. The obtained electrode density is comparable and even higher than the typical density of neuronal cells in cortical cultures. Commercially available HDMEA-based acquisition systems are able to record the neural activity from the whole array at the same time with submillisecond resolution. These devices are a very promising tool and are increasingly used in neuroscience to tackle fundamental questions regarding the complex dynamics of neural networks. Even if electrical or optical stimulation is generally an available feature of such systems, they lack the capability of creating a closed-loop between the biological neural activity and the artificial system. Stimuli are usually sent in an open-loop manner, thus violating the inherent working basis of neural circuits that in nature are constantly reacting to the external environment. This forbids to unravel the real mechanisms behind the behavior of neural networks. The primary objective of this PhD work is to overcome such limitation by creating a fullyreconfigurable processing system capable of providing real-time feedback to the ongoing neural activity recorded with HDMEA platforms. The potentiality of modern heterogeneous FPGAs has been exploited to realize the system. In particular, the Xilinx Zynq All Programmable System on Chip (APSoC) has been used. The device features reconfigurable logic, specialized hardwired blocks, and a dual-core ARM-based processor; the synergy of these components allows to achieve high elaboration performances while maintaining a high level of flexibility and adaptivity. The developed system has been embedded in an acquisition and stimulation setup featuring the following platforms: • 3·Brain BioCam X, a state-of-the-art HDMEA-based acquisition platform capable of recording in parallel from 4096 electrodes at 18 kHz per electrode. • PlexStim™ Electrical Stimulator System, able to generate electrical stimuli with custom waveforms to 16 different output channels. • Texas Instruments DLP® LightCrafter™ Evaluation Module, capable of projecting 608x684 pixels images with a refresh rate of 60 Hz; it holds the function of optical stimulation. All the features of the system, such as band-pass filtering and spike detection of all the recorded channels, have been validated by means of ex vivo experiments. Very low-latency has been achieved while processing the whole input data stream in real-time. In the case of electrical stimulation the total latency is below 2 ms; when optical stimuli are needed, instead, the total latency is a little higher, being 21 ms in the worst case. The final setup is ready to be used to infer cellular properties by means of closed-loop experiments. As a proof of this concept, it has been successfully used for the clustering and classification of retinal ganglion cells (RGCs) in mice retina. For this experiment, the light-evoked spikes from thousands of RGCs have been correctly recorded and analyzed in real-time. Around 90% of the total clusters have been classified as ON- or OFF-type cells. In addition to the closed-loop system, a denoising prototype has been developed. The main idea is to exploit oversampling techniques to reduce the thermal noise recorded by HDMEAbased acquisition systems. The prototype is capable of processing in real-time all the input signals from the BioCam X, and it is currently being tested to evaluate the performance in terms of signal-to-noise-ratio improvement.
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Zhao, Yi. "Fault modeling and on-line testing for deep-submicron noise interference in system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3127634.

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Liu, Meng. "Real-Time Communication over Wormhole-Switched On-Chip Networks." Doctoral thesis, Mälardalens högskola, Inbyggda system, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35316.

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In a modern industrial system, the requirement on computational capacity has increased dramatically, in order to support a higher number of functionalities, to process a larger amount of data or to make faster and safer run-time decisions. Instead of using a traditional single-core processor where threads can only be executed sequentially, multi-core and many-core processors are gaining more and more attentions nowadays. In a multi-core processor, software programs can be executed in parallel, which can thus boost the computational performance. Many-core processors are specialized multi-core processors with a larger number of cores which are designed to achieve a higher degree of parallel processing. An on-chip communication bus is a central intersection used for data-exchange between cores, memory and I/O in most multi-core processors. As the number of cores increases, more contention can occur on the communication bus which raises a bottleneck of the overall performance. Therefore, in order to reduce contention incurred on the communication bus, a many-core processor typically employs a Network-on-Chip (NoC) to achieve data-exchange. Real-time embedded systems have been widely utilized for decades. In addition to the correctness of functionalities, timeliness is also an important factor in such systems. Violation of specific timing requirements can result in performance degradation or even fatal problems. While executing real-time applications on many-core processors, the timeliness of a NoC, as a communication subsystem, is essential as well. Unfortunately, many real-time system designs over-provision resources to guarantee the fulfillment of timing requirements, which can lead to significant resource waste. For example, analysis of a NoC design yields that the network is already saturated (i.e. accepting more traffic can incur requirement violation), however, in reality the network actually has the capacity to admit more traffic. In this thesis, we target such resource wasting problems related to design and analysis of NoCs that are used in real-time systems. We propose a number of solutions to improve the schedulability of real-time traffic over wormhole-switched NoCs in order to further improve the resource utilization of the whole system. The solutions focus mainly on two aspects: (1) providing more accurate and efficient time analyses; (2) proposing more cost-effective scheduling methods.
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Books on the topic "System-on-chips"

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Fokin, Sergey. Improvement of technical means for processing waste from logging operations for fuel chips in felling conditions. ru: INFRA-M Academic Publishing LLC., 2017. http://dx.doi.org/10.12737/24135.

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Currently, wood waste in the form of a dissected crown on the ground and the root fraction of the tree's biomass in the ground remain in felling areas, becoming potentially dangerous combustible materials in the event of forest fires, as well as obstacles to reforestation activities, and possible foci of infections. Shredding wood waste into wood chips will solve the problem of their disposal by using fuel chips as an additional source of heat energy. In the present work, the influence of design and operational parameters of milling machines with a modernized hydraulic system and equipped with active working bodies on the process of shredding wood waste is established. The annual economic effect from the introduction of the developed complex of wood waste shredding machines and economic indicators from the use of fuel chips are given. This publication is intended for undergraduates and postgraduates engaged in scientific research in the field of forestry mechanization.
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Manfred, Glesner, ed. VLSI-SOC, from systems to chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany. New York: Springer, 2006.

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Indrusiak, Leandro, Hans Eveking, Ricardo Reis, Manfred Glesner, and Vincent Mooney. VLSI-SOC : from Systems to Chips: IFIP TC 10/WG 10. 5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip , December 1-3, 2003, Darmstadt, Germany. Springer, 2006.

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Indrusiak, Leandro, Hans Eveking, Ricardo Reis, Manfred Glesner, and Vincent Mooney. VLSI-SOC : from Systems to Chips: IFIP TC 10/WG 10. 5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip , December 1-3, 2003, Darmstadt, Germany. Springer, 2010.

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(Editor), Manfred Glesner, Ricardo Reis (Editor), Leandro Indrusiak (Editor), Vincent Mooney (Editor), and Hans Eveking (Editor), eds. VLSI-SOC: From Systems to Chips: IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-SoC 2003), ... Federation for Information Processing). Springer, 2006.

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Cameron, James. Collapse of the Consensus and the Struggle for Coherence, 1969–1970. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780190459925.003.0005.

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This chapter shows how Richard Nixon and his national security advisor, Henry Kissinger, were forced to change their strategy for nuclear arms control based on the collapse of the US congressional consensus behind nuclear superiority. Nixon entered office with strong convictions on the importance of nuclear superiority for supporting the United States’ national security commitments. Nixon also saw US technological advantages in ballistic missile defenses as one of the main bargaining chips to cap the growth of Soviet offensive forces at the upcoming Strategic Arms Limitation Talks. This strategy for détente was thrown into disarray, however, when Congress signaled its lack of support for a new ballistic missile defense system and the strategy of nuclear superiority. Nixon and Kissinger then changed tack, attempting to conclude a quick arms limitation agreement through backchannel negotiations with Soviet Ambassador Anatoly Dobrynin. This initiative failed, weakening the American hand at the formal talks.
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Low-Power NoC for High-Performance SoC Design (System-on-Chip Design and Technologies). CRC, 2008.

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Book chapters on the topic "System-on-chips"

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Basu, Kanad. "Security Verification of System-on-Chips (SoCs)." In Encyclopedia of Cryptography, Security and Privacy, 1–3. Berlin, Heidelberg: Springer Berlin Heidelberg, 2021. http://dx.doi.org/10.1007/978-3-642-27739-9_1647-1.

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Bromberger, Michael, Steffen Ehrle, Michael Scharrer, Lukas Erlinghagen, and Jens Schick. "OpenCL-Based 6D-Vision on Heterogeneous System on Chips." In Architecture of Computing Systems - ARCS 2017, 33–46. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54999-6_3.

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Liu, Feng, and Vipin Chaudhary. "A Practical OpenMP Compiler for System on Chips." In OpenMP Shared Memory Parallel Programming, 54–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-45009-2_5.

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Esposito, Stefano, and Massimo Violante. "Mitigating Soft Errors in Processors Cores Embedded in System-on Programmable-Chips." In FPGAs and Parallel Architectures for Aerospace Applications, 219–38. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14352-1_15.

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Stefanov, Todor, Andy Pimentel, and Hristo Nikolov. "DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips." In Handbook of Hardware/Software Codesign, 983–1018. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_30.

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Stefanov, Todor, Andy Pimentel, and Hristo Nikolov. "Daedalus: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips." In Handbook of Hardware/Software Codesign, 1–36. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_30-1.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "Introduction to Design of System on Chips and Future Trends in VLSI." In SoC Physical Design, 1–20. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-98112-9_1.

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Han, Peicen, Zhaohui Ye, and Shiyuan Yang. "The Design and Implementation of Network Video Surveillance System Based on Davinci Chips." In Communications in Computer and Information Science, 296–302. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22418-8_41.

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Salehi, Mohammad, Florian Kriebel, Semeen Rehman, and Muhammad Shafique. "Power-Aware Fault-Tolerance for Embedded Systems." In Dependable Embedded Systems, 565–88. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_24.

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AbstractPower-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (RMT). In dark silicon chips, the maximum number of cores that can simultaneously be powered-on (at the full performance level) is constrained by the thermal design power (TDP). The rest of the cores have to be power-gated (i.e., stay “dark”), or the cores have to operate at a lower performance level. It has been predicted that about 25–50% of a many-core chip can potentially be “dark.” In this chapter, a system-level power–reliability management technique is presented. The technique jointly considers multiple hardening modes at the software and hardware levels, each offering distinct power, reliability, and performance properties. Also, a framework for the system-level optimization is introduced which considers different power–reliability–performance management problems for many-core processors depending upon the target system and user constraints.
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Kirchner, Aljoscha. "Einleitung." In Entwicklung von Methoden zur abstrakten Modellierung von Automotive Systems-on-Chips, 1–5. Wiesbaden: Springer Fachmedien Wiesbaden, 2022. http://dx.doi.org/10.1007/978-3-658-38437-1_1.

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ZusammenfassungEs sind die großen Technologietrends der heutigen Zeit, welche die Automobilbranche nach wie vor zu einem der großen Treiber der Innovationsentwicklung werden lässt. Dabei ist es neben der Digitalisierung und der Elektrifizierung des Automobils insbesondere die Entwicklung des autonomen Fahrens, welche die Komplexität der Anforderungen stetig steigen lässt. Aus den steigenden Anforderungen in der Automobilbranche resultieren steigende Anforderungen bei den Zulieferern. Ziel dieser Arbeit ist die Effizienzsteigerung in der Entwicklung von Automotive System-on-Chips durch die direkte oder indirekte Senkung der entstehenden Aufwände. Hierzu soll eine Methode entwickelt werden, mit dem Ziel, die bestehenden Defizite des aktuellen Entwicklungs-Flows in der Automotive-SoC-Entwicklung zu minimieren. Ein besonderer Fokus der Arbeit liegt dabei auf dem Erstellen und Pflegen der Spezifikationsdokumente.
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Conference papers on the topic "System-on-chips"

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Joseph, Jan Moritz, Dominik Ermel, Lennart Bamberg, Alberto Garcia Oritz, and Thilo Pionteck. "System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips." In 2019 IEEE 37th International Conference on Computer Design (ICCD). IEEE, 2019. http://dx.doi.org/10.1109/iccd46524.2019.00064.

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Tshagharyan, G., G. Harutyunyan, S. Shoukourian, and Y. Zorian. "Securing test infrastructure of system-on-chips." In 2016 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2016. http://dx.doi.org/10.1109/ewdts.2016.7807696.

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Ejnioui, Abdel. "Runtime Adaptation in Reconfigurable System-on-Chips." In 2009 International Conference on Parallel Processing Workshops (ICPPW). IEEE, 2009. http://dx.doi.org/10.1109/icppw.2009.53.

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Yi Ni, Wai Sum Mong, and Jianwen Zhu. "On virtual prototyping of embedded system-on-chips." In 2011 IEEE 9th International Conference on ASIC (ASICON 2011). IEEE, 2011. http://dx.doi.org/10.1109/asicon.2011.6157402.

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Meinhardt, Cristina, Ricardo Reis, Massimo Violante, and Matteo Sonza Reorda. "Recovery scheme for hardening system on programmable chips." In 2009 10th Latin American Test Workshop. IEEE, 2009. http://dx.doi.org/10.1109/latw.2009.4813816.

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Eychenne, Ch, and Y. Zorian. "An effective functional safety infrastructure for system-on-chips." In 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE, 2017. http://dx.doi.org/10.1109/iolts.2017.8046235.

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Tenentes, Vasileios, Daniele Rossi, and Bashir M. Al-Hashimi. "Collective-Aware System-on-Chips for Dependable IoT Applications." In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE, 2018. http://dx.doi.org/10.1109/iolts.2018.8474172.

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Yousuf, Shaon, Adam Jacobs, and Ann Gordon-Ross. "Partially reconfigurable system-on-chips for adaptive fault tolerance." In 2011 International Conference on Field-Programmable Technology (FPT). IEEE, 2011. http://dx.doi.org/10.1109/fpt.2011.6132708.

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Gharehbaghi, Amir Masoud, and Masahiro Fujita. "Transaction-based debugging of system-on-chips with patterns." In 2009 IEEE International Conference on Computer Design (ICCD 2009). IEEE, 2009. http://dx.doi.org/10.1109/iccd.2009.5413157.

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Arda, Samet E., Anish NK, A. Alper Goksoy, Joshua Mack, Nirmal Kumbhare, Anderson L. Sartor, Ali Akoglu, Radu Marculescu, and Umit Y. Ogras. "A simulation framework for domain-specific system-on-chips." In CODES/ISSS '19: International Conference on Hardware/Software Codesign and System Synthesis. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3349567.3351719.

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